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clk: Add basic clock support for esp32h2

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This commit is contained in:
Song Ruo Jing
2023-01-03 11:00:32 +08:00
parent b23eb428d1
commit 981d6a67b0
9 changed files with 137 additions and 149 deletions
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6
components/hal/esp32h2/include/hal/uart_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -120,7 +120,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, uart_sclk_t source_clk)
{
switch (source_clk) {
default:
case UART_SCLK_APB:
case UART_SCLK_PLL_F48M:
hw->clk_conf.sclk_sel = 1;
break;
case UART_SCLK_RTC:
@@ -145,7 +145,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, uart_sclk_t *source_clk)
switch (hw->clk_conf.sclk_sel) {
default:
case 1:
*source_clk = UART_SCLK_APB;
*source_clk = UART_SCLK_PLL_F48M;
break;
case 2:
*source_clk = UART_SCLK_RTC;