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Merge branch 'feature/esp32h2_clock_basic_support' into 'master'
clk: Add basic clock support for esp32h2 Closes IDF-6265 and IDF-5973 See merge request espressif/esp-idf!21943
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@@ -33,8 +33,8 @@ __attribute__((weak)) void bootloader_clock_configure(void)
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// and will be done with the bootloader much earlier than UART FIFO is empty.
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esp_rom_uart_tx_wait_idle(0);
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/* Set CPU to 80MHz. Keep other clocks unmodified. */
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int cpu_freq_mhz = 80;
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/* Set CPU to a higher certain frequency. Keep other clocks unmodified. */
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int cpu_freq_mhz = CPU_CLK_FREQ_MHZ_BTLD;
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#if CONFIG_IDF_TARGET_ESP32
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/* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
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@@ -46,8 +46,6 @@ __attribute__((weak)) void bootloader_clock_configure(void)
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clk_ll_cpu_get_freq_mhz_from_pll() == CLK_LL_PLL_240M_FREQ_MHZ) {
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cpu_freq_mhz = 240;
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}
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#elif CONFIG_IDF_TARGET_ESP32H4
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cpu_freq_mhz = 64;
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#endif
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if (esp_rom_get_reset_reason(0) != RESET_REASON_CPU0_SW || rtc_clk_apb_freq_get() < APB_CLK_FREQ) {
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@@ -114,7 +112,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
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SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_ANA_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_ANA_BOD_MODE0_LP_INT_CLR); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_WAKEUP_INT_CLR); /* SLP_REJECT */
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SET_PERI_REG_MASK(PMU_SOC_SLEEP_REJECT_INT_CLR, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */
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SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SOC_SLEEP_REJECT_INT_CLR); /* SLP_WAKEUP */
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#else
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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@@ -43,7 +43,7 @@
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#include "hal/cache_hal.h"
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#include "soc/lp_wdt_reg.h"
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#include "hal/efuse_hal.h"
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#include "modem/modem_lpcon_reg.h"
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static const char *TAG = "boot.esp32h2";
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@@ -86,8 +86,9 @@ static void bootloader_super_wdt_auto_feed(void)
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static inline void bootloader_hardware_init(void)
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{
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// ESP32H2-TODO: IDF-5990
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SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO);
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// TODO: IDF-6267
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/* Enable analog i2c master clock */
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SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
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}
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static inline void bootloader_ana_reset_config(void)
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