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spi_flash: add support for ext flash

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This commit is contained in:
Cao Sen Miao
2021-06-21 19:43:51 +08:00
parent c0cf45b118
commit 992de2750e
10 changed files with 78 additions and 46 deletions
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2
components/soc/esp32s3/include/soc/spi_caps.h
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@@ -28,7 +28,7 @@
// Peripheral supports DIO, DOUT, QIO, or QOUT
// VSPI (SPI3) only support 1-bit mode
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2)
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
// Peripheral supports output given level during its "dummy phase"
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1

8
components/soc/esp32s3/spi_periph.c
View File

@@ -73,12 +73,12 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
.spid_out = SPI3_D_OUT_IDX,
.spiq_out = SPI3_Q_OUT_IDX,
//SPI3 doesn't have wp and hd signals
.spiwp_out = -1,
.spihd_out = -1,
.spiwp_out = SPI3_WP_OUT_IDX,
.spihd_out = SPI3_HD_OUT_IDX,
.spid_in = SPI3_D_IN_IDX,
.spiq_in = SPI3_Q_IN_IDX,
.spiwp_in = -1,
.spihd_in = -1,
.spiwp_in = SPI3_WP_IN_IDX,
.spihd_in = SPI3_HD_IN_IDX,
.spics_out = {SPI3_CS0_OUT_IDX, SPI3_CS1_OUT_IDX, SPI3_CS2_OUT_IDX},
.spics_in = SPI3_CS0_IN_IDX,
//SPI3 doesn't have iomux pins