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esp32s2 riscv ulp: Ensure reset vector is always at offset 0x0

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Previous linker script relied on nothing else using the .text section

As reported at https://esp32.com/viewtopic.php?f=2&t=20734&p=75997
This commit is contained in:
Angus Gratton
2021-05-05 17:53:47 +10:00
parent 788312a009
commit 997c07c2ee
2 changed files with 4 additions and 1 deletions
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1
components/ulp/ld/esp32s2.ulp.riscv.ld
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@@ -12,6 +12,7 @@ SECTIONS
. = ORIGIN(ram); . = ORIGIN(ram);
.text : .text :
{ {
*start.S.obj(.text.vectors) /* Default reset vector must link to offset 0x0 */
*(.text) *(.text)
*(.text*) *(.text*)
} >ram } >ram

4
components/ulp/ulp_riscv/start.S
View File

@@ -1,4 +1,4 @@
.section .text .section .text.vectors
.global irq_vector .global irq_vector
.global reset_vector .global reset_vector
@@ -11,6 +11,8 @@ reset_vector:
irq_vector: irq_vector:
ret ret
.section .text
__start: __start:
/* setup the stack pointer */ /* setup the stack pointer */
la sp, __stack_top la sp, __stack_top