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feat(lp_io): Add LP_IO support for ESP32C61

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This commit is contained in:
Song Ruo Jing
2024-08-22 15:21:17 +08:00
parent 87b295a35f
commit 9994f493ed
23 changed files with 600 additions and 117 deletions
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3
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.c
View File

@@ -238,8 +238,7 @@ TEST_CASE("RTCIO_output_hold_test", "[rtcio]")
#if SOC_DEEP_SLEEP_SUPPORTED && SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
// It is not necessary to test every rtcio pin, it will take too much ci testing time for deep sleep
// Only tests on s_test_map[TEST_RTCIO_DEEP_SLEEP_PIN_INDEX] pin
// (ESP32: IO25, ESP32S2, S3: IO6, C6: IO5, H2: IO12, C5: IO5) these pads' default configuration is low level
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5
// These pads' default configuration is low level
static void rtcio_deep_sleep_hold_test_first_stage(void)
{

19
components/esp_driver_gpio/test_apps/gpio/main/test_rtcio.h
View File

@@ -37,6 +37,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_38, //GPIO38
GPIO_NUM_39, //GPIO39
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO25
#elif defined CONFIG_IDF_TARGET_ESP32S2
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
@@ -65,6 +66,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_20, //GPIO20
GPIO_NUM_21, //GPIO21
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO6
#elif defined CONFIG_IDF_TARGET_ESP32S3
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
@@ -93,6 +95,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_20, //GPIO20
GPIO_NUM_21, //GPIO21
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO6
#elif CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
@@ -107,6 +110,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_6, //GPIO6
GPIO_NUM_7, //GPIO7
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO5
#elif CONFIG_IDF_TARGET_ESP32H2
#define TEST_GPIO_PIN_COUNT 8
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
@@ -119,6 +123,7 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_13, //GPIO13
GPIO_NUM_14, //GPIO14
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 5 // IO12
#elif CONFIG_IDF_TARGET_ESP32P4
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
@@ -141,6 +146,20 @@ const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_14, //GPIO14
GPIO_NUM_15, //GPIO15
};
#elif CONFIG_IDF_TARGET_ESP32C61
// Has no input-only rtcio pins, all pins support pull-up/down
#define RTCIO_SUPPORT_PU_PD(num) 1
#define TEST_GPIO_PIN_COUNT 7
const int s_test_map[TEST_GPIO_PIN_COUNT] = {
GPIO_NUM_0, //GPIO0
GPIO_NUM_1, //GPIO1
GPIO_NUM_2, //GPIO2
GPIO_NUM_3, //GPIO3
GPIO_NUM_4, //GPIO4
GPIO_NUM_5, //GPIO5
GPIO_NUM_6, //GPIO6
};
#define TEST_RTCIO_DEEP_SLEEP_PIN_INDEX 6 // IO6
#endif
#ifdef __cplusplus