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Merge branch 'refactor/emac_hal' into 'master'
hal/emac_hal: refactor of emac_hal Closes IDF-3155 See merge request espressif/esp-idf!13500
This commit is contained in:
Michael (XIAO Xufeng)
@@ -1,410 +0,0 @@
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// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_err.h"
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#include "soc/emac_dma_struct.h"
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#include "soc/emac_mac_struct.h"
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#include "soc/emac_ext_struct.h"
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#define EMAC_MEDIA_INTERFACE_MII (0)
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#define EMAC_MEDIA_INTERFACE_RMII (1)
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#define EMAC_WATCHDOG_ENABLE (0)
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#define EMAC_WATCHDOG_DISABLE (1)
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#define EMAC_JABBER_ENABLE (0)
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#define EMAC_JABBER_DISABLE (1)
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#define EMAC_INTERFRAME_GAP_96BIT (0)
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#define EMAC_INTERFRAME_GAP_88BIT (1)
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#define EMAC_INTERFRAME_GAP_80BIT (2)
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#define EMAC_INTERFRAME_GAP_72BIT (3)
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#define EMAC_INTERFRAME_GAP_64BIT (4)
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#define EMAC_INTERFRAME_GAP_56BIT (5)
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#define EMAC_INTERFRAME_GAP_48BIT (6)
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#define EMAC_INTERFRAME_GAP_40BIT (7)
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#define EMAC_CARRIERSENSE_ENABLE (0)
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#define EMAC_CARRIERSENSE_DISABLE (1)
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#define EMAC_PORT_1000MBPS (0)
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#define EMAC_PORT_10_100MBPS (1)
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#define EMAC_SPEED_10M (0)
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#define EMAC_SPEED_100M (1)
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#define EMAC_RECEIVE_OWN_ENABLE (0)
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#define EMAC_RECEIVE_OWN_DISABLE (1)
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#define EMAC_LOOPBACK_DISABLE (0)
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#define EMAC_LOOPBACK_ENABLE (1)
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#define EMAC_DUPLEX_HALF (0)
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#define EMAC_DUPLEX_FULL (1)
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#define EMAC_CHECKSUM_SW (0)
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#define EMAC_CHECKSUM_HW (1)
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#define EMAC_RETRY_TRANSMISSION_ENABLE (0)
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#define EMAC_RETRY_TRANSMISSION_DISABLE (1)
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#define EMAC_AUTO_PAD_CRC_STRIP_DISABLE (0)
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#define EMAC_AUTO_PAD_CRC_STRIP_ENABLE (1)
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#define EMAC_BACKOFF_LIMIT_10 (0)
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#define EMAC_BACKOFF_LIMIT_8 (1)
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#define EMAC_BACKOFF_LIMIT_4 (2)
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#define EMAC_BACKOFF_LIMIT_1 (3)
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#define EMAC_DEFERRAL_CHECK_DISABLE (0)
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#define EMAC_DEFERRAL_CHECK_ENABLE (1)
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#define EMAC_PREAMBLE_LENGTH_7 (0)
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#define EMAC_PREAMBLE_LENGTH_5 (1)
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#define EMAC_PREAMBLE_LENGTH_3 (2)
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#define EMAC_RECEIVE_ALL_DISABLE (0)
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#define EMAC_RECEIVE_ALL_ENABLE (1)
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#define EMAC_SOURCE_ADDR_FILTER_DISABLE (0)
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#define EMAC_SOURCE_ADDR_FILTER_NORMAL (2)
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#define EMAC_SOURCE_ADDR_FILTER_INVERSE (3)
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#define EMAC_CONTROL_FRAME_BLOCKALL (0)
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#define EMAC_CONTROL_FRAME_FORWARDALL_PAUSE (1)
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#define EMAC_CONTROL_FRAME_FORWARDALL (2)
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#define EMAC_CONTROL_FRAME_FORWARDFILT (3)
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#define EMAC_RECEPT_BROADCAST_ENABLE (0)
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#define EMAC_RECEPT_BROADCAST_DISABLE (1)
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#define EMAC_DEST_ADDR_FILTER_NORMAL (0)
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#define EMAC_DEST_ADDR_FILTER_INVERSE (1)
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#define EMAC_PROMISCUOUS_DISABLE (0)
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#define EMAC_PROMISCUOUS_ENABLE (1)
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#define EMAC_PAUSE_TIME 0x1648
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#define EMAC_ZERO_QUANTA_PAUSE_ENABLE (0)
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#define EMAC_ZERO_QUANTA_PAUSE_DISABLE (1)
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#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_4 (0)
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#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_28 (1)
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#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_144 (2)
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#define EMAC_PAUSE_LOW_THRESHOLD_MINUS_256
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#define EMAC_UNICAST_PAUSE_DETECT_DISABLE (0)
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#define EMAC_UNICAST_PAUSE_DETECT_ENABLE (1)
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#define EMAC_RECEIVE_FLOW_CONTROL_DISABLE (0)
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#define EMAC_RECEIVE_FLOW_CONTROL_ENABLE (1)
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#define EMAC_TRANSMIT_FLOW_CONTROL_DISABLE (0)
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#define EMAC_TRANSMIT_FLOW_CONTROL_ENABLE (1)
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#define EMAC_DROP_TCPIP_CHECKSUM_ERROR_ENABLE (0)
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#define EMAC_DROP_TCPIP_CHECKSUM_ERROR_DISABLE (1)
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#define EMAC_RECEIVE_STORE_FORWARD_DISABLE (0)
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#define EMAC_RECEIVE_STORE_FORWARD_ENABLE (1)
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#define EMAC_FLUSH_RECEIVED_FRAME_ENABLE (0)
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#define EMAC_FLUSH_RECEIVED_FRAME_DISABLE (1)
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#define EMAC_TRANSMIT_STORE_FORWARD_DISABLE (0)
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#define EMAC_TRANSMIT_STORE_FORWARD_ENABLE (1)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_64 (0)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_128 (1)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_192 (2)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_256 (3)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_40 (4)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_32 (5)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_24 (6)
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#define EMAC_TRANSMIT_THRESHOLD_CONTROL_16 (7)
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#define EMAC_FORWARD_ERROR_FRAME_DISABLE (0)
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#define EMAC_FORWARD_ERROR_FRAME_ENABLE (1)
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#define EMAC_FORWARD_UNDERSIZED_GOOD_FRAME_DISABLE (0)
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#define EMAC_FORWARD_UNDERSIZED_GOOD_FRAME_ENABLE (1)
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#define EMAC_RECEIVE_THRESHOLD_CONTROL_64 (0)
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#define EMAC_RECEIVE_THRESHOLD_CONTROL_32 (1)
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#define EMAC_RECEIVE_THRESHOLD_CONTROL_96 (2)
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#define EMAC_RECEIVE_THRESHOLD_CONTROL_128 (3)
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#define EMAC_OPERATE_SECOND_FRAME_DISABLE (0)
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#define EMAC_OPERATE_SECOND_FRAME_ENABLE (1)
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#define EMAC_MIXED_BURST_DISABLE (0)
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#define EMAC_MIXED_BURST_ENABLE (1)
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#define EMAC_ADDR_ALIGN_BEATS_DISABLE (0)
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#define EMAC_ADDR_ALIGN_BEATS_ENABLE (1)
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#define EMAC_UNUSE_SEPARATE_PBL (0)
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#define EMAC_USE_SEPARATE_PBL (1)
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#define EMAC_DMA_BURST_LENGTH_1BEAT (1)
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#define EMAC_DMA_BURST_LENGTH_2BEAT (2)
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#define EMAC_DMA_BURST_LENGTH_4BEAT (4)
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#define EMAC_DMA_BURST_LENGTH_8BEAT (8)
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#define EMAC_DMA_BURST_LENGTH_16BEAT (16)
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#define EMAC_DMA_BURST_LENGTH_32BEAT (32)
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#define EMAC_ENHANCED_DESCRIPTOR_DISABLE (0)
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#define EMAC_ENHANCED_DESCRIPTOR_ENABLE (1)
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#define EMAC_DMA_ARBITRATION_SCHEME_ROUNDROBIN (0)
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#define EMAC_DMA_ARBITRATION_SCHEME_FIXEDPRIO (1)
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#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_1_1 (0)
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#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_2_1 (1)
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#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_3_1 (2)
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#define EMAC_DMA_ARBITRATION_ROUNDROBIN_RXTX_4_1 (3)
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/**
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* @brief Ethernet DMA TX Descriptor
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*
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*/
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typedef struct {
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volatile union {
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struct {
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uint32_t Deferred : 1; /*!< MAC defers before transmission */
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uint32_t UnderflowErr : 1; /*!< DMA encountered an empty transmit buffer */
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uint32_t ExcessiveDeferral : 1; /*!< Excessive deferral of over 24,288 bit times */
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uint32_t CollisionCount : 4; /*!< Number of collisions occurred before transmitted */
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uint32_t VLanFrame : 1; /*!< Transmitted frame is a VLAN-type frame */
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uint32_t ExcessiveCollision : 1; /*!< Transmission aborted after 16 successive collisions */
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uint32_t LateCollision : 1; /*!< Collision occurred after the collision window */
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uint32_t NoCarrier : 1; /*!< Carrier Sense signal from the PHY was not asserted */
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uint32_t LossCarrier : 1; /*!< Loss of carrier occurred during transmission */
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uint32_t PayloadChecksumErr : 1; /*!< Checksum error in TCP/UDP/ICMP datagram payload */
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uint32_t FrameFlushed : 1; /*!< DMA or MTL flushed the frame */
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uint32_t JabberTimeout : 1; /*!< MAC transmitter has experienced a jabber timeout */
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uint32_t ErrSummary : 1; /*!< Error Summary */
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uint32_t IPHeadErr : 1; /*!< IP Header Error */
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uint32_t TxTimestampStatus : 1; /*!< Timestamp captured for the transmit frame */
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uint32_t VLANInsertControl : 2; /*!< VLAN tagging or untagging before transmitting */
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uint32_t SecondAddressChained : 1; /*!< Second address in the descriptor is Next Descriptor address */
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uint32_t TransmitEndRing : 1; /*!< Descriptor list reached its final descriptor */
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uint32_t ChecksumInsertControl : 2; /*!< Control checksum calculation and insertion */
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uint32_t CRCReplacementControl : 1; /*!< Control CRC replace */
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uint32_t TransmitTimestampEnable : 1; /*!< Enable IEEE1588 harware timestamping */
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uint32_t DisablePad : 1; /*!< Control add padding when frame short than 64 bytes */
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uint32_t DisableCRC : 1; /*!< Control append CRC to the end of frame */
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uint32_t FirstSegment : 1; /*!< Buffer contains the first segment of a frame */
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uint32_t LastSegment : 1; /*!< Buffer contains the last segment of a frame */
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uint32_t InterruptOnComplete : 1; /*!< Interrupt after frame transmitted */
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uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
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};
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uint32_t Value;
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} TDES0;
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union {
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struct {
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uint32_t TransmitBuffer1Size : 13; /*!< First data buffer byte size */
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uint32_t Reserved : 3; /*!< Reserved */
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uint32_t TransmitBuffer2Size : 13; /*!< Second data buffer byte size */
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uint32_t SAInsertControl : 3; /*!< Control MAC add or replace Source Address field */
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};
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uint32_t Value;
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} TDES1;
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uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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uint32_t Reserved1; /*!< Reserved */
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uint32_t Reserved2; /*!< Reserved */
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uint32_t TimeStampLow; /*!< Transmit Frame Timestamp Low */
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uint32_t TimeStampHigh; /*!< Transmit Frame Timestamp High */
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} eth_dma_tx_descriptor_t;
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#define EMAC_DMATXDESC_CHECKSUM_BYPASS 0 /*!< Checksum engine bypass */
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#define EMAC_DMATXDESC_CHECKSUM_IPV4HEADER 1 /*!< IPv4 header checksum insertion */
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#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPSEGMENT 2 /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
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#define EMAC_DMATXDESC_CHECKSUM_TCPUDPICMPFULL 3 /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
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_Static_assert(sizeof(eth_dma_tx_descriptor_t) == 32, "eth_dma_tx_descriptor_t should occupy 32 bytes in memory");
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/**
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* @brief Ethernet DMA RX Descriptor
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*
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*/
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typedef struct {
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volatile union {
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struct {
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uint32_t ExtendStatusAvailable : 1; /*!< Extended statsu is available in RDES4 */
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uint32_t CRCErr : 1; /*!< CRC error occurred on frame */
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uint32_t DribbleBitErr : 1; /*!< frame contains non int multiple of 8 bits */
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uint32_t ReceiveErr : 1; /*!< Receive error */
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uint32_t ReceiveWatchdogTimeout : 1; /*!< Receive Watchdog timeout */
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uint32_t FrameType : 1; /*!< Ethernet type or IEEE802.3 */
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uint32_t LateCollision : 1; /*!< Late collision occurred during reception */
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uint32_t TSAvailIPChecksumErrGiantFrame : 1; /*!< Timestamp available or IP Checksum error or Giant frame */
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uint32_t LastDescriptor : 1; /*!< Last buffer of the frame */
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uint32_t FirstDescriptor : 1; /*!< First buffer of the frame */
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uint32_t VLANTag : 1; /*!< VLAN Tag: received frame is a VLAN frame */
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uint32_t OverflowErr : 1; /*!< Frame was damaged due to buffer overflow */
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uint32_t LengthErr : 1; /*!< Frame size not matching with length field */
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uint32_t SourceAddrFilterFail : 1; /*!< SA field of frame failed the SA filter */
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uint32_t DescriptorErr : 1; /*!< Frame truncated and DMA doesn't own next descriptor */
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uint32_t ErrSummary : 1; /*!< Error Summary, OR of all errors in RDES */
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uint32_t FrameLength : 14; /*!< Byte length of received frame */
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uint32_t DestinationAddrFilterFail : 1; /*!< Frame failed in the DA Filter in the MAC */
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uint32_t Own : 1; /*!< Owner of this descriptor: DMA controller or host */
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};
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uint32_t Value;
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} RDES0;
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union {
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struct {
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uint32_t ReceiveBuffer1Size : 13; /*!< First data buffer size in bytes */
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uint32_t Reserved1 : 1; /*!< Reserved */
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uint32_t SecondAddressChained : 1; /*!< Seconde address is the Next Descriptor address */
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uint32_t ReceiveEndOfRing : 1; /*!< Descriptor reached its final descriptor */
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uint32_t ReceiveBuffer2Size : 13; /*!< Second data buffer size in bytes */
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uint32_t Reserved : 2; /*!< Reserved */
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uint32_t DisableInterruptOnComplete : 1; /*!< Disable the assertion of interrupt to host */
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};
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uint32_t Value;
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} RDES1;
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uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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volatile union {
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struct {
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uint32_t IPPayloadType : 3; /*!< Type of payload in the IP datagram */
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uint32_t IPHeadErr : 1; /*!< IP header error */
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uint32_t IPPayloadErr : 1; /*!< IP payload error */
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uint32_t IPChecksumBypass : 1; /*!< Checksum offload engine is bypassed */
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uint32_t IPv4PacketReceived : 1; /*!< Received packet is an IPv4 packet */
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uint32_t IPv6PacketReceived : 1; /*!< Received packet is an IPv6 packet */
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uint32_t MessageType : 4; /*!< PTP Message Type */
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uint32_t PTPFrameType : 1; /*!< PTP message is over Ethernet or IPv4/IPv6 */
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uint32_t PTPVersion : 1; /*!< Version of PTP protocol */
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uint32_t TimestampDropped : 1; /*!< Timestamp dropped because of overflow */
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uint32_t Reserved1 : 1; /*!< Reserved */
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uint32_t AVPacketReceived : 1; /*!< AV packet is received */
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uint32_t AVTaggedPacketReceived : 1; /*!< AV tagged packet is received */
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uint32_t VLANTagPrioVal : 3; /*!< VLAN tag's user value in the received packekt */
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uint32_t Reserved2 : 3; /*!< Reserved */
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uint32_t Layer3FilterMatch : 1; /*!< Received frame matches one of the enabled Layer3 IP */
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uint32_t Layer4FilterMatch : 1; /*!< Received frame matches one of the enabled Layer4 IP */
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uint32_t Layer3Layer4FilterNumberMatch : 2; /*!< Number of Layer3 and Layer4 Filter that matches the received frame */
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uint32_t Reserved3 : 4; /*!< Reserved */
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};
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uint32_t Value;
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} ExtendedStatus;
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uint32_t Reserved; /*!< Reserved */
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uint32_t TimeStampLow; /*!< Receive frame timestamp low */
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uint32_t TimeStampHigh; /*!< Receive frame timestamp high */
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} eth_dma_rx_descriptor_t;
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#define EMAC_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
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#define EMAC_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
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#define EMAC_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
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#define EMAC_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
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#define EMAC_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
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#define EMAC_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
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#define EMAC_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
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#define EMAC_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
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#define EMAC_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
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#define EMAC_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
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#define EMAC_DMADESC_OWNER_CPU (0)
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#define EMAC_DMADESC_OWNER_DMA (1)
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_Static_assert(sizeof(eth_dma_rx_descriptor_t) == 32, "eth_dma_rx_descriptor_t should occupy 32 bytes in memory");
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typedef struct {
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emac_mac_dev_t *mac_regs;
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emac_dma_dev_t *dma_regs;
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emac_ext_dev_t *ext_regs;
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uint8_t **rx_buf;
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uint8_t **tx_buf;
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void *descriptors;
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eth_dma_rx_descriptor_t *rx_desc;
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eth_dma_tx_descriptor_t *tx_desc;
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} emac_hal_context_t;
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void emac_hal_init(emac_hal_context_t *hal, void *descriptors,
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uint8_t **rx_buf, uint8_t **tx_buf);
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void emac_hal_reset_desc_chain(emac_hal_context_t *hal);
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void emac_hal_lowlevel_init(emac_hal_context_t *hal);
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void emac_hal_reset(emac_hal_context_t *hal);
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bool emac_hal_is_reset_done(emac_hal_context_t *hal);
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void emac_hal_set_csr_clock_range(emac_hal_context_t *hal);
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void emac_hal_init_mac_default(emac_hal_context_t *hal);
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|
||||
void emac_hal_init_dma_default(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_speed(emac_hal_context_t *hal, uint32_t speed);
|
||||
|
||||
void emac_hal_set_duplex(emac_hal_context_t *hal, uint32_t duplex);
|
||||
|
||||
void emac_hal_set_promiscuous(emac_hal_context_t *hal, bool enable);
|
||||
|
||||
/**
|
||||
* @brief Send MAC-CTRL frames to peer (EtherType=0x8808, opcode=0x0001, dest_addr=MAC-specific-ctrl-proto-01 (01:80:c2:00:00:01))
|
||||
*/
|
||||
void emac_hal_send_pause_frame(emac_hal_context_t *hal, bool enable);
|
||||
|
||||
bool emac_hal_is_mii_busy(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_phy_cmd(emac_hal_context_t *hal, uint32_t phy_addr, uint32_t phy_reg, bool write);
|
||||
|
||||
void emac_hal_set_phy_data(emac_hal_context_t *hal, uint32_t reg_value);
|
||||
|
||||
uint32_t emac_hal_get_phy_data(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_set_address(emac_hal_context_t *hal, uint8_t *mac_addr);
|
||||
|
||||
void emac_hal_start(emac_hal_context_t *hal);
|
||||
|
||||
void emac_hal_stop(emac_hal_context_t *hal);
|
||||
|
||||
uint32_t emac_hal_get_tx_desc_owner(emac_hal_context_t *hal);
|
||||
|
||||
uint32_t emac_hal_transmit_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t length);
|
||||
|
||||
uint32_t emac_hal_receive_frame(emac_hal_context_t *hal, uint8_t *buf, uint32_t size, uint32_t *frames_remain, uint32_t *free_desc);
|
||||
|
||||
void emac_hal_enable_flow_ctrl(emac_hal_context_t *hal, bool enable);
|
||||
|
||||
void emac_hal_isr(void *arg);
|
||||
|
||||
void emac_hal_tx_complete_cb(void *arg);
|
||||
|
||||
void emac_hal_tx_unavail_cb (void *arg);
|
||||
|
||||
void emac_hal_rx_complete_cb (void *arg);
|
||||
|
||||
void emac_hal_rx_early_cb(void *arg);
|
||||
|
||||
void emac_hal_rx_unavail_cb(void *arg);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
596
components/hal/esp32/include/hal/emac_ll.h
Normal file
596
components/hal/esp32/include/hal/emac_ll.h
Normal file
@@ -0,0 +1,596 @@
|
||||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
/*******************************************************************************
|
||||
* NOTICE
|
||||
* The hal is not public api, don't use in application code.
|
||||
* See readme.md in hal/include/hal/readme.md
|
||||
******************************************************************************/
|
||||
|
||||
// The LL layer for ESP32 eMAC register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "hal/eth_types.h"
|
||||
#include "soc/emac_dma_struct.h"
|
||||
#include "soc/emac_mac_struct.h"
|
||||
#include "soc/emac_ext_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Register configuration */
|
||||
#define EMAC_LL_INTERFRAME_GAP_96BIT (0)
|
||||
#define EMAC_LL_INTERFRAME_GAP_88BIT (1)
|
||||
#define EMAC_LL_INTERFRAME_GAP_80BIT (2)
|
||||
#define EMAC_LL_INTERFRAME_GAP_72BIT (3)
|
||||
#define EMAC_LL_INTERFRAME_GAP_64BIT (4)
|
||||
#define EMAC_LL_INTERFRAME_GAP_56BIT (5)
|
||||
#define EMAC_LL_INTERFRAME_GAP_48BIT (6)
|
||||
#define EMAC_LL_INTERFRAME_GAP_40BIT (7)
|
||||
|
||||
#define EMAC_LL_BACKOFF_LIMIT_10 (0)
|
||||
#define EMAC_LL_BACKOFF_LIMIT_8 (1)
|
||||
#define EMAC_LL_BACKOFF_LIMIT_4 (2)
|
||||
#define EMAC_LL_BACKOFF_LIMIT_1 (3)
|
||||
|
||||
#define EMAC_LL_PREAMBLE_LENGTH_7 (0)
|
||||
#define EMAC_LL_PREAMBLE_LENGTH_5 (1)
|
||||
#define EMAC_LL_PREAMBLE_LENGTH_3 (2)
|
||||
|
||||
#define EMAC_LL_SOURCE_ADDR_FILTER_DISABLE (0)
|
||||
#define EMAC_LL_SOURCE_ADDR_FILTER_NORMAL (2)
|
||||
#define EMAC_LL_SOURCE_ADDR_FILTER_INVERSE (3)
|
||||
|
||||
#define EMAC_LL_CONTROL_FRAME_BLOCKALL (0)
|
||||
#define EMAC_LL_CONTROL_FRAME_FORWARDALL_PAUSE (1)
|
||||
#define EMAC_LL_CONTROL_FRAME_FORWARDALL (2)
|
||||
#define EMAC_LL_CONTROL_FRAME_FORWARDFILT (3)
|
||||
|
||||
#define EMAC_LL_PAUSE_TIME 0x1648
|
||||
|
||||
#define EMAC_LL_PAUSE_LOW_THRESHOLD_MINUS_4 (0)
|
||||
#define EMAC_LL_PAUSE_LOW_THRESHOLD_MINUS_28 (1)
|
||||
#define EMAC_LL_PAUSE_LOW_THRESHOLD_MINUS_144 (2)
|
||||
#define EMAC_LL_PAUSE_LOW_THRESHOLD_MINUS_256 (3)
|
||||
|
||||
#define EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_64 (0)
|
||||
#define EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_128 (1)
|
||||
#define EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_192 (2)
|
||||
#define EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_256 (3)
|
||||
#define EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_40 (4)
|
||||
#define EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_32 (5)
|
||||
#define EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_24 (6)
|
||||
#define EMAC_LL_TRANSMIT_THRESHOLD_CONTROL_16 (7)
|
||||
|
||||
#define EMAC_LL_RECEIVE_THRESHOLD_CONTROL_64 (0)
|
||||
#define EMAC_LL_RECEIVE_THRESHOLD_CONTROL_32 (1)
|
||||
#define EMAC_LL_RECEIVE_THRESHOLD_CONTROL_96 (2)
|
||||
#define EMAC_LL_RECEIVE_THRESHOLD_CONTROL_128 (3)
|
||||
|
||||
#define EMAC_LL_DMA_BURST_LENGTH_1BEAT (1)
|
||||
#define EMAC_LL_DMA_BURST_LENGTH_2BEAT (2)
|
||||
#define EMAC_LL_DMA_BURST_LENGTH_4BEAT (4)
|
||||
#define EMAC_LL_DMA_BURST_LENGTH_8BEAT (8)
|
||||
#define EMAC_LL_DMA_BURST_LENGTH_16BEAT (16)
|
||||
#define EMAC_LL_DMA_BURST_LENGTH_32BEAT (32)
|
||||
|
||||
#define EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_1_1 (0)
|
||||
#define EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_2_1 (1)
|
||||
#define EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_3_1 (2)
|
||||
#define EMAC_LL_DMA_ARBITRATION_ROUNDROBIN_RXTX_4_1 (3)
|
||||
|
||||
/* PTP register bits */
|
||||
#define EMAC_LL_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
|
||||
#define EMAC_LL_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
|
||||
#define EMAC_LL_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
|
||||
#define EMAC_LL_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
|
||||
#define EMAC_LL_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
|
||||
#define EMAC_LL_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
|
||||
#define EMAC_LL_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
|
||||
|
||||
#define EMAC_LL_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
|
||||
#define EMAC_LL_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
|
||||
#define EMAC_LL_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
|
||||
|
||||
#define EMAC_LL_DMADESC_OWNER_CPU (0)
|
||||
#define EMAC_LL_DMADESC_OWNER_DMA (1)
|
||||
|
||||
/* Interrupt flags (referring to dmastatus register in emac_dma_struct.h) */
|
||||
#define EMAC_LL_DMA_TRANSMIT_FINISH_INTR 0x00000001U
|
||||
#define EMAC_LL_DMA_TRANSMIT_STOP_INTR 0x00000002U
|
||||
#define EMAC_LL_DMA_TRANSMIT_BUFF_UNAVAILABLE_INTR 0x00000004U
|
||||
#define EMAC_LL_DMA_TRANSMIT_TIMEOUT_INTR 0x00000008U
|
||||
#define EMAC_LL_DMA_RECEIVE_OVERFLOW_INTR 0x00000010U
|
||||
#define EMAC_LL_DMA_TRANSMIT_UNDERFLOW_INTR 0x00000020U
|
||||
#define EMAC_LL_DMA_RECEIVE_FINISH_INTR 0x00000040U
|
||||
#define EMAC_LL_DMA_RECEIVE_BUFF_UNAVAILABLE_INTR 0x00000080U
|
||||
#define EMAC_LL_DMA_RECEIVE_STOP_INTR 0x00000100U
|
||||
#define EMAC_LL_DMA_RECEIVE_TIMEOUT_INTR 0x00000200U
|
||||
#define EMAC_LL_DMA_TRANSMIT_FIRST_BYTE_INTR 0x00000400U
|
||||
#define EMAC_LL_DMA_FATAL_BUS_ERROR_INRT 0x00001000U
|
||||
#define EMAC_LL_DMA_RECEIVE_FIRST_BYTE_INTR 0x00002000U
|
||||
#define EMAC_LL_DMA_ABNORMAL_INTR_SUMMARY 0x00004000U
|
||||
#define EMAC_LL_DMA_NORMAL_INTR_SUMMARY 0x00008000U
|
||||
#define EMAC_LL_DMA_POWER_MANAGE_INTR 0x10000000U
|
||||
#define EMAC_LL_DMA_TIMESTAMP_TRIGGER_INTR 0x20000000U
|
||||
|
||||
/* Interrupt enable (referring to dmain_en register in emac_dma_struct.h) */
|
||||
#define EMAC_LL_INTR_TRANSMIT_ENABLE 0x00000001U
|
||||
#define EMAC_LL_INTR_TRANSMIT_STOP_ENABLE 0x00000002U
|
||||
#define EMAC_LL_INTR_TRANSMIT_BUFF_UNAVAILABLE_ENABLE 0x00000004U
|
||||
#define EMAC_LL_INTR_TRANSMIT_TIMEOUT_ENABLE 0x00000008U
|
||||
#define EMAC_LL_INTR_OVERFLOW_ENABLE 0x00000010U
|
||||
#define EMAC_LL_INTR_UNDERFLOW_ENABLE 0x00000020U
|
||||
#define EMAC_LL_INTR_RECEIVE_ENABLE 0x00000040U
|
||||
#define EMAC_LL_INTR_REVEIVE_BUFF_UNAVAILABLE_ENABLE 0x00000080U
|
||||
#define EMAC_LL_INTR_RECEIVE_STOP_ENABLE 0x00000100U
|
||||
#define EMAC_LL_INTR_RECEIVE_TIMEOUT_ENABLE 0x00000200U
|
||||
#define EMAC_LL_INTR_TRANSMIT_FIRST_BYTE_ENABLE 0x00000400U
|
||||
#define EMAC_LL_INTR_FATAL_BUS_ERR_ENABLE 0x00002000U
|
||||
#define EMAC_LL_INTR_RECEIVE_FIRST_BYTE_ENABLE 0x00004000U
|
||||
#define EMAC_LL_INTR_ABNORMAL_SUMMARY_ENABLE 0x00008000U
|
||||
#define EMAC_LL_INTR_NORMAL_SUMMARY_ENABLE 0x00010000U
|
||||
|
||||
/* Enable needed interrupts (recv/recv_buf_unavailabal/normal must be enabled to make eth work) */
|
||||
#define EMAC_LL_CONFIG_ENABLE_INTR_MASK (EMAC_LL_INTR_RECEIVE_ENABLE | EMAC_LL_INTR_NORMAL_SUMMARY_ENABLE)
|
||||
|
||||
/************** Start of mac regs operation ********************/
|
||||
/* emacgmiiaddr */
|
||||
static inline void emac_ll_set_csr_clock_division(emac_mac_dev_t *mac_regs, uint32_t div_mode)
|
||||
{
|
||||
mac_regs->emacgmiiaddr.miicsrclk = div_mode;
|
||||
}
|
||||
|
||||
static inline bool emac_ll_is_mii_busy(emac_mac_dev_t *mac_regs)
|
||||
{
|
||||
return mac_regs->emacgmiiaddr.miibusy ? true : false;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_phy_addr(emac_mac_dev_t *mac_regs, uint32_t addr)
|
||||
{
|
||||
mac_regs->emacgmiiaddr.miidev = addr;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_phy_reg(emac_mac_dev_t *mac_regs, uint32_t reg)
|
||||
{
|
||||
mac_regs->emacgmiiaddr.miireg = reg;
|
||||
}
|
||||
|
||||
static inline void emac_ll_write_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->emacgmiiaddr.miiwrite = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_busy(emac_mac_dev_t *mac_regs, bool busy)
|
||||
{
|
||||
mac_regs->emacgmiiaddr.miibusy = busy ? 1 : 0;
|
||||
}
|
||||
|
||||
/* gmacconfig */
|
||||
static inline void emac_ll_watchdog_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.watchdog = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_jabber_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.jabber = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_inter_frame_gap(emac_mac_dev_t *mac_regs, uint32_t gap)
|
||||
{
|
||||
mac_regs->gmacconfig.interframegap = gap;
|
||||
}
|
||||
|
||||
static inline void emac_ll_carrier_sense_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.disablecrs = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_port_speed(emac_mac_dev_t *mac_regs, eth_speed_t speed)
|
||||
{
|
||||
if (speed == ETH_SPEED_10M || speed == ETH_SPEED_100M) {
|
||||
mac_regs->gmacconfig.mii = 1; // 10_100MBPS
|
||||
mac_regs->gmacconfig.fespeed = speed;
|
||||
} else {
|
||||
mac_regs->gmacconfig.mii = 0; // 1000MBPS
|
||||
}
|
||||
}
|
||||
|
||||
static inline void emac_ll_recv_own_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.rxown = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_loopback_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.loopback = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_duplex(emac_mac_dev_t *mac_regs, eth_duplex_t duplex)
|
||||
{
|
||||
mac_regs->gmacconfig.duplex = duplex;
|
||||
}
|
||||
|
||||
static inline void emac_ll_checksum_offload_mode(emac_mac_dev_t *mac_regs, eth_checksum_t mode)
|
||||
{
|
||||
mac_regs->gmacconfig.rxipcoffload = mode;
|
||||
}
|
||||
|
||||
static inline void emac_ll_retry_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.retry = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_auto_pad_crc_strip_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.padcrcstrip = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_back_off_limit(emac_mac_dev_t *mac_regs, uint32_t limit)
|
||||
{
|
||||
mac_regs->gmacconfig.backofflimit = limit;
|
||||
}
|
||||
|
||||
static inline void emac_ll_deferral_check_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.padcrcstrip = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_preamble_length(emac_mac_dev_t *mac_regs, uint32_t len)
|
||||
{
|
||||
mac_regs->gmacconfig.pltf = len;
|
||||
}
|
||||
|
||||
static inline void emac_ll_transmit_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.tx = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_receive_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacconfig.rx = enable;
|
||||
}
|
||||
|
||||
/* gmacff */
|
||||
static inline void emac_ll_receive_all_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacff.receive_all = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_src_addr_filter(emac_mac_dev_t *mac_regs, uint32_t filter)
|
||||
{
|
||||
mac_regs->gmacff.safe = filter;
|
||||
}
|
||||
|
||||
static inline void emac_ll_sa_inverse_filter_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacff.saif = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_pass_ctrl_frame_mode(emac_mac_dev_t *mac_regs, uint32_t mode)
|
||||
{
|
||||
mac_regs->gmacff.pcf = mode;
|
||||
}
|
||||
|
||||
static inline void emac_ll_broadcast_frame_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacff.dbf = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_pass_all_multicast_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacff.pam = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_da_inverse_filter_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacff.daif = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_promiscuous_mode_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacff.pmode = enable;
|
||||
}
|
||||
|
||||
/* gmacfc */
|
||||
static inline void emac_ll_set_pause_time(emac_mac_dev_t *mac_regs, uint32_t time)
|
||||
{
|
||||
mac_regs->gmacfc.pause_time = time;
|
||||
}
|
||||
|
||||
static inline void emac_ll_zero_quanta_pause_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacfc.dzpq = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_pause_low_threshold(emac_mac_dev_t *mac_regs, uint32_t threshold)
|
||||
{
|
||||
mac_regs->gmacfc.plt = threshold;
|
||||
}
|
||||
|
||||
static inline void emac_ll_unicast_pause_frame_detect_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacfc.upfd = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_receive_flow_ctrl_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacfc.rfce = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_transmit_flow_ctrl_enable(emac_mac_dev_t *mac_regs, bool enable)
|
||||
{
|
||||
mac_regs->gmacfc.tfce = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_clear(emac_mac_dev_t *mac_regs)
|
||||
{
|
||||
mac_regs->gmacfc.val = 0;
|
||||
}
|
||||
|
||||
/* emacmiidata */
|
||||
static inline void emac_ll_set_phy_data(emac_mac_dev_t *mac_regs, uint32_t data)
|
||||
{
|
||||
mac_regs->emacmiidata.mii_data = data;
|
||||
}
|
||||
|
||||
static inline uint32_t emac_ll_get_phy_data(emac_mac_dev_t *mac_regs)
|
||||
{
|
||||
return mac_regs->emacmiidata.mii_data;
|
||||
}
|
||||
|
||||
/* emacaddr0 */
|
||||
static inline void emac_ll_set_addr(emac_mac_dev_t *mac_regs, const uint8_t *addr)
|
||||
{
|
||||
mac_regs->emacaddr0high.address0_hi = (addr[5] << 8) | addr[4];
|
||||
mac_regs->emacaddr0low = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | (addr[0]);
|
||||
}
|
||||
/*************** End of mac regs operation *********************/
|
||||
|
||||
|
||||
|
||||
/************** Start of dma regs operation ********************/
|
||||
/* dmabusmode */
|
||||
static inline void emac_ll_reset(emac_dma_dev_t *dma_regs)
|
||||
{
|
||||
dma_regs->dmabusmode.sw_rst = 1;
|
||||
}
|
||||
|
||||
static inline bool emac_ll_is_reset_done(emac_dma_dev_t *dma_regs)
|
||||
{
|
||||
return dma_regs->dmabusmode.sw_rst ? false : true;
|
||||
}
|
||||
|
||||
/* dmarxbaseaddr / dmatxbaseaddr */
|
||||
static inline void emac_ll_set_rx_desc_addr(emac_dma_dev_t *dma_regs, uint32_t addr)
|
||||
{
|
||||
dma_regs->dmarxbaseaddr = addr;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_tx_desc_addr(emac_dma_dev_t *dma_regs, uint32_t addr)
|
||||
{
|
||||
dma_regs->dmatxbaseaddr = addr;
|
||||
}
|
||||
|
||||
/* dmaoperation_mode */
|
||||
static inline void emac_ll_drop_tcp_err_frame_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.dis_drop_tcpip_err_fram = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_recv_store_forward_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.rx_store_forward = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_flush_recv_frame_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.dis_flush_recv_frames = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_trans_store_forward_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.tx_str_fwd = !enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_flush_trans_fifo_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.flush_tx_fifo = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_transmit_threshold(emac_dma_dev_t *dma_regs, uint32_t threshold)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.tx_thresh_ctrl = threshold;
|
||||
}
|
||||
|
||||
static inline void emac_ll_start_stop_dma_transmit(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.start_stop_transmission_command = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_forward_err_frame_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.fwd_err_frame = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_forward_undersized_good_frame_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.fwd_under_gf = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_recv_threshold(emac_dma_dev_t *dma_regs, uint32_t threshold)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.rx_thresh_ctrl = threshold;
|
||||
}
|
||||
|
||||
static inline void emac_ll_opt_second_frame_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.opt_second_frame = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_start_stop_dma_receive(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmaoperation_mode.start_stop_rx = enable;
|
||||
}
|
||||
|
||||
/* dmabusmode */
|
||||
static inline void emac_ll_mixed_burst_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmabusmode.dmamixedburst = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_addr_align_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmabusmode.dmaaddralibea = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_use_separate_pbl_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmabusmode.use_sep_pbl = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_rx_dma_pbl(emac_dma_dev_t *dma_regs, uint32_t pbl)
|
||||
{
|
||||
dma_regs->dmabusmode.rx_dma_pbl = pbl;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_prog_burst_len(emac_dma_dev_t *dma_regs, uint32_t len)
|
||||
{
|
||||
dma_regs->dmabusmode.prog_burst_len = len;
|
||||
}
|
||||
|
||||
static inline void emac_ll_enhance_desc_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmabusmode.alt_desc_size = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_desc_skip_len(emac_dma_dev_t *dma_regs, uint32_t len)
|
||||
{
|
||||
dma_regs->dmabusmode.desc_skip_len = len;
|
||||
}
|
||||
|
||||
static inline void emac_ll_fixed_arbitration_enable(emac_dma_dev_t *dma_regs, bool enable)
|
||||
{
|
||||
dma_regs->dmabusmode.dma_arb_sch = enable;
|
||||
}
|
||||
|
||||
static inline void emac_ll_set_priority_ratio(emac_dma_dev_t *dma_regs, uint32_t ratio)
|
||||
{
|
||||
dma_regs->dmabusmode.pri_ratio = ratio;
|
||||
}
|
||||
|
||||
/* dmain_en */
|
||||
static inline void emac_ll_enable_all_intr(emac_dma_dev_t *dma_regs)
|
||||
{
|
||||
dma_regs->dmain_en.val = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
static inline void emac_ll_disable_all_intr(emac_dma_dev_t *dma_regs)
|
||||
{
|
||||
dma_regs->dmain_en.val = 0x00000000;
|
||||
}
|
||||
|
||||
static inline void emac_ll_enable_corresponding_intr(emac_dma_dev_t *dma_regs, uint32_t mask)
|
||||
{
|
||||
dma_regs->dmain_en.val |= mask;
|
||||
}
|
||||
|
||||
static inline void emac_ll_disable_corresponding_intr(emac_dma_dev_t *dma_regs, uint32_t mask)
|
||||
{
|
||||
dma_regs->dmain_en.val &= ~mask;
|
||||
}
|
||||
|
||||
static inline uint32_t emac_ll_get_intr_enable_status(emac_dma_dev_t *dma_regs)
|
||||
{
|
||||
return dma_regs->dmain_en.val;
|
||||
}
|
||||
|
||||
/* dmastatus */
|
||||
__attribute__((always_inline)) static inline uint32_t emac_ll_get_intr_status(emac_dma_dev_t *dma_regs)
|
||||
{
|
||||
return dma_regs->dmastatus.val;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void emac_ll_clear_corresponding_intr(emac_dma_dev_t *dma_regs, uint32_t bits)
|
||||
{
|
||||
dma_regs->dmastatus.val = bits;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void emac_ll_clear_all_pending_intr(emac_dma_dev_t *dma_regs)
|
||||
{
|
||||
dma_regs->dmastatus.val = 0xFFFFFFFF;
|
||||
}
|
||||
|
||||
|
||||
/* dmatxpolldemand / dmarxpolldemand */
|
||||
static inline void emac_ll_transmit_poll_demand(emac_dma_dev_t *dma_regs, uint32_t val)
|
||||
{
|
||||
dma_regs->dmatxpolldemand = val;
|
||||
}
|
||||
static inline void emac_ll_receive_poll_demand(emac_dma_dev_t *dma_regs, uint32_t val)
|
||||
{
|
||||
dma_regs->dmarxpolldemand = val;
|
||||
}
|
||||
|
||||
/*************** End of dma regs operation *********************/
|
||||
|
||||
|
||||
|
||||
/************** Start of ext regs operation ********************/
|
||||
static inline void emac_ll_clock_enable_mii(emac_ext_dev_t *ext_regs)
|
||||
{
|
||||
/* 0 for mii mode */
|
||||
ext_regs->ex_phyinf_conf.phy_intf_sel = 0;
|
||||
ext_regs->ex_clk_ctrl.mii_clk_rx_en = 1;
|
||||
ext_regs->ex_clk_ctrl.mii_clk_tx_en = 1;
|
||||
}
|
||||
|
||||
static inline void emac_ll_clock_enable_rmii_input(emac_ext_dev_t *ext_regs)
|
||||
{
|
||||
/* 4 for rmii mode */
|
||||
ext_regs->ex_phyinf_conf.phy_intf_sel = 4;
|
||||
/* ref clk for phy is input in rmii mode, the clk can be offered by mac layer or external crystal.
|
||||
config pin as output to generate ref clk by esp32 mac layer or input to obtain the clock from external crystal */
|
||||
ext_regs->ex_clk_ctrl.ext_en = 1;
|
||||
ext_regs->ex_clk_ctrl.int_en = 0;
|
||||
ext_regs->ex_oscclk_conf.clk_sel = 1;
|
||||
}
|
||||
|
||||
static inline void emac_ll_clock_enable_rmii_output(emac_ext_dev_t *ext_regs)
|
||||
{
|
||||
/* 4 for rmii mode */
|
||||
ext_regs->ex_phyinf_conf.phy_intf_sel = 4;
|
||||
/* ref clk for phy is input in rmii mode, the clk can be offered by mac layer or external crystal.
|
||||
config pin as output to generate ref clk by esp32 mac layer or input to obtain the clock from external crystal */
|
||||
ext_regs->ex_clk_ctrl.ext_en = 0;
|
||||
ext_regs->ex_clk_ctrl.int_en = 1;
|
||||
ext_regs->ex_oscclk_conf.clk_sel = 0;
|
||||
ext_regs->ex_clkout_conf.div_num = 0;
|
||||
ext_regs->ex_clkout_conf.h_div_num = 0;
|
||||
}
|
||||
|
||||
|
||||
static inline void emac_ll_pause_frame_enable(emac_ext_dev_t *ext_regs, bool enable)
|
||||
{
|
||||
ext_regs->ex_phyinf_conf.sbd_flowctrl = enable;
|
||||
}
|
||||
/*************** End of ext regs operation *********************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user