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run WiFi on ESP32SBETA

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This commit is contained in:
Xia Xiaotian
2019-06-17 11:50:37 +08:00
parent b395279196
commit 99ef587a05
36 changed files with 995 additions and 68 deletions
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4
components/soc/esp32s2beta/include/soc/rtc.h
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@@ -598,6 +598,7 @@ typedef struct {
uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
uint32_t xtal_fpu : 1;
uint32_t bbpll_fpu : 1;
uint32_t cpu_waiti_clk_gate : 1;
} rtc_config_t;
/**
@@ -614,7 +615,8 @@ typedef struct {
.pwrctl_init = 1, \
.rtc_dboost_fpd = 1, \
.xtal_fpu = 0, \
.bbpll_fpu = 0 \
.bbpll_fpu = 0, \
.cpu_waiti_clk_gate = 1\
}
/**

2
components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h
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@@ -329,7 +329,7 @@ extern "C" {
#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF
#define RTC_CNTL_PLL_BUF_WAIT_S 24
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 100
/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
/*description: XTAL wait cycles in slow_clk_rtc*/
#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF

6
components/soc/esp32s2beta/include/soc/syscon_reg.h
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@@ -793,9 +793,9 @@ extern "C" {
/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
Bit15 not included here because of the bit now can't be cleared */
#define DPORT_WIFI_CLK_WIFI_EN 0x003807cf
#define DPORT_WIFI_CLK_WIFI_EN 0x00008040
#define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
#define DPORT_WIFI_CLK_WIFI_EN_V 0x7cf
#define DPORT_WIFI_CLK_WIFI_EN_V 0x0804
#define DPORT_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits - 11, 16, 17 */
#define DPORT_WIFI_CLK_BT_EN 0x61
@@ -803,7 +803,7 @@ extern "C" {
#define DPORT_WIFI_CLK_BT_EN_V 0x61
#define DPORT_WIFI_CLK_BT_EN_S 11
/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x0038078f
/* Digital team to check */
//bluetooth baseband bit11

2
components/soc/esp32s2beta/include/soc/wdev_reg.h
View File

@@ -17,5 +17,5 @@
#include "soc.h"
/* Hardware random number generator register */
#define WDEV_RND_REG 0x60035100
#define WDEV_RND_REG 0x6003510C