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refactor(rng): refactor to use hal/ll apis for S3

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gaoxu
2025-07-26 20:35:16 +08:00
committed by Gao Xu
parent 2fbd8779d6
commit 9a57629e73
7 changed files with 153 additions and 85 deletions
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79
components/hal/esp32s3/include/hal/adc_ll.h
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@@ -253,6 +253,17 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
}
}
/**
* Rest pattern table to default value
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
for(int i = 0; i < 4; i++) {
APB_SARADC.sar1_patt_tab[i].sar1_patt_tab = 0xffffff;
APB_SARADC.sar2_patt_tab[i].sar2_patt_tab = 0xffffff;
}
}
/**
* Set pattern table for digital controller.
* The pattern table that defines the conversion rules for each SAR ADC. Each table has 12 items, in which channel selection,
@@ -619,20 +630,20 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
* @brief Enable the ADC clock
* @param enable true to enable, false to disable
*/
static inline void adc_ll_enable_bus_clock(bool enable)
static inline void _adc_ll_enable_bus_clock(bool enable)
{
SYSTEM.perip_clk_en0.apb_saradc_clk_en = enable;
}
// SYSTEM.perip_clk_en0 is a shared register, so this function must be used in an atomic way
#define adc_ll_enable_bus_clock(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
adc_ll_enable_bus_clock(__VA_ARGS__); \
_adc_ll_enable_bus_clock(__VA_ARGS__); \
} while(0)
/**
* @brief Reset ADC module
*/
static inline void adc_ll_reset_register(void)
static inline void _adc_ll_reset_register(void)
{
SYSTEM.perip_rst_en0.apb_saradc_rst = 1;
SYSTEM.perip_rst_en0.apb_saradc_rst = 0;
@@ -640,7 +651,7 @@ static inline void adc_ll_reset_register(void)
// SYSTEM.perip_rst_en0 is a shared register, so this function must be used in an atomic way
#define adc_ll_reset_register(...) do { \
(void)__DECLARE_RCC_ATOMIC_ENV; \
adc_ll_reset_register(__VA_ARGS__); \
_adc_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
@@ -888,6 +899,66 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param
}
}
/**
* Set the SAR DTEST param
*
* @param param DTEST value
*/
__attribute__((always_inline))
static inline void adc_ll_set_dtest_param(uint32_t param)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, param);
}
/**
* Set the SAR ENT param
*
* @param param ENT value
*/
__attribute__((always_inline))
static inline void adc_ll_set_ent_param(uint32_t param)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, param);
}
/**
* Enable/disable the calibration voltage reference for ADC unit.
*
* @param adc_n ADC index number.
* @param en true to enable, false to disable
*/
__attribute__((always_inline))
static inline void adc_ll_enable_calibration_ref(adc_unit_t adc_n, bool en)
{
(void)adc_n;
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENCAL_REF_ADDR, en);
}
/**
* Init regi2c SARADC registers
*/
__attribute__((always_inline))
static inline void adc_ll_regi2c_init(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(1);
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
adc_ll_enable_calibration_ref(ADC_UNIT_1, true);
adc_ll_enable_calibration_ref(ADC_UNIT_2, true);
}
/**
* Deinit regi2c SARADC registers
*/
__attribute__((always_inline))
static inline void adc_ll_regi2c_adc_deinit(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(0);
adc_ll_enable_calibration_ref(ADC_UNIT_1, false);
adc_ll_enable_calibration_ref(ADC_UNIT_2, false);
}
/**
* Output ADC internal reference voltage to channels, only available for ADC2 on ESP32.
*