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fix(panic): fixed cache error being reported as illegal instruction

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On riscv chips accessing cache mapped memory regions over the ibus would
result in an illegal instructions exception triggering faster than the cache
error interrupt/exception.

Added a cache error check in the panic handler, if any cache errors are active
the panic handler will now report a cache error, even if the trigger exception
was a illegal instructions.
This commit is contained in:
Marius Vikhammer
2023-11-28 09:57:44 +08:00
parent 30eb2918c6
commit 9a6de4cb3e
14 changed files with 349 additions and 122 deletions
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9
tools/test_apps/system/panic/pytest_panic.py
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@@ -260,9 +260,12 @@ def test_int_wdt_cache_disabled(
@pytest.mark.generic
def test_cache_error(dut: PanicTestDut, config: str, test_func_name: str) -> None:
dut.run_test_func(test_func_name)
if dut.target in ['esp32c3', 'esp32c2', 'esp32c6', 'esp32h2']:
# Cache error interrupt is not raised, IDF-6398
dut.expect_gme('Illegal instruction')
if dut.target in ['esp32c3', 'esp32c2']:
dut.expect_gme('Cache error')
dut.expect_exact('Cached memory region accessed while ibus or cache is disabled')
elif dut.target in ['esp32c6', 'esp32h2']:
dut.expect_gme('Cache error')
dut.expect_exact('Cache access error')
elif dut.target in ['esp32s2']:
# Cache error interrupt is not enabled, IDF-1558
dut.expect_gme('IllegalInstruction')