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hal: added HAL_ASSERT

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This commit is contained in:
morris
2021-05-19 10:53:21 +08:00
parent ed428ab811
commit 9afdf54748
47 changed files with 328 additions and 186 deletions
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32
components/hal/esp32s2/include/hal/memprot_ll.h
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@@ -14,6 +14,8 @@
#pragma once
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -149,7 +151,7 @@ static inline bool esp_memprot_iram0_sram_is_intr_mine(void)
//block 0-3
static inline void esp_memprot_iram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm, bool exec_perm)
{
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
uint32_t write_bit, read_bit, exec_bit;
switch (block) {
@@ -198,7 +200,7 @@ static inline void esp_memprot_iram0_sram_set_uni_block_perm(uint32_t block, boo
static inline uint32_t esp_memprot_iram0_sram_get_uni_block_read_bit(uint32_t block)
{
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
switch (block) {
case IRAM0_SRAM_UNI_BLOCK_0:
@@ -216,7 +218,7 @@ static inline uint32_t esp_memprot_iram0_sram_get_uni_block_read_bit(uint32_t bl
static inline uint32_t esp_memprot_iram0_sram_get_uni_block_write_bit(uint32_t block)
{
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
switch (block) {
case IRAM0_SRAM_UNI_BLOCK_0:
@@ -234,7 +236,7 @@ static inline uint32_t esp_memprot_iram0_sram_get_uni_block_write_bit(uint32_t b
static inline uint32_t esp_memprot_iram0_sram_get_uni_block_exec_bit(uint32_t block)
{
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
switch (block) {
case IRAM0_SRAM_UNI_BLOCK_0:
@@ -252,7 +254,7 @@ static inline uint32_t esp_memprot_iram0_sram_get_uni_block_exec_bit(uint32_t bl
static inline void esp_memprot_iram0_sram_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit, uint32_t *exec_bit)
{
assert(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
HAL_ASSERT(block < IRAM0_SRAM_TOTAL_UNI_BLOCKS);
switch (block) {
case IRAM0_SRAM_UNI_BLOCK_0:
@@ -293,8 +295,8 @@ static inline uint32_t esp_memprot_iram0_sram_get_perm_split_reg(void)
static inline void esp_memprot_iram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
{
uint32_t addr = (uint32_t)split_addr;
assert(addr <= IRAM0_SRAM_SPL_BLOCK_HIGH);
assert(addr % 0x4 == 0);
HAL_ASSERT(addr <= IRAM0_SRAM_SPL_BLOCK_HIGH);
HAL_ASSERT(addr % 0x4 == 0);
//find possible split.address in low region blocks
int uni_blocks_low = -1;
@@ -437,7 +439,7 @@ static inline uint32_t esp_memprot_iram0_rtcfast_get_perm_split_reg(void)
static inline void esp_memprot_iram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
HAL_ASSERT(addr % 0x4 == 0);
//conf reg [10:0]
uint32_t reg_split_addr = IRAM0_RTCFAST_ADDR_TO_CONF_REG(addr);
@@ -626,7 +628,7 @@ static inline bool esp_memprot_dram0_sram_is_intr_mine(void)
static inline void esp_memprot_dram0_sram_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit)
{
assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
HAL_ASSERT(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
switch (block) {
case DRAM0_SRAM_UNI_BLOCK_0:
@@ -652,7 +654,7 @@ static inline void esp_memprot_dram0_sram_get_uni_block_sgnf_bits(uint32_t block
static inline void esp_memprot_dram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm)
{
assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
HAL_ASSERT(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
uint32_t write_bit, read_bit;
esp_memprot_dram0_sram_get_uni_block_sgnf_bits(block, &write_bit, &read_bit);
@@ -672,7 +674,7 @@ static inline void esp_memprot_dram0_sram_set_uni_block_perm(uint32_t block, boo
static inline uint32_t esp_memprot_dram0_sram_get_uni_block_read_bit(uint32_t block)
{
assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
HAL_ASSERT(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
switch (block) {
case DRAM0_SRAM_UNI_BLOCK_0:
@@ -690,7 +692,7 @@ static inline uint32_t esp_memprot_dram0_sram_get_uni_block_read_bit(uint32_t bl
static inline uint32_t esp_memprot_dram0_sram_get_uni_block_write_bit(uint32_t block)
{
assert(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
HAL_ASSERT(block < DRAM0_SRAM_TOTAL_UNI_BLOCKS);
switch (block) {
case DRAM0_SRAM_UNI_BLOCK_0:
@@ -717,8 +719,8 @@ static inline void esp_memprot_dram0_sram_set_prot(uint32_t *split_addr, bool lw
uint32_t addr = (uint32_t)split_addr;
//low boundary check provided by LD script. see comment in esp_memprot_iram0_sram_set_prot()
assert( addr <= DRAM0_SRAM_SPL_BLOCK_HIGH );
assert( addr % 0x4 == 0 );
HAL_ASSERT(addr <= DRAM0_SRAM_SPL_BLOCK_HIGH);
HAL_ASSERT(addr % 0x4 == 0 );
//set low region
int uni_blocks_low = -1;
@@ -828,7 +830,7 @@ static inline bool esp_memprot_dram0_rtcfast_is_intr_mine(void)
static inline void esp_memprot_dram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
HAL_ASSERT(addr % 0x4 == 0);
//conf reg [10:0]
uint32_t reg_split_addr = DRAM0_RTCFAST_ADDR_TO_CONF_REG( addr );

8
components/hal/esp32s2/include/hal/memprot_peri_ll.h
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@@ -14,6 +14,8 @@
#pragma once
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -140,7 +142,7 @@ static inline bool esp_memprot_peri1_rtcslow_is_intr_mine(void)
static inline void esp_memprot_peri1_rtcslow_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
HAL_ASSERT(addr % 0x4 == 0);
uint32_t reg_split_addr = PERI1_RTCSLOW_ADDR_TO_CONF_REG(addr);
@@ -302,7 +304,7 @@ static inline bool esp_memprot_peri2_rtcslow_0_is_intr_mine(void)
static inline void esp_memprot_peri2_rtcslow_0_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
HAL_ASSERT(addr % 0x4 == 0);
uint32_t reg_split_addr = PERI2_RTCSLOW_0_ADDR_TO_CONF_REG(addr);
@@ -387,7 +389,7 @@ static inline bool esp_memprot_peri2_rtcslow_1_is_intr_mine(void)
static inline void esp_memprot_peri2_rtcslow_1_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
{
uint32_t addr = (uint32_t)split_addr;
assert( addr % 0x4 == 0 );
HAL_ASSERT(addr % 0x4 == 0);
uint32_t reg_split_addr = PERI2_RTCSLOW_1_ADDR_TO_CONF_REG(addr);

8
components/hal/esp32s2/include/hal/spi_flash_encrypted_ll.h
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@@ -20,12 +20,12 @@
// The Lowlevel layer for SPI Flash Encryption.
#include <stdbool.h>
#include <string.h>
#include "soc/system_reg.h"
#include "soc/hwcrypto_reg.h"
#include "soc/soc.h"
#include "string.h"
#include "assert.h"
#include <stdbool.h>
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
@@ -77,7 +77,7 @@ static inline void spi_flash_encrypt_ll_disable(void)
static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{
// Our hardware only support flash encryption
assert(type == FLASH_ENCRYPTION_MANU);
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
REG_WRITE(AES_XTS_DESTINATION_REG, type);
}

17
components/hal/esp32s2/include/hal/spi_ll.h
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@@ -24,11 +24,12 @@
#include <stdlib.h> //for abs()
#include <string.h>
#include "hal/hal_defs.h"
#include "esp_types.h"
#include "soc/spi_periph.h"
#include "esp32s2/rom/lldesc.h"
#include "esp_attr.h"
#include "soc/spi_periph.h"
#include "soc/lldesc.h"
#include "hal/assert.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@@ -39,7 +40,7 @@ extern "C" {
/// Interrupt not used. Don't use in app.
#define SPI_LL_UNUSED_INT_MASK (SPI_INT_TRANS_DONE_EN | SPI_INT_WR_DMA_DONE_EN | SPI_INT_RD_DMA_DONE_EN | SPI_INT_WR_BUF_DONE_EN | SPI_INT_RD_BUF_DONE_EN)
/// Swap the bit order to its correct place to send
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
/// This is the expected clock frequency
#define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : &GPSPI3))
@@ -360,9 +361,9 @@ static inline void spi_ll_read_buffer_byte(spi_dev_t *hw, int byte_addr, uint8_t
static inline void spi_ll_write_buffer_byte(spi_dev_t *hw, int byte_addr, uint8_t *data, int len)
{
assert( byte_addr + len <= 72);
assert(len > 0);
assert(byte_addr >= 0);
HAL_ASSERT(byte_addr + len <= 72);
HAL_ASSERT(len > 0);
HAL_ASSERT(byte_addr >= 0);
while (len > 0) {
uint32_t word;
@@ -1088,7 +1089,7 @@ static inline void spi_dma_ll_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel)
{
//Reset RX DMA peripheral
dma_in->dma_in_link.dma_rx_ena = 0;
assert(dma_in->dma_in_link.dma_rx_ena == 0);
HAL_ASSERT(dma_in->dma_in_link.dma_rx_ena == 0);
dma_in->dma_conf.in_rst = 1;
dma_in->dma_conf.in_rst = 0;

4
components/hal/esp32s2/include/hal/systimer_ll.h
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@@ -15,8 +15,8 @@
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include "soc/systimer_struct.h"
#include "hal/assert.h"
#define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time
#define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time
@@ -131,7 +131,7 @@ __attribute__((always_inline)) static inline void systimer_ll_enable_alarm_perio
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
{
assert(period < (1 << 30));
HAL_ASSERT(period < (1 << 30));
dev->target_conf[alarm_id].target_period = period;
}

5
components/hal/esp32s2/include/hal/timer_ll.h
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@@ -22,8 +22,9 @@ extern "C" {
#endif
#include <stdlib.h>
#include "hal/timer_types.h"
#include "soc/timer_periph.h"
#include "hal/timer_types.h"
#include "hal/assert.h"
_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
_Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
@@ -43,7 +44,7 @@ _Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt
*/
static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider)
{
assert(divider >= 2 && divider <= 65536);
HAL_ASSERT(divider >= 2 && divider <= 65536);
if (divider >= 65536) {
divider = 0;
}

13
components/hal/esp32s2/include/hal/twai_ll.h
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@@ -28,6 +28,7 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "hal/twai_types.h"
#include "soc/twai_periph.h"
@@ -482,8 +483,8 @@ static inline void twai_ll_set_tec(twai_dev_t *hw, uint32_t tec)
*/
static inline void twai_ll_set_acc_filter(twai_dev_t* hw, uint32_t code, uint32_t mask, bool single_filter)
{
uint32_t code_swapped = __builtin_bswap32(code);
uint32_t mask_swapped = __builtin_bswap32(mask);
uint32_t code_swapped = HAL_SWAP32(code);
uint32_t mask_swapped = HAL_SWAP32(mask);
for (int i = 0; i < 4; i++) {
hw->acceptance_filter.acr[i].byte = ((code_swapped >> (i * 8)) & 0xFF);
hw->acceptance_filter.amr[i].byte = ((mask_swapped >> (i * 8)) & 0xFF);
@@ -555,12 +556,12 @@ static inline void twai_ll_format_frame_buffer(uint32_t id, uint8_t dlc, const u
//Set ID. The ID registers are big endian and left aligned, therefore a bswap will be required
if (is_extd) {
uint32_t id_temp = __builtin_bswap32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
uint32_t id_temp = HAL_SWAP32((id & TWAI_EXTD_ID_MASK) << 3); //((id << 3) >> 8*(3-i))
for (int i = 0; i < 4; i++) {
tx_frame->extended.id[i] = (id_temp >> (8 * i)) & 0xFF;
}
} else {
uint32_t id_temp = __builtin_bswap16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
uint32_t id_temp = HAL_SWAP16((id & TWAI_STD_ID_MASK) << 5); //((id << 5) >> 8*(1-i))
for (int i = 0; i < 2; i++) {
tx_frame->standard.id[i] = (id_temp >> (8 * i)) & 0xFF;
}
@@ -600,14 +601,14 @@ static inline void twai_ll_prase_frame_buffer(twai_ll_frame_buffer_t *rx_frame,
for (int i = 0; i < 4; i++) {
id_temp |= rx_frame->extended.id[i] << (8 * i);
}
id_temp = __builtin_bswap32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
id_temp = HAL_SWAP32(id_temp) >> 3; //((byte[i] << 8*(3-i)) >> 3)
*id = id_temp & TWAI_EXTD_ID_MASK;
} else {
uint32_t id_temp = 0;
for (int i = 0; i < 2; i++) {
id_temp |= rx_frame->standard.id[i] << (8 * i);
}
id_temp = __builtin_bswap16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
id_temp = HAL_SWAP16(id_temp) >> 5; //((byte[i] << 8*(1-i)) >> 5)
*id = id_temp & TWAI_STD_ID_MASK;
}