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feat(hal/sha): use RCC atomic block to enable/reset the SHA peripheral

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harshal.patil
2024-03-08 00:40:26 +05:30
parent 211a2a5477
commit 9cd10e196b
18 changed files with 375 additions and 55 deletions
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37
components/hal/esp32s3/include/hal/sha_ll.h
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@@ -1,19 +1,50 @@
/*
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "soc/hwcrypto_reg.h"
#include "hal/sha_types.h"
#include "soc/dport_reg.h"
#include "soc/hwcrypto_reg.h"
#include "soc/system_struct.h"
#include "hal/sha_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the bus clock for SHA peripheral module
*
* @param enable true to enable the module, false to disable the module
*/
static inline void sha_ll_enable_bus_clock(bool enable)
{
SYSTEM.perip_clk_en1.crypto_sha_clk_en = enable;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset the SHA peripheral module
*/
static inline void sha_ll_reset_register(void)
{
SYSTEM.perip_rst_en1.crypto_sha_rst = 1;
SYSTEM.perip_rst_en1.crypto_sha_rst = 0;
// Clear reset on digital signature and hmac also, otherwise SHA is held in reset
SYSTEM.perip_rst_en1.crypto_ds_rst = 0;
SYSTEM.perip_rst_en1.crypto_hmac_rst = 0;
}
/// use a macro to wrap the function, force the caller to use it in a critical section
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define sha_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; sha_ll_reset_register(__VA_ARGS__)
/**
* @brief Start a new SHA block conversions (no initial hash in HW)