Merge branch 'feature/esp32h2_gpio_support' into 'master'

gpio: Add support for esp32h2 Closes IDF-6227, IDF-6388, IDF-6403, and IDF-6676 See merge request espressif/esp-idf!21986
2025-11-27 21:15:37 +00:00 · 2023-01-18 16:24:13 +08:00
parent 7e7533d3a1 4c8fdc31f9
commit 9db3865cb7
26 changed files with 557 additions and 299 deletions
--- a/components/soc/esp32h2/gpio_periph.c
+++ b/components/soc/esp32h2/gpio_periph.c
@@ -1,12 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 #include "soc/gpio_periph.h"

-const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
+const uint32_t GPIO_PIN_MUX_REG[] = {
    IO_MUX_GPIO0_REG,
    IO_MUX_GPIO1_REG,
    IO_MUX_GPIO2_REG,
@@ -37,7 +37,9 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
    IO_MUX_GPIO27_REG
 };

-const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
+_Static_assert(sizeof(GPIO_PIN_MUX_REG) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_PIN_MUX_REG");
+
+const uint32_t GPIO_HOLD_MASK[] = {
    BIT(0),          //GPIO0   // LP_AON_GPIO_HOLD0_REG
    BIT(1),          //GPIO1
    BIT(2),          //GPIO2
@@ -67,3 +69,5 @@ const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
    BIT(26),         //GPIO26
    BIT(27),         //GPIO27
 };
+
+_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -221,11 +221,7 @@ config SOC_GPIO_PORT

 config SOC_GPIO_PIN_COUNT
    int
-    default 31
-
-config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
-    bool
-    default y
+    default 28

 config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
    bool
@@ -237,7 +233,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK

 config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
    hex
-    default 0x000000007FFFFF00
+    default 0x000000000FFF807F

 config SOC_GPIO_SUPPORT_SLP_SWITCH
    bool
--- a/components/soc/esp32h2/include/soc/clkout_channel.h
+++ b/components/soc/esp32h2/include/soc/clkout_channel.h
@@ -1,15 +1,8 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 #pragma once

-//CLKOUT channels
-// ESP32H2-TODO: IDF-6388 please check
-#define CLKOUT_GPIO20_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
-#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM     20
-#define CLKOUT_GPIO19_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
-#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM     19
-#define CLKOUT_GPIO18_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
-#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM     18
+// ESP32H2 CLKOUT signals has no corresponding iomux pins
--- a/components/soc/esp32h2/include/soc/gpio_pins.h
+++ b/components/soc/esp32h2/include/soc/gpio_pins.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -11,8 +11,9 @@
 extern "C" {
 #endif

-#define GPIO_MATRIX_CONST_ONE_INPUT   (0x1E)
-#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x1F)
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
+#define GPIO_MATRIX_INVALID           (0x3A)

 #ifdef __cplusplus
 }
--- a/components/soc/esp32h2/include/soc/io_mux_reg.h
+++ b/components/soc/esp32h2/include/soc/io_mux_reg.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -63,15 +63,33 @@
 #define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
 #define MCU_SEL_V 0x7
 #define MCU_SEL_S 12
+/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
+#define FILTER_EN (BIT(15))
+#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
+#define FILTER_EN_V 1
+#define FILTER_EN_S 15

-#define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
-#define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
-#define PIN_PULLUP_DIS(PIN_NAME)                 REG_CLR_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLUP_EN(PIN_NAME)                  REG_SET_BIT(PIN_NAME, FUN_PU)
-#define PIN_PULLDWN_DIS(PIN_NAME)             REG_CLR_BIT(PIN_NAME, FUN_PD)
-#define PIN_PULLDWN_EN(PIN_NAME)              REG_SET_BIT(PIN_NAME, FUN_PD)
-#define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_SLP_INPUT_ENABLE(PIN_NAME)      SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_INPUT_DISABLE(PIN_NAME)     CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
+#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
+#define PIN_SLP_PULLUP_ENABLE(PIN_NAME)     SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLUP_DISABLE(PIN_NAME)    CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
+#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME)   SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME)  CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
+#define PIN_SLP_SEL_ENABLE(PIN_NAME)        SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+#define PIN_SLP_SEL_DISABLE(PIN_NAME)       CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
+
+#define PIN_INPUT_ENABLE(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)          REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)           REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)            REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)     REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+#define PIN_FILTER_EN(PIN_NAME)             REG_SET_BIT(PIN_NAME, FILTER_EN)
+#define PIN_FILTER_DIS(PIN_NAME)            REG_CLR_BIT(PIN_NAME, FILTER_EN)

 #define IO_MUX_GPIO0_REG               PERIPHS_IO_MUX_GPIO0_U
 #define IO_MUX_GPIO1_REG               PERIPHS_IO_MUX_GPIO1_U
@@ -102,7 +120,6 @@
 #define IO_MUX_GPIO26_REG              PERIPHS_IO_MUX_GPIO26_U
 #define IO_MUX_GPIO27_REG              PERIPHS_IO_MUX_GPIO27_U

-#define FUNC_GPIO_GPIO                              1
 #define PIN_FUNC_GPIO								1

 #define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
@@ -116,25 +133,17 @@
 #define SPI_D_GPIO_NUM               20
 #define SPI_Q_GPIO_NUM               16

-#define MAX_RTC_GPIO_NUM              7
+#define USB_DM_GPIO_NUM              26
+#define USB_DP_GPIO_NUM              27
+
+#define MAX_RTC_GPIO_NUM             14            // GPIO7~14 are the pads with LP function
 #define MAX_PAD_GPIO_NUM             27
 #define MAX_GPIO_NUM                 31
 #define HIGH_IO_HOLD_BIT_SHIFT       32
-#define GPIO_NUM_IN_FORCE_0          0x3c
-#define GPIO_NUM_IN_FORCE_1          0x38
-#define GPIO_NUM_IN_INVALID          0x3a
+

 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
 #define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
-#define PAD_POWER_SEL                               BIT(15)
-#define PAD_POWER_SEL_V                             0x1
-#define PAD_POWER_SEL_M                             BIT(15)
-#define PAD_POWER_SEL_S                             15
-
-#define PAD_POWER_SWITCH_DELAY                      0x7
-#define PAD_POWER_SWITCH_DELAY_V                    0x7
-#define PAD_POWER_SWITCH_DELAY_M                    (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
-#define PAD_POWER_SWITCH_DELAY_S                    12

 #define CLK_OUT3                                    IO_MUX_CLK_OUT3
 #define CLK_OUT3_V                                  IO_MUX_CLK_OUT3_V
@@ -274,40 +283,64 @@
 #define FUNC_GPIO27_GPIO27                                          1
 #define FUNC_GPIO27_GPIO27_0                                        0

-#define IO_MUX_PIN_CTRL_REG          (REG_IO_MUX_BASE + 0x0)
-/* IO_MUX_CLK_OUT3 : R/W ;bitpos:[14:10] ;default: 5'h7 ; */
-/*description: If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. C
-LK_OUT_out3 can be found in peripheral output signals..*/
-#define IO_MUX_CLK_OUT3    0x0000001F
-#define IO_MUX_CLK_OUT3_M  ((IO_MUX_CLK_OUT3_V)<<(IO_MUX_CLK_OUT3_S))
-#define IO_MUX_CLK_OUT3_V  0x1F
-#define IO_MUX_CLK_OUT3_S  10
-/* IO_MUX_CLK_OUT2 : R/W ;bitpos:[9:5] ;default: 5'hf ; */
-/*description: If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. C
-LK_OUT_out2 can be found in peripheral output signals..*/
-#define IO_MUX_CLK_OUT2    0x0000001F
-#define IO_MUX_CLK_OUT2_M  ((IO_MUX_CLK_OUT2_V)<<(IO_MUX_CLK_OUT2_S))
-#define IO_MUX_CLK_OUT2_V  0x1F
-#define IO_MUX_CLK_OUT2_S  5
-/* IO_MUX_CLK_OUT1 : R/W ;bitpos:[4:0] ;default: 5'hf ; */
-/*description: If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. C
-LK_OUT_out1 can be found in peripheral output signals..*/
+/** IO_MUX_PIN_CTRL_REG register
+ *  Clock Output Configuration
+ *  Register
+ */
+#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
+/* IO_MUX_CLK_OUT1 : R/W; bitpos: [5:0]; default: 15;
+ * If you want to output clock for I2S to CLK_OUT_out1, set this register
+ * to 0x0. CLK_OUT_out1 can be found in peripheral output
+ * signals.
+ */
 #define IO_MUX_CLK_OUT1    0x0000001F
-#define IO_MUX_CLK_OUT1_M  ((IO_MUX_CLK_OUT1_V)<<(IO_MUX_CLK_OUT1_S))
-#define IO_MUX_CLK_OUT1_V  0x1F
+#define IO_MUX_CLK_OUT1_M  (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
+#define IO_MUX_CLK_OUT1_V  0x0000001F
 #define IO_MUX_CLK_OUT1_S  0
-#define IO_MUX_MODEM_DIAG_EN_REG          (REG_IO_MUX_BASE + 0xBC)
-/* IO_MUX_MODEM_DIAG_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio
- matrix. 0:enable other signals into gpio matrix.*/
+/* IO_MUX_CLK_OUT2 : R/W; bitpos: [10:5]; default: 15;
+ * If you want to output clock for I2S to CLK_OUT_out2, set this register
+ * to 0x0. CLK_OUT_out2 can be found in peripheral output
+ * signals.
+ */
+#define IO_MUX_CLK_OUT2    0x0000001F
+#define IO_MUX_CLK_OUT2_M  (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
+#define IO_MUX_CLK_OUT2_V  0x0000001F
+#define IO_MUX_CLK_OUT2_S  5
+/* IO_MUX_CLK_OUT3 : R/W; bitpos: [15:10]; default: 7;
+ * If you want to output clock for I2S to CLK_OUT_out3, set this register
+ * to 0x0. CLK_OUT_out3 can be found in peripheral output
+ * signals.
+ */
+#define IO_MUX_CLK_OUT3    0x0000001F
+#define IO_MUX_CLK_OUT3_M  (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
+#define IO_MUX_CLK_OUT3_V  0x0000001F
+#define IO_MUX_CLK_OUT3_S  10
+
+/** IO_MUX_MODEM_DIAG_EN_REG register
+ *  GPIO MATRIX Configure Register for modem
+ *  diag
+ */
+#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc)
+/* IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [32:0]; default: 0;
+ * bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i]
+ * into gpio matrix. 0:enable other signals into gpio
+ * matrix
+ */
 #define IO_MUX_MODEM_DIAG_EN    0xFFFFFFFF
-#define IO_MUX_MODEM_DIAG_EN_M  ((IO_MUX_MODEM_DIAG_EN_V)<<(IO_MUX_MODEM_DIAG_EN_S))
+#define IO_MUX_MODEM_DIAG_EN_M  (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S)
 #define IO_MUX_MODEM_DIAG_EN_V  0xFFFFFFFF
 #define IO_MUX_MODEM_DIAG_EN_S  0
-#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0xFC)
-/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2207270 ; */
-/*description: Version control register.*/
+
+/** IO_MUX_DATE_REG register
+ *  IO MUX Version Control
+ *  Register
+ */
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+/* IO_MUX_REG_DATE : R/W; bitpos: [28:0]; default: 35680880;
+ * Version control
+ * register
+ */
 #define IO_MUX_REG_DATE    0x0FFFFFFF
-#define IO_MUX_REG_DATE_M  ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S))
-#define IO_MUX_REG_DATE_V  0xFFFFFFF
+#define IO_MUX_REG_DATE_M  (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
+#define IO_MUX_REG_DATE_V  0x0FFFFFFF
 #define IO_MUX_REG_DATE_S  0
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -144,22 +144,21 @@
 #define SOC_GDMA_SUPPORT_ETM            (1)  // Support ETM submodule

 /*-------------------------- GPIO CAPS ---------------------------------------*/
-// ESP32-C6 has 1 GPIO peripheral
+// ESP32-H2 has 1 GPIO peripheral
 #define SOC_GPIO_PORT               (1U)
-#define SOC_GPIO_PIN_COUNT          (31)
+#define SOC_GPIO_PIN_COUNT          (28)

-// Target has the full LP IO subsystem
-// On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
-#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT    (1)
-// GPIO0~7 on ESP32C6 can support chip deep sleep wakeup
+// Target has no full LP IO subsystem, GPIO7~14 remain LP function (powered by VDD3V3_LP, and can be used as deep-sleep wakeup pins)
+
+// GPIO7~14 on ESP32H2 can support chip deep sleep wakeup
 #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)

 #define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
-#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
+#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT14)

-// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
-#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
+// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_0~6. GPIO_NUM_15~27)
+#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000000FFF807FULL

 // Support to configure sleep status
 #define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)