feat(spiram): Add spiram support on esp32c5

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -163,6 +163,10 @@ config SOC_MODEM_CLOCK_SUPPORTED
     bool
     default y
 
+config SOC_SPIRAM_SUPPORTED
+    bool
+    default y
+
 config SOC_XTAL_SUPPORT_40M
     bool
     default y

components/soc/esp32c5/include/soc/clk_tree_defs.h

@@ -502,7 +502,7 @@ typedef enum {
 /**
  * @brief MSPI digital controller clock source
  */
-typedef enum {  // TODO: [ESP32C5] IDF-8649
+typedef enum {
     MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
     MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
     MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL,           /*!< Select SPLL as the source clock */

components/soc/esp32c5/include/soc/io_mux_reg.h

@@ -137,6 +137,7 @@ extern "C" {
 #define SPI_CLK_GPIO_NUM             21
 #define SPI_D_GPIO_NUM               22
 #define SPI_Q_GPIO_NUM               17
+#define SPI_CS1_GPIO_NUM             15
 
 #define USB_INT_PHY0_DM_GPIO_NUM              13
 #define USB_INT_PHY0_DP_GPIO_NUM              14

components/soc/esp32c5/include/soc/soc_caps.h

@@ -77,6 +77,7 @@
 // #define SOC_DEEP_SLEEP_SUPPORTED        1  // TODO: [ESP32C5] IDF-8638
 #define SOC_MODEM_CLOCK_SUPPORTED       1
 // #define SOC_PM_SUPPORTED                1  // TODO: [ESP32C5] IDF-8643
+#define SOC_SPIRAM_SUPPORTED            1
 
 /*-------------------------- XTAL CAPS ---------------------------------------*/
 #define SOC_XTAL_SUPPORT_40M            1

components/soc/esp32c5/include/soc/spi1_mem_reg.h

@@ -11,10 +11,10 @@
 extern "C" {
 #endif
 
-/** SPI_MEM_CMD_REG register
+/** SPI_MEM_CMD_REG(i) register
  *  SPI1 memory command register
  */
-#define SPI_MEM_CMD_REG (DR_REG_SPI_MEM_BASE + 0x0)
+#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0)
 /** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0;
  *  The current status of SPI1 master FSM.
  */
@@ -155,10 +155,10 @@ extern "C" {
 #define SPI_MEM_FLASH_READ_V  0x00000001U
 #define SPI_MEM_FLASH_READ_S  31
 
-/** SPI_MEM_ADDR_REG register
+/** SPI_MEM_ADDR_REG(i) register
  *  SPI1 address register
  */
-#define SPI_MEM_ADDR_REG (DR_REG_SPI_MEM_BASE + 0x4)
+#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4)
 /** SPI_MEM_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
  *  In user mode, it is the memory address. other then the bit0-bit23 is the memory
  *  address, the bit24-bit31 are the byte length of a transfer.
@@ -168,10 +168,10 @@ extern "C" {
 #define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFFU
 #define SPI_MEM_USR_ADDR_VALUE_S  0
 
-/** SPI_MEM_CTRL_REG register
+/** SPI_MEM_CTRL_REG(i) register
  *  SPI1 control register.
  */
-#define SPI_MEM_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x8)
+#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8)
 /** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1;
  *  In the dummy phase of a MSPI read data transfer when accesses to flash, the signal
  *  level of SPI bus is output by the MSPI controller.
@@ -314,10 +314,10 @@ extern "C" {
 #define SPI_MEM_FREAD_QIO_V  0x00000001U
 #define SPI_MEM_FREAD_QIO_S  24
 
-/** SPI_MEM_CTRL1_REG register
+/** SPI_MEM_CTRL1_REG(i) register
  *  SPI1 control1 register.
  */
-#define SPI_MEM_CTRL1_REG (DR_REG_SPI_MEM_BASE + 0xc)
+#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xc)
 /** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
  *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
  *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
@@ -336,10 +336,10 @@ extern "C" {
 #define SPI_MEM_CS_HOLD_DLY_RES_V  0x000003FFU
 #define SPI_MEM_CS_HOLD_DLY_RES_S  2
 
-/** SPI_MEM_CTRL2_REG register
+/** SPI_MEM_CTRL2_REG(i) register
  *  SPI1 control2 register.
  */
-#define SPI_MEM_CTRL2_REG (DR_REG_SPI_MEM_BASE + 0x10)
+#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10)
 /** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0;
  *  The FSM will be reset.
  */
@@ -348,10 +348,10 @@ extern "C" {
 #define SPI_MEM_SYNC_RESET_V  0x00000001U
 #define SPI_MEM_SYNC_RESET_S  31
 
-/** SPI_MEM_CLOCK_REG register
+/** SPI_MEM_CLOCK_REG(i) register
  *  SPI1 clock division control register.
  */
-#define SPI_MEM_CLOCK_REG (DR_REG_SPI_MEM_BASE + 0x14)
+#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14)
 /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3;
  *  In the master mode it must be equal to spi_mem_clkcnt_N.
  */
@@ -382,10 +382,10 @@ extern "C" {
 #define SPI_MEM_CLK_EQU_SYSCLK_V  0x00000001U
 #define SPI_MEM_CLK_EQU_SYSCLK_S  31
 
-/** SPI_MEM_USER_REG register
+/** SPI_MEM_USER_REG(i) register
  *  SPI1 user register.
  */
-#define SPI_MEM_USER_REG (DR_REG_SPI_MEM_BASE + 0x18)
+#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18)
 /** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0;
  *  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
  */
@@ -480,10 +480,10 @@ extern "C" {
 #define SPI_MEM_USR_COMMAND_V  0x00000001U
 #define SPI_MEM_USR_COMMAND_S  31
 
-/** SPI_MEM_USER1_REG register
+/** SPI_MEM_USER1_REG(i) register
  *  SPI1 user1 register.
  */
-#define SPI_MEM_USER1_REG (DR_REG_SPI_MEM_BASE + 0x1c)
+#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1c)
 /** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7;
  *  The length in spi_mem_clk cycles of dummy phase. The register value shall be
  *  (cycle_num-1).
@@ -500,10 +500,10 @@ extern "C" {
 #define SPI_MEM_USR_ADDR_BITLEN_V  0x0000003FU
 #define SPI_MEM_USR_ADDR_BITLEN_S  26
 
-/** SPI_MEM_USER2_REG register
+/** SPI_MEM_USER2_REG(i) register
  *  SPI1 user2 register.
  */
-#define SPI_MEM_USER2_REG (DR_REG_SPI_MEM_BASE + 0x20)
+#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20)
 /** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
  *  The value of  command.
  */
@@ -519,10 +519,10 @@ extern "C" {
 #define SPI_MEM_USR_COMMAND_BITLEN_V  0x0000000FU
 #define SPI_MEM_USR_COMMAND_BITLEN_S  28
 
-/** SPI_MEM_MOSI_DLEN_REG register
+/** SPI_MEM_MOSI_DLEN_REG(i) register
  *  SPI1 send data bit length control register.
  */
-#define SPI_MEM_MOSI_DLEN_REG (DR_REG_SPI_MEM_BASE + 0x24)
+#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24)
 /** SPI_MEM_USR_MOSI_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of write-data. The register value shall be (bit_num-1).
  */
@@ -531,10 +531,10 @@ extern "C" {
 #define SPI_MEM_USR_MOSI_DBITLEN_V  0x000003FFU
 #define SPI_MEM_USR_MOSI_DBITLEN_S  0
 
-/** SPI_MEM_MISO_DLEN_REG register
+/** SPI_MEM_MISO_DLEN_REG(i) register
  *  SPI1 receive data bit length control register.
  */
-#define SPI_MEM_MISO_DLEN_REG (DR_REG_SPI_MEM_BASE + 0x28)
+#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28)
 /** SPI_MEM_USR_MISO_DBITLEN : R/W; bitpos: [9:0]; default: 0;
  *  The length in bits of  read-data. The register value shall be (bit_num-1).
  */
@@ -543,10 +543,10 @@ extern "C" {
 #define SPI_MEM_USR_MISO_DBITLEN_V  0x000003FFU
 #define SPI_MEM_USR_MISO_DBITLEN_S  0
 
-/** SPI_MEM_RD_STATUS_REG register
+/** SPI_MEM_RD_STATUS_REG(i) register
  *  SPI1 status register.
  */
-#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI_MEM_BASE + 0x2c)
+#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c)
 /** SPI_MEM_STATUS : R/W/SS; bitpos: [15:0]; default: 0;
  *  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
  */
@@ -576,10 +576,10 @@ extern "C" {
 #define SPI_MEM_WB_MODE_EN_V  0x00000001U
 #define SPI_MEM_WB_MODE_EN_S  27
 
-/** SPI_MEM_MISC_REG register
+/** SPI_MEM_MISC_REG(i) register
  *  SPI1 misc register
  */
-#define SPI_MEM_MISC_REG (DR_REG_SPI_MEM_BASE + 0x34)
+#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34)
 /** SPI_MEM_CS0_DIS : R/W; bitpos: [0]; default: 0;
  *  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
  *  device, such as flash, external RAM and so on.
@@ -611,10 +611,10 @@ extern "C" {
 #define SPI_MEM_CS_KEEP_ACTIVE_V  0x00000001U
 #define SPI_MEM_CS_KEEP_ACTIVE_S  10
 
-/** SPI_MEM_TX_CRC_REG register
+/** SPI_MEM_TX_CRC_REG(i) register
  *  SPI1 TX CRC data register.
  */
-#define SPI_MEM_TX_CRC_REG (DR_REG_SPI_MEM_BASE + 0x38)
+#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38)
 /** SPI_MEM_TX_CRC_DATA : RO; bitpos: [31:0]; default: 4294967295;
  *  For SPI1, the value of crc32.
  */
@@ -623,10 +623,10 @@ extern "C" {
 #define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFFU
 #define SPI_MEM_TX_CRC_DATA_S  0
 
-/** SPI_MEM_CACHE_FCTRL_REG register
+/** SPI_MEM_CACHE_FCTRL_REG(i) register
  *  SPI1 bit mode control register.
  */
-#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_MEM_BASE + 0x3c)
+#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c)
 /** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0;
  *  For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
  */
@@ -683,10 +683,10 @@ extern "C" {
 #define SPI_MEM_FADDR_QUAD_V  0x00000001U
 #define SPI_MEM_FADDR_QUAD_S  8
 
-/** SPI_MEM_W0_REG register
+/** SPI_MEM_W0_REG(i) register
  *  SPI1 memory data buffer0
  */
-#define SPI_MEM_W0_REG (DR_REG_SPI_MEM_BASE + 0x58)
+#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58)
 /** SPI_MEM_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -695,10 +695,10 @@ extern "C" {
 #define SPI_MEM_BUF0_V  0xFFFFFFFFU
 #define SPI_MEM_BUF0_S  0
 
-/** SPI_MEM_W1_REG register
+/** SPI_MEM_W1_REG(i) register
  *  SPI1 memory data buffer1
  */
-#define SPI_MEM_W1_REG (DR_REG_SPI_MEM_BASE + 0x5c)
+#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5c)
 /** SPI_MEM_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -707,10 +707,10 @@ extern "C" {
 #define SPI_MEM_BUF1_V  0xFFFFFFFFU
 #define SPI_MEM_BUF1_S  0
 
-/** SPI_MEM_W2_REG register
+/** SPI_MEM_W2_REG(i) register
  *  SPI1 memory data buffer2
  */
-#define SPI_MEM_W2_REG (DR_REG_SPI_MEM_BASE + 0x60)
+#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60)
 /** SPI_MEM_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -719,10 +719,10 @@ extern "C" {
 #define SPI_MEM_BUF2_V  0xFFFFFFFFU
 #define SPI_MEM_BUF2_S  0
 
-/** SPI_MEM_W3_REG register
+/** SPI_MEM_W3_REG(i) register
  *  SPI1 memory data buffer3
  */
-#define SPI_MEM_W3_REG (DR_REG_SPI_MEM_BASE + 0x64)
+#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64)
 /** SPI_MEM_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -731,10 +731,10 @@ extern "C" {
 #define SPI_MEM_BUF3_V  0xFFFFFFFFU
 #define SPI_MEM_BUF3_S  0
 
-/** SPI_MEM_W4_REG register
+/** SPI_MEM_W4_REG(i) register
  *  SPI1 memory data buffer4
  */
-#define SPI_MEM_W4_REG (DR_REG_SPI_MEM_BASE + 0x68)
+#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68)
 /** SPI_MEM_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -743,10 +743,10 @@ extern "C" {
 #define SPI_MEM_BUF4_V  0xFFFFFFFFU
 #define SPI_MEM_BUF4_S  0
 
-/** SPI_MEM_W5_REG register
+/** SPI_MEM_W5_REG(i) register
  *  SPI1 memory data buffer5
  */
-#define SPI_MEM_W5_REG (DR_REG_SPI_MEM_BASE + 0x6c)
+#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6c)
 /** SPI_MEM_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -755,10 +755,10 @@ extern "C" {
 #define SPI_MEM_BUF5_V  0xFFFFFFFFU
 #define SPI_MEM_BUF5_S  0
 
-/** SPI_MEM_W6_REG register
+/** SPI_MEM_W6_REG(i) register
  *  SPI1 memory data buffer6
  */
-#define SPI_MEM_W6_REG (DR_REG_SPI_MEM_BASE + 0x70)
+#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70)
 /** SPI_MEM_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -767,10 +767,10 @@ extern "C" {
 #define SPI_MEM_BUF6_V  0xFFFFFFFFU
 #define SPI_MEM_BUF6_S  0
 
-/** SPI_MEM_W7_REG register
+/** SPI_MEM_W7_REG(i) register
  *  SPI1 memory data buffer7
  */
-#define SPI_MEM_W7_REG (DR_REG_SPI_MEM_BASE + 0x74)
+#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74)
 /** SPI_MEM_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -779,10 +779,10 @@ extern "C" {
 #define SPI_MEM_BUF7_V  0xFFFFFFFFU
 #define SPI_MEM_BUF7_S  0
 
-/** SPI_MEM_W8_REG register
+/** SPI_MEM_W8_REG(i) register
  *  SPI1 memory data buffer8
  */
-#define SPI_MEM_W8_REG (DR_REG_SPI_MEM_BASE + 0x78)
+#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78)
 /** SPI_MEM_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -791,10 +791,10 @@ extern "C" {
 #define SPI_MEM_BUF8_V  0xFFFFFFFFU
 #define SPI_MEM_BUF8_S  0
 
-/** SPI_MEM_W9_REG register
+/** SPI_MEM_W9_REG(i) register
  *  SPI1 memory data buffer9
  */
-#define SPI_MEM_W9_REG (DR_REG_SPI_MEM_BASE + 0x7c)
+#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7c)
 /** SPI_MEM_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -803,10 +803,10 @@ extern "C" {
 #define SPI_MEM_BUF9_V  0xFFFFFFFFU
 #define SPI_MEM_BUF9_S  0
 
-/** SPI_MEM_W10_REG register
+/** SPI_MEM_W10_REG(i) register
  *  SPI1 memory data buffer10
  */
-#define SPI_MEM_W10_REG (DR_REG_SPI_MEM_BASE + 0x80)
+#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80)
 /** SPI_MEM_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -815,10 +815,10 @@ extern "C" {
 #define SPI_MEM_BUF10_V  0xFFFFFFFFU
 #define SPI_MEM_BUF10_S  0
 
-/** SPI_MEM_W11_REG register
+/** SPI_MEM_W11_REG(i) register
  *  SPI1 memory data buffer11
  */
-#define SPI_MEM_W11_REG (DR_REG_SPI_MEM_BASE + 0x84)
+#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84)
 /** SPI_MEM_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -827,10 +827,10 @@ extern "C" {
 #define SPI_MEM_BUF11_V  0xFFFFFFFFU
 #define SPI_MEM_BUF11_S  0
 
-/** SPI_MEM_W12_REG register
+/** SPI_MEM_W12_REG(i) register
  *  SPI1 memory data buffer12
  */
-#define SPI_MEM_W12_REG (DR_REG_SPI_MEM_BASE + 0x88)
+#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88)
 /** SPI_MEM_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -839,10 +839,10 @@ extern "C" {
 #define SPI_MEM_BUF12_V  0xFFFFFFFFU
 #define SPI_MEM_BUF12_S  0
 
-/** SPI_MEM_W13_REG register
+/** SPI_MEM_W13_REG(i) register
  *  SPI1 memory data buffer13
  */
-#define SPI_MEM_W13_REG (DR_REG_SPI_MEM_BASE + 0x8c)
+#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8c)
 /** SPI_MEM_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -851,10 +851,10 @@ extern "C" {
 #define SPI_MEM_BUF13_V  0xFFFFFFFFU
 #define SPI_MEM_BUF13_S  0
 
-/** SPI_MEM_W14_REG register
+/** SPI_MEM_W14_REG(i) register
  *  SPI1 memory data buffer14
  */
-#define SPI_MEM_W14_REG (DR_REG_SPI_MEM_BASE + 0x90)
+#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90)
 /** SPI_MEM_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -863,10 +863,10 @@ extern "C" {
 #define SPI_MEM_BUF14_V  0xFFFFFFFFU
 #define SPI_MEM_BUF14_S  0
 
-/** SPI_MEM_W15_REG register
+/** SPI_MEM_W15_REG(i) register
  *  SPI1 memory data buffer15
  */
-#define SPI_MEM_W15_REG (DR_REG_SPI_MEM_BASE + 0x94)
+#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94)
 /** SPI_MEM_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
  *  data buffer
  */
@@ -875,10 +875,10 @@ extern "C" {
 #define SPI_MEM_BUF15_V  0xFFFFFFFFU
 #define SPI_MEM_BUF15_S  0
 
-/** SPI_MEM_FLASH_WAITI_CTRL_REG register
+/** SPI_MEM_FLASH_WAITI_CTRL_REG(i) register
  *  SPI1 wait idle control register
  */
-#define SPI_MEM_FLASH_WAITI_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x98)
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98)
 /** SPI_MEM_WAITI_EN : R/W; bitpos: [0]; default: 1;
  *  1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto
  *  Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto
@@ -934,10 +934,10 @@ extern "C" {
 #define SPI_MEM_WAITI_CMD_V  0x0000FFFFU
 #define SPI_MEM_WAITI_CMD_S  16
 
-/** SPI_MEM_FLASH_SUS_CTRL_REG register
+/** SPI_MEM_FLASH_SUS_CTRL_REG(i) register
  *  SPI1 flash suspend control register
  */
-#define SPI_MEM_FLASH_SUS_CTRL_REG (DR_REG_SPI_MEM_BASE + 0x9c)
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x9c)
 /** SPI_MEM_FLASH_PER : R/W/SC; bitpos: [0]; default: 0;
  *  program erase resume bit, program erase suspend operation will be triggered when
  *  the bit is set. The bit will be cleared once the operation done.1: enable 0:
@@ -1032,10 +1032,10 @@ extern "C" {
 #define SPI_MEM_SUS_TIMEOUT_CNT_V  0x0000007FU
 #define SPI_MEM_SUS_TIMEOUT_CNT_S  25
 
-/** SPI_MEM_FLASH_SUS_CMD_REG register
+/** SPI_MEM_FLASH_SUS_CMD_REG(i) register
  *  SPI1 flash suspend command register
  */
-#define SPI_MEM_FLASH_SUS_CMD_REG (DR_REG_SPI_MEM_BASE + 0xa0)
+#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0xa0)
 /** SPI_MEM_FLASH_PES_COMMAND : R/W; bitpos: [15:0]; default: 30069;
  *  Program/Erase suspend command.
  */
@@ -1052,10 +1052,10 @@ extern "C" {
 #define SPI_MEM_WAIT_PESR_COMMAND_V  0x0000FFFFU
 #define SPI_MEM_WAIT_PESR_COMMAND_S  16
 
-/** SPI_MEM_SUS_STATUS_REG register
+/** SPI_MEM_SUS_STATUS_REG(i) register
  *  SPI1 flash suspend status register
  */
-#define SPI_MEM_SUS_STATUS_REG (DR_REG_SPI_MEM_BASE + 0xa4)
+#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xa4)
 /** SPI_MEM_FLASH_SUS : R/W/SS/SC; bitpos: [0]; default: 0;
  *  The status of flash suspend, only used in SPI1.
  */
@@ -1141,10 +1141,10 @@ extern "C" {
 #define SPI_MEM_FLASH_PER_COMMAND_V  0x0000FFFFU
 #define SPI_MEM_FLASH_PER_COMMAND_S  16
 
-/** SPI_MEM_FLASH_WAITI_CTRL1_REG register
+/** SPI_MEM_FLASH_WAITI_CTRL1_REG(i) register
  *  SPI1 wait idle control register
  */
-#define SPI_MEM_FLASH_WAITI_CTRL1_REG (DR_REG_SPI_MEM_BASE + 0xac)
+#define SPI_MEM_FLASH_WAITI_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xac)
 /** SPI_MEM_WAITI_IDLE_DELAY_TIME : R/W; bitpos: [9:0]; default: 0;
  *  SPI1 wait idle gap time configuration. SPI1 slv fsm will count during SPI1 IDLE.
  */
@@ -1160,10 +1160,10 @@ extern "C" {
 #define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_V  0x00000001U
 #define SPI_MEM_WAITI_IDLE_DELAY_TIME_EN_S  10
 
-/** SPI_MEM_INT_ENA_REG register
+/** SPI_MEM_INT_ENA_REG(i) register
  *  SPI1 interrupt enable register
  */
-#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_MEM_BASE + 0xc0)
+#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xc0)
 /** SPI_MEM_PER_END_INT_ENA : R/W; bitpos: [0]; default: 0;
  *  The enable bit for SPI_MEM_PER_END_INT interrupt.
  */
@@ -1207,10 +1207,10 @@ extern "C" {
 #define SPI_MEM_BROWN_OUT_INT_ENA_V  0x00000001U
 #define SPI_MEM_BROWN_OUT_INT_ENA_S  10
 
-/** SPI_MEM_INT_CLR_REG register
+/** SPI_MEM_INT_CLR_REG(i) register
  *  SPI1 interrupt clear register
  */
-#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_MEM_BASE + 0xc4)
+#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xc4)
 /** SPI_MEM_PER_END_INT_CLR : WT; bitpos: [0]; default: 0;
  *  The clear bit for SPI_MEM_PER_END_INT interrupt.
  */
@@ -1254,10 +1254,10 @@ extern "C" {
 #define SPI_MEM_BROWN_OUT_INT_CLR_V  0x00000001U
 #define SPI_MEM_BROWN_OUT_INT_CLR_S  10
 
-/** SPI_MEM_INT_RAW_REG register
+/** SPI_MEM_INT_RAW_REG(i) register
  *  SPI1 interrupt raw register
  */
-#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_MEM_BASE + 0xc8)
+#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xc8)
 /** SPI_MEM_PER_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
  *  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
  *  command (0x7A) is sent and flash is resumed successfully. 0: Others.
@@ -1310,10 +1310,10 @@ extern "C" {
 #define SPI_MEM_BROWN_OUT_INT_RAW_V  0x00000001U
 #define SPI_MEM_BROWN_OUT_INT_RAW_S  10
 
-/** SPI_MEM_INT_ST_REG register
+/** SPI_MEM_INT_ST_REG(i) register
  *  SPI1 interrupt status register
  */
-#define SPI_MEM_INT_ST_REG (DR_REG_SPI_MEM_BASE + 0xcc)
+#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xcc)
 /** SPI_MEM_PER_END_INT_ST : RO; bitpos: [0]; default: 0;
  *  The status bit for SPI_MEM_PER_END_INT interrupt.
  */
@@ -1357,10 +1357,10 @@ extern "C" {
 #define SPI_MEM_BROWN_OUT_INT_ST_V  0x00000001U
 #define SPI_MEM_BROWN_OUT_INT_ST_S  10
 
-/** SPI_MEM_DDR_REG register
+/** SPI_MEM_DDR_REG(i) register
  *  SPI1 DDR control register
  */
-#define SPI_MEM_DDR_REG (DR_REG_SPI_MEM_BASE + 0xd4)
+#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4)
 /** SPI_MEM_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0;
  *  1: in ddr mode,  0 in sdr mode
  */
@@ -1466,10 +1466,10 @@ extern "C" {
 #define SPI_MEM_FMEM_HYPERBUS_CA_V  0x00000001U
 #define SPI_MEM_FMEM_HYPERBUS_CA_S  30
 
-/** SPI_MEM_TIMING_CALI_REG register
+/** SPI_MEM_TIMING_CALI_REG(i) register
  *  SPI1 timing control register
  */
-#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_MEM_BASE + 0x180)
+#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x180)
 /** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0;
  *  The bit is used to enable timing auto-calibration for all reading operations.
  */
@@ -1485,10 +1485,10 @@ extern "C" {
 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x00000007U
 #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
 
-/** SPI_MEM_CLOCK_GATE_REG register
+/** SPI_MEM_CLOCK_GATE_REG(i) register
  *  SPI1 clk_gate register
  */
-#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_MEM_BASE + 0x200)
+#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x200)
 /** SPI_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Register clock gate enable signal. 1: Enable. 0: Disable.
  */
@@ -1497,10 +1497,10 @@ extern "C" {
 #define SPI_MEM_CLK_EN_V  0x00000001U
 #define SPI_MEM_CLK_EN_S  0
 
-/** SPI_MEM_DATE_REG register
+/** SPI_MEM_DATE_REG(i) register
  *  Version control register
  */
-#define SPI_MEM_DATE_REG (DR_REG_SPI_MEM_BASE + 0x3fc)
+#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc)
 /** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400;
  *  Version control register
  */