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esp32c3: format and clean up interrupt and os port code
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@@ -1,4 +1,4 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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@@ -12,8 +12,7 @@
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef __ESP_INTR_ALLOC_H__
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#define __ESP_INTR_ALLOC_H__
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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@@ -37,24 +36,24 @@ extern "C" {
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*/
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//Keep the LEVELx values as they are here; they match up with (1<<level)
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#define ESP_INTR_FLAG_LEVEL1 (1<<1) ///< Accept a Level 1 interrupt vector (lowest priority)
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#define ESP_INTR_FLAG_LEVEL2 (1<<2) ///< Accept a Level 2 interrupt vector
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#define ESP_INTR_FLAG_LEVEL3 (1<<3) ///< Accept a Level 3 interrupt vector
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#define ESP_INTR_FLAG_LEVEL4 (1<<4) ///< Accept a Level 4 interrupt vector
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#define ESP_INTR_FLAG_LEVEL5 (1<<5) ///< Accept a Level 5 interrupt vector
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#define ESP_INTR_FLAG_LEVEL6 (1<<6) ///< Accept a Level 6 interrupt vector
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#define ESP_INTR_FLAG_NMI (1<<7) ///< Accept a Level 7 interrupt vector (highest priority)
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#define ESP_INTR_FLAG_SHARED (1<<8) ///< Interrupt can be shared between ISRs
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#define ESP_INTR_FLAG_EDGE (1<<9) ///< Edge-triggered interrupt
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#define ESP_INTR_FLAG_IRAM (1<<10) ///< ISR can be called if cache is disabled
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#define ESP_INTR_FLAG_INTRDISABLED (1<<11) ///< Return with this interrupt disabled
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#define ESP_INTR_FLAG_LEVEL1 (1<<1) ///< Accept a Level 1 interrupt vector (lowest priority)
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#define ESP_INTR_FLAG_LEVEL2 (1<<2) ///< Accept a Level 2 interrupt vector
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#define ESP_INTR_FLAG_LEVEL3 (1<<3) ///< Accept a Level 3 interrupt vector
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#define ESP_INTR_FLAG_LEVEL4 (1<<4) ///< Accept a Level 4 interrupt vector
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#define ESP_INTR_FLAG_LEVEL5 (1<<5) ///< Accept a Level 5 interrupt vector
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#define ESP_INTR_FLAG_LEVEL6 (1<<6) ///< Accept a Level 6 interrupt vector
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#define ESP_INTR_FLAG_NMI (1<<7) ///< Accept a Level 7 interrupt vector (highest priority)
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#define ESP_INTR_FLAG_SHARED (1<<8) ///< Interrupt can be shared between ISRs
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#define ESP_INTR_FLAG_EDGE (1<<9) ///< Edge-triggered interrupt
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#define ESP_INTR_FLAG_IRAM (1<<10) ///< ISR can be called if cache is disabled
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#define ESP_INTR_FLAG_INTRDISABLED (1<<11) ///< Return with this interrupt disabled
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#define ESP_INTR_FLAG_LOWMED (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) ///< Low and medium prio interrupts. These can be handled in C.
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#define ESP_INTR_FLAG_HIGH (ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6|ESP_INTR_FLAG_NMI) ///< High level interrupts. Need to be handled in assembly.
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#define ESP_INTR_FLAG_LOWMED (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) ///< Low and medium prio interrupts. These can be handled in C.
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#define ESP_INTR_FLAG_HIGH (ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6|ESP_INTR_FLAG_NMI) ///< High level interrupts. Need to be handled in assembly.
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#define ESP_INTR_FLAG_LEVELMASK (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
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ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
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ESP_INTR_FLAG_NMI) ///< Mask for all level flags
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#define ESP_INTR_FLAG_LEVELMASK (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
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ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
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ESP_INTR_FLAG_NMI) ///< Mask for all level flags
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/** @addtogroup Intr_Alloc_Pseudo_Src
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@@ -67,18 +66,18 @@ extern "C" {
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* sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
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* pass these pseudo-sources to the functions.
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*/
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#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 ///< Platform timer 0 interrupt source
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#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 ///< Platform timer 1 interrupt source
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#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 ///< Platform timer 2 interrupt source
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#define ETS_INTERNAL_SW0_INTR_SOURCE -4 ///< Software int source 1
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#define ETS_INTERNAL_SW1_INTR_SOURCE -5 ///< Software int source 2
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#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 ///< Int source for profiling
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#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 ///< Platform timer 0 interrupt source
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#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 ///< Platform timer 1 interrupt source
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#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 ///< Platform timer 2 interrupt source
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#define ETS_INTERNAL_SW0_INTR_SOURCE -4 ///< Software int source 1
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#define ETS_INTERNAL_SW1_INTR_SOURCE -5 ///< Software int source 2
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#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 ///< Int source for profiling
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/**@}*/
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/** Provides SystemView with positive IRQ IDs, otherwise scheduler events are not shown properly
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*/
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#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
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#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
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/** Enable interrupt by interrupt number */
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#define ESP_INTR_ENABLE(inum) esp_intr_enable_source(inum)
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@@ -93,7 +92,7 @@ typedef void (*intr_handler_t)(void *arg);
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typedef struct intr_handle_data_t intr_handle_data_t;
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/** Handle to an interrupt handler */
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typedef intr_handle_data_t* intr_handle_t ;
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typedef intr_handle_data_t *intr_handle_t ;
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/**
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* @brief Mark an interrupt as a shared interrupt
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@@ -306,11 +305,18 @@ void esp_intr_enable_source(int inum);
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*/
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void esp_intr_disable_source(int inum);
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/**
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* @brief Get the lowest interrupt level from the flags
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* @param flags The same flags that pass to `esp_intr_alloc_intrstatus` API
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*/
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static inline int esp_intr_flags_to_level(int flags)
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{
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return __builtin_ffs((flags & ESP_INTR_FLAG_LEVELMASK) >> 1) + 1;
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}
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/**@}*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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