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Merge branch 'feature/adc_driver_ng' into 'master'

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ADC Driver NG

Closes IDF-4560, IDF-3908, IDF-4225, IDF-2482, IDF-4111, IDF-3610, IDF-4058, IDF-3801, IDF-3636, IDF-2537, IDF-4310, IDF-5150, IDF-5151, and IDF-4979

See merge request espressif/esp-idf!17960
This commit is contained in:
Armando (Dou Yiwen)
2022-07-19 21:28:31 +08:00
parent b59309852a 5b523a3313
commit 9f6f61345b
185 changed files with 7783 additions and 6462 deletions
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610
components/hal/esp32c2/include/hal/adc_ll.h
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@@ -15,6 +15,7 @@
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#include "hal/regi2c_ctrl.h"
@@ -24,9 +25,9 @@
extern "C" {
#endif
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_CLKM_DIV_NUM_DEFAULT 15
#define ADC_LL_CLKM_DIV_B_DEFAULT 1
#define ADC_LL_CLKM_DIV_A_DEFAULT 0
#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
@@ -47,43 +48,8 @@ typedef enum {
typedef enum {
ADC_LL_CTRL_DIG = 0, ///< For ADC1. Select DIG controller.
ADC_LL_CTRL_ARB = 1, ///< For ADC2. The controller is selected by the arbiter.
} adc_ll_controller_t;
/**
* @brief ADC digital controller (DMA mode) work mode.
*
* @note The conversion mode affects the sampling frequency:
* ESP32C2 only support ALTER_UNIT mode
* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
*/
typedef enum {
ADC_LL_DIGI_CONV_ALTER_UNIT = 0, // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
} adc_ll_digi_convert_mode_t;
//These values should be set according to the HW
typedef enum {
ADC_LL_INTR_THRES1_LOW = BIT(26),
ADC_LL_INTR_THRES0_LOW = BIT(27),
ADC_LL_INTR_THRES1_HIGH = BIT(28),
ADC_LL_INTR_THRES0_HIGH = BIT(29),
ADC_LL_INTR_ADC2_DONE = BIT(30),
ADC_LL_INTR_ADC1_DONE = BIT(31),
} adc_ll_intr_t;
FLAG_ATTR(adc_ll_intr_t)
typedef struct {
union {
struct {
uint8_t atten: 2;
uint8_t channel: 3;
uint8_t unit: 1;
uint8_t reserved: 2;
};
uint8_t val;
};
} __attribute__((packed)) adc_ll_digi_pattern_table_t;
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
@@ -97,13 +63,12 @@ typedef struct {
*/
static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
{
abort(); //TODO IDF-3908
// // Internal FSM reset wait time
// HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait);
// // Internal FSM start wait time
// HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait);
// // Internal FSM standby wait time
// HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait);
// Internal FSM reset wait time
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_rstb_wait, rst_wait);
// Internal FSM start wait time
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_xpd_wait, start_wait);
// Internal FSM standby wait time
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_fsm_wait, saradc_saradc_standby_wait, standby_wait);
}
/**
@@ -115,10 +80,9 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
*/
static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
{
abort(); //TODO IDF-3908
// /* Should be called before writing I2C registers. */
// SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
/* Should be called before writing I2C registers. */
SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
}
/**
@@ -129,105 +93,8 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
*/
static inline void adc_ll_digi_set_clk_div(uint32_t div)
{
abort(); //TODO IDF-3908
// /* ADC clock devided from digital controller clock clk */
// HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div);
}
/**
* Set adc max conversion number for digital controller.
* If the number of ADC conversion is equal to the maximum, the conversion is stopped.
*
* @param meas_num Max conversion number. Range: 0 ~ 255.
*/
static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
{
abort(); //TODO IDF-3908
// HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num);
}
/**
* Enable max conversion number detection for digital controller.
* If the number of ADC conversion is equal to the maximum, the conversion is stopped.
*/
static inline void adc_ll_digi_convert_limit_enable(void)
{
abort(); //TODO IDF-3908
// APB_SARADC.ctrl2.meas_num_limit = 1;
}
/**
* Disable max conversion number detection for digital controller.
* If the number of ADC conversion is equal to the maximum, the conversion is stopped.
*/
static inline void adc_ll_digi_convert_limit_disable(void)
{
abort(); //TODO IDF-3908
// APB_SARADC.ctrl2.meas_num_limit = 0;
}
/**
* Set adc conversion mode for digital controller.
*
* @note ESP32-C2 only support ADC1 single mode.
*
* @param mode Conversion mode select.
*/
static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
{
//ESP32-C2 only supports ADC_CONV_ALTER_UNIT mode
}
/**
* Set pattern table length for digital controller.
* The pattern table that defines the conversion rules for each SAR ADC. Each table has 8 items, in which channel selection,
* and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
* pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself.
*
* @param adc_n ADC unit.
* @param patt_len Items range: 1 ~ 8.
*/
static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
{
abort(); //TODO IDF-3908
// APB_SARADC.ctrl.sar_patt_len = patt_len - 1;
}
/**
* Set pattern table for digital controller.
* The pattern table that defines the conversion rules for each SAR ADC. Each table has 8 items, in which channel selection,
* resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
* pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself.
*
* @param adc_n ADC unit.
* @param pattern_index Items index. Range: 0 ~ 7.
* @param pattern Stored conversion rules.
*/
static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
{
abort(); //TODO IDF-3908
// uint32_t tab;
// uint8_t index = pattern_index / 4;
// uint8_t offset = (pattern_index % 4) * 6;
// adc_ll_digi_pattern_table_t pattern = {0};
// pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5);
// tab = APB_SARADC.sar_patt_tab[index].sar_patt_tab1; // Read old register value
// tab &= (~(0xFC0000 >> offset)); // Clear old data
// tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data
// APB_SARADC.sar_patt_tab[index].sar_patt_tab1 = tab; // Write back
}
/**
* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
*
* @param adc_n ADC unit.
*/
static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
{
abort(); //TODO IDF-3908
// APB_SARADC.ctrl.sar_patt_p_clear = 1;
// APB_SARADC.ctrl.sar_patt_p_clear = 0;
/* ADC clock devided from digital controller clock clk */
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl, saradc_saradc_sar_clk_div, div);
}
/**
@@ -238,8 +105,7 @@ static inline void adc_ll_digi_clear_pattern_table(adc_unit_t adc_n)
*/
static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
{
abort(); //TODO IDF-3908
// APB_SARADC.ctrl.wait_arb_cycle = cycle;
APB_SARADC.saradc_ctrl.saradc_saradc_wait_arb_cycle = cycle;
}
/**
@@ -250,43 +116,11 @@ static inline void adc_ll_digi_set_arbiter_stable_cycle(uint32_t cycle)
*/
static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
{
abort(); //TODO IDF-3908
// if (adc_n == ADC_UNIT_1) {
// APB_SARADC.ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
// } else { // adc_n == ADC_UNIT_2
// APB_SARADC.ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
// }
}
/**
* Set the interval clock cycle for the digital controller to trigger the measurement.
* Expression: `trigger_meas_freq` = `controller_clk` / 2 / interval.
*
* @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
* @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
*/
static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
{
abort(); //TODO IDF-3908
// APB_SARADC.ctrl2.timer_target = cycle;
}
/**
* Enable digital controller timer to trigger the measurement.
*/
static inline void adc_ll_digi_trigger_enable(void)
{
abort(); //TODO IDF-3908
// APB_SARADC.ctrl2.timer_en = 1;
}
/**
* Disable digital controller timer to trigger the measurement.
*/
static inline void adc_ll_digi_trigger_disable(void)
{
abort(); //TODO IDF-3908
// APB_SARADC.ctrl2.timer_en = 0;
if (adc_n == ADC_UNIT_1) {
APB_SARADC.saradc_ctrl2.saradc_saradc_sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_UNIT_2
APB_SARADC.saradc_ctrl2.saradc_saradc_sar2_inv = inv_en; // Enable / Disable ADC data invert
}
}
/**
@@ -300,9 +134,9 @@ static inline void adc_ll_digi_trigger_disable(void)
static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
{
abort(); //TODO IDF-3908
// HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num);
// APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b;
// APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_apb_adc_clkm_conf, saradc_reg_clkm_div_num, div_num);
APB_SARADC.saradc_apb_adc_clkm_conf.saradc_reg_clkm_div_b = div_b;
APB_SARADC.saradc_apb_adc_clkm_conf.saradc_reg_clkm_div_a = div_a;
}
/**
@@ -312,13 +146,12 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
*/
static inline void adc_ll_digi_clk_sel(bool use_apll)
{
abort(); //TODO IDF-3908
// if (use_apll) {
// APB_SARADC.apb_adc_clkm_conf.clk_sel = 1; // APLL clock
// } else {
// APB_SARADC.apb_adc_clkm_conf.clk_sel = 2; // APB clock
// }
// APB_SARADC.ctrl.sar_clk_gated = 1;
if (use_apll) {
APB_SARADC.saradc_apb_adc_clkm_conf.saradc_reg_clk_sel = 1; // APLL clock
} else {
APB_SARADC.saradc_apb_adc_clkm_conf.saradc_reg_clk_sel = 2; // APB clock
}
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
}
/**
@@ -326,8 +159,7 @@ static inline void adc_ll_digi_clk_sel(bool use_apll)
*/
static inline void adc_ll_digi_controller_clk_disable(void)
{
abort(); //TODO IDF-3908
// APB_SARADC.ctrl.sar_clk_gated = 0;
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0;
}
/**
@@ -337,8 +169,7 @@ static inline void adc_ll_digi_controller_clk_disable(void)
*/
static inline void adc_ll_digi_filter_reset(adc_unit_t adc_n)
{
abort(); //TODO IDF-3908
// APB_SARADC.filter_ctrl0.filter_reset = 1;
APB_SARADC.saradc_filter_ctrl0.saradc_filter_reset = 1;
}
/**
@@ -350,14 +181,7 @@ static inline void adc_ll_digi_filter_reset(adc_unit_t adc_n)
*/
static inline void adc_ll_digi_filter_set_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter)
{
abort(); //TODO IDF-3908
// if (idx == ADC_DIGI_FILTER_IDX0) {
// APB_SARADC.filter_ctrl0.filter_channel0 = (filter->adc_unit << 3) | (filter->channel & 0x7);
// APB_SARADC.filter_ctrl1.filter_factor0 = filter->mode;
// } else if (idx == ADC_DIGI_FILTER_IDX1) {
// APB_SARADC.filter_ctrl0.filter_channel1 = (filter->adc_unit << 3) | (filter->channel & 0x7);
// APB_SARADC.filter_ctrl1.filter_factor1 = filter->mode;
// }
abort();
}
/**
@@ -368,16 +192,7 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_filter_idx_t idx, adc_
*/
static inline void adc_ll_digi_filter_get_factor(adc_digi_filter_idx_t idx, adc_digi_filter_t *filter)
{
abort(); //TODO IDF-3908
// if (idx == ADC_DIGI_FILTER_IDX0) {
// filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel0 >> 3) & 0x1;
// filter->channel = APB_SARADC.filter_ctrl0.filter_channel0 & 0x7;
// filter->mode = APB_SARADC.filter_ctrl1.filter_factor0;
// } else if (idx == ADC_DIGI_FILTER_IDX1) {
// filter->adc_unit = (APB_SARADC.filter_ctrl0.filter_channel1 >> 3) & 0x1;
// filter->channel = APB_SARADC.filter_ctrl0.filter_channel1 & 0x7;
// filter->mode = APB_SARADC.filter_ctrl1.filter_factor1;
// }
abort();
}
/**
@@ -389,14 +204,7 @@ static inline void adc_ll_digi_filter_get_factor(adc_digi_filter_idx_t idx, adc_
*/
static inline void adc_ll_digi_filter_disable(adc_digi_filter_idx_t idx)
{
abort(); //TODO IDF-3908
// if (idx == ADC_DIGI_FILTER_IDX0) {
// APB_SARADC.filter_ctrl0.filter_channel0 = 0xF;
// APB_SARADC.filter_ctrl1.filter_factor0 = 0;
// } else if (idx == ADC_DIGI_FILTER_IDX1) {
// APB_SARADC.filter_ctrl0.filter_channel1 = 0xF;
// APB_SARADC.filter_ctrl1.filter_factor1 = 0;
// }
abort();
}
/**
@@ -409,16 +217,15 @@ static inline void adc_ll_digi_filter_disable(adc_digi_filter_idx_t idx)
*/
static inline void adc_ll_digi_monitor_set_mode(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *cfg)
{
abort(); //TODO IDF-3908
// if (idx == ADC_DIGI_MONITOR_IDX0) {
// APB_SARADC.thres0_ctrl.thres0_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7);
// APB_SARADC.thres0_ctrl.thres0_high = cfg->h_threshold;
// APB_SARADC.thres0_ctrl.thres0_low = cfg->l_threshold;
// } else { // ADC_DIGI_MONITOR_IDX1
// APB_SARADC.thres1_ctrl.thres1_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7);
// APB_SARADC.thres1_ctrl.thres1_high = cfg->h_threshold;
// APB_SARADC.thres1_ctrl.thres1_low = cfg->l_threshold;
// }
if (idx == ADC_DIGI_MONITOR_IDX0) {
APB_SARADC.saradc_thres0_ctrl.saradc_thres0_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7);
APB_SARADC.saradc_thres0_ctrl.saradc_thres0_high = cfg->h_threshold;
APB_SARADC.saradc_thres0_ctrl.saradc_thres0_low = cfg->l_threshold;
} else { // ADC_DIGI_MONITOR_IDX1
APB_SARADC.saradc_thres1_ctrl.saradc_thres1_channel = (cfg->adc_unit << 3) | (cfg->channel & 0x7);
APB_SARADC.saradc_thres1_ctrl.saradc_thres1_high = cfg->h_threshold;
APB_SARADC.saradc_thres1_ctrl.saradc_thres1_low = cfg->l_threshold;
}
}
/**
@@ -429,42 +236,11 @@ static inline void adc_ll_digi_monitor_set_mode(adc_digi_monitor_idx_t idx, adc_
*/
static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx)
{
abort(); //TODO IDF-3908
// if (idx == ADC_DIGI_MONITOR_IDX0) {
// APB_SARADC.thres0_ctrl.thres0_channel = 0xF;
// } else { // ADC_DIGI_MONITOR_IDX1
// APB_SARADC.thres1_ctrl.thres1_channel = 0xF;
// }
}
/**
* Set DMA eof num of adc digital controller.
* If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated.
*
* @param num eof num of DMA.
*/
static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
{
abort(); //TODO IDF-3908
// HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num);
}
/**
* Enable output data to DMA from adc digital controller.
*/
static inline void adc_ll_digi_dma_enable(void)
{
abort(); //TODO IDF-3908
// APB_SARADC.dma_conf.apb_adc_trans = 1;
}
/**
* Disable output data to DMA from adc digital controller.
*/
static inline void adc_ll_digi_dma_disable(void)
{
abort(); //TODO IDF-3908
// APB_SARADC.dma_conf.apb_adc_trans = 0;
if (idx == ADC_DIGI_MONITOR_IDX0) {
APB_SARADC.saradc_thres0_ctrl.saradc_thres0_channel = 0xF;
} else { // ADC_DIGI_MONITOR_IDX1
APB_SARADC.saradc_thres1_ctrl.saradc_thres1_channel = 0xF;
}
}
/**
@@ -472,9 +248,8 @@ static inline void adc_ll_digi_dma_disable(void)
*/
static inline void adc_ll_digi_reset(void)
{
abort(); //TODO IDF-3908
// APB_SARADC.dma_conf.apb_adc_reset_fsm = 1;
// APB_SARADC.dma_conf.apb_adc_reset_fsm = 0;
APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 1;
APB_SARADC.saradc_dma_conf.saradc_apb_adc_reset_fsm = 0;
}
/*---------------------------------------------------------------
@@ -488,9 +263,8 @@ static inline void adc_ll_digi_reset(void)
*/
static inline void adc_ll_pwdet_set_cct(uint32_t cct)
{
abort(); //TODO IDF-3908
// /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
// RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct;
/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct;
}
/**
@@ -501,34 +275,8 @@ static inline void adc_ll_pwdet_set_cct(uint32_t cct)
*/
static inline uint32_t adc_ll_pwdet_get_cct(void)
{
abort(); //TODO IDF-3908
// /* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
// return RTCCNTL.sensor_ctrl.sar2_pwdet_cct;
}
/**
* Analyze whether the obtained raw data is correct.
* ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data.
*
* @param adc_n ADC unit.
* @param raw_data ADC raw data input (convert value).
* @return
* - 0: The data is correct to use.
* - -1: The data is invalid.
*/
static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_unit_t adc_n, int raw_data)
{
abort(); //TODO IDF-3908
// if (adc_n == ADC_UNIT_1) {
// return ADC_RTC_DATA_OK;
// }
// //The raw data API returns value without channel information. Read value directly from the register
// if (((APB_SARADC.apb_saradc2_data_status.adc2_data >> 13) & 0xF) > 9) {
// return ADC_RTC_DATA_FAIL;
// }
// return ADC_RTC_DATA_OK;
/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
return RTCCNTL.sensor_ctrl.sar2_pwdet_cct;
}
/*---------------------------------------------------------------
@@ -541,19 +289,18 @@ static inline adc_ll_rtc_raw_data_t adc_ll_analysis_raw_data(adc_unit_t adc_n, i
*/
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
{
abort(); //TODO IDF-3908
// /* Bit1 0:Fsm 1: SW mode
// Bit0 0:SW mode power down 1: SW mode power on */
// if (manage == ADC_POWER_SW_ON) {
// APB_SARADC.ctrl.sar_clk_gated = 1;
// APB_SARADC.ctrl.xpd_sar_force = 3;
// } else if (manage == ADC_POWER_BY_FSM) {
// APB_SARADC.ctrl.sar_clk_gated = 1;
// APB_SARADC.ctrl.xpd_sar_force = 0;
// } else if (manage == ADC_POWER_SW_OFF) {
// APB_SARADC.ctrl.sar_clk_gated = 0;
// APB_SARADC.ctrl.xpd_sar_force = 2;
// }
/* Bit1 0:Fsm 1: SW mode
Bit0 0:SW mode power down 1: SW mode power on */
if (manage == ADC_POWER_SW_ON) {
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3;
} else if (manage == ADC_POWER_BY_FSM) {
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0;
} else if (manage == ADC_POWER_SW_OFF) {
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0;
APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2;
}
}
static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
@@ -561,75 +308,6 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
//Not used on ESP32-C2
}
/**
* Set ADC2 module arbiter work mode.
* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
* the low priority controller will read the invalid ADC data, and the validity of the data can be judged by the flag bit in the data.
*
* @note Only ADC2 support arbiter.
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
*
* @param mode Refer to `adc_arbiter_mode_t`.
*/
static inline void adc_ll_set_arbiter_work_mode(adc_arbiter_mode_t mode)
{
abort(); //TODO IDF-3908
// if (mode == ADC_ARB_MODE_FIX) {
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 1;
// } else if (mode == ADC_ARB_MODE_LOOP) {
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 0;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_fix_priority = 0;
// } else {
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_grant_force = 1; // Shield arbiter.
// }
}
/**
* Set ADC2 module controller priority in arbiter.
* The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
* the low priority controller will read the invalid ADC data, and the validity of the data can be judged by the flag bit in the data.
*
* @note Only ADC2 support arbiter.
* @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
* @note Default priority: Wi-Fi(2) > RTC(1) > Digital(0);
*
* @param pri_rtc RTC controller priority. Range: 0 ~ 2.
* @param pri_dig Digital controller priority. Range: 0 ~ 2.
* @param pri_pwdet Wi-Fi controller priority. Range: 0 ~ 2.
*/
static inline void adc_ll_set_arbiter_priority(uint8_t pri_rtc, uint8_t pri_dig, uint8_t pri_pwdet)
{
abort(); //TODO IDF-3908
// if (pri_rtc != pri_dig && pri_rtc != pri_pwdet && pri_dig != pri_pwdet) {
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_priority = pri_rtc;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_priority = pri_dig;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_priority = pri_pwdet;
// }
// /* Should select highest priority controller. */
// if (pri_rtc > pri_dig) {
// if (pri_rtc > pri_pwdet) {
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 1;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0;
// } else {
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1;
// }
// } else {
// if (pri_dig > pri_pwdet) {
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 1;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 0;
// } else {
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_apb_force = 0;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_rtc_force = 0;
// APB_SARADC.apb_adc_arb_ctrl.adc_arb_wifi_force = 1;
// }
// }
}
/* ADC calibration code. */
/**
* @brief Set common calibration configuration. Should be shared with other parts (PWDET).
@@ -708,78 +386,21 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
// }
}
/* Temp code end. */
/**
* Output ADCn inter reference voltage to ADC2 channels.
*
* This function routes the internal reference voltage of ADCn to one of
* ADC1's channels. This reference voltage can then be manually measured
* for calibration purposes.
*
* @param[in] adc ADC unit select
* @param[in] channel ADC1 channel number
* @param[in] en Enable/disable the reference voltage output
*/
static inline void adc_ll_vref_output(adc_unit_t adc, adc_channel_t channel, bool en)
{
abort(); //TODO IDF-3908
// if (en) {
// REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 3);
// SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
// REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2);
// SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN);
// SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE);
// SET_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE);
// APB_SARADC.sar_patt_tab[0].sar_patt_tab1 = 0xFFFFFF;
// APB_SARADC.sar_patt_tab[1].sar_patt_tab1 = 0xFFFFFF;
// APB_SARADC.onetime_sample.adc1_onetime_sample = 1;
// APB_SARADC.onetime_sample.onetime_channel = channel;
// SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU);
// if (adc == ADC_UNIT_1) {
// /* Config test mux to route v_ref to ADC1 Channels */
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 1);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 1);
// } else {
// /* Config test mux to route v_ref to ADC2 Channels */
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
// }
// } else {
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
// REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
// APB_SARADC.onetime_sample.adc1_onetime_sample = 0;
// APB_SARADC.onetime_sample.onetime_channel = 0xf;
// REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0);
// REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 0);
// CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN);
// CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_GRANT_FORCE);
// CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_ARB_CTRL_REG, APB_SARADC_ADC_ARB_APB_FORCE);
// }
}
/*---------------------------------------------------------------
Single Read
Oneshot Read
---------------------------------------------------------------*/
/**
* Set adc output data format for oneshot mode
*
* @note ESP32C3 Oneshot mode only supports 12bit.
* @note ESP32C2 Oneshot mode only supports 12bit.
* @param adc_n ADC unit.
* @param bits Output data bits width option.
*/
static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits)
{
abort(); //TODO IDF-3908
// //ESP32C3 only supports 12bit, leave here for compatibility
// HAL_ASSERT(bits == ADC_BITWIDTH_12);
//ESP32C2 only supports 12bit, leave here for compatibility
HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT);
}
/**
@@ -792,8 +413,8 @@ static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth
*/
static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel)
{
abort(); //TODO IDF-3908
// APB_SARADC.onetime_sample.onetime_channel = ((adc_n << 3) | channel);
HAL_ASSERT(adc_n == ADC_UNIT_1);
APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | channel);
}
/**
@@ -805,12 +426,8 @@ static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t ch
*/
static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n)
{
abort(); //TODO IDF-3908
// if (adc_n == ADC_UNIT_1) {
// APB_SARADC.onetime_sample.onetime_channel = ((adc_n << 3) | 0xF);
// } else { // adc_n == ADC_UNIT_2
// APB_SARADC.onetime_sample.onetime_channel = ((adc_n << 3) | 0x1);
// }
HAL_ASSERT(adc_n == ADC_UNIT_1);
APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0xF);
}
/**
@@ -822,8 +439,7 @@ static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n)
*/
static inline void adc_oneshot_ll_start(bool val)
{
abort(); //TODO IDF-3908
// APB_SARADC.onetime_sample.onetime_start = val;
APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_start = val;
}
/**
@@ -833,8 +449,7 @@ static inline void adc_oneshot_ll_start(bool val)
*/
static inline void adc_oneshot_ll_clear_event(uint32_t event_mask)
{
abort(); //TODO IDF-3908
// APB_SARADC.int_clr.val |= event_mask;
APB_SARADC.saradc_int_clr.val |= event_mask;
}
/**
@@ -848,8 +463,7 @@ static inline void adc_oneshot_ll_clear_event(uint32_t event_mask)
*/
static inline bool adc_oneshot_ll_get_event(uint32_t event_mask)
{
abort(); //TODO IDF-3908
// return (APB_SARADC.int_raw.val & event_mask);
return (APB_SARADC.saradc_int_raw.val & event_mask);
}
/**
@@ -861,14 +475,10 @@ static inline bool adc_oneshot_ll_get_event(uint32_t event_mask)
*/
static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
{
abort(); //TODO IDF-3908
// uint32_t ret_val = 0;
// if (adc_n == ADC_UNIT_1) {
// ret_val = APB_SARADC.apb_saradc1_data_status.adc1_data & 0xfff;
// } else { // adc_n == ADC_UNIT_2
// ret_val = APB_SARADC.apb_saradc2_data_status.adc2_data & 0xfff;
// }
// return ret_val;
HAL_ASSERT(adc_n == ADC_UNIT_1);
uint32_t ret_val = 0;
ret_val = APB_SARADC.saradc1_data_status.saradc1_data & 0xfff;
return ret_val;
}
/**
@@ -883,17 +493,8 @@ static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
*/
static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data)
{
abort(); //TODO IDF-3908
// if (adc_n == ADC_UNIT_1) {
// return true;
// }
// //The raw data API returns value without channel information. Read value directly from the register
// if (((APB_SARADC.apb_saradc2_data_status.adc2_data >> 13) & 0xF) > 9) {
// return false;
// }
// return true;
HAL_ASSERT(adc_n == ADC_UNIT_1);
return true;
}
/**
@@ -904,10 +505,9 @@ static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw
*/
static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en)
{
abort(); //TODO IDF-3908
// (void)adc_n;
// (void)inv_en;
// //For compatibility
(void)adc_n;
(void)inv_en;
//For compatibility
}
/**
@@ -917,12 +517,8 @@ static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en)
*/
static inline void adc_oneshot_ll_enable(adc_unit_t adc_n)
{
abort(); //TODO IDF-3908
// if (adc_n == ADC_UNIT_1) {
// APB_SARADC.onetime_sample.adc1_onetime_sample = 1;
// } else {
// APB_SARADC.onetime_sample.adc2_onetime_sample = 1;
// }
HAL_ASSERT(adc_n == ADC_UNIT_1);
APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1;
}
/**
@@ -930,9 +526,8 @@ static inline void adc_oneshot_ll_enable(adc_unit_t adc_n)
*/
static inline void adc_oneshot_ll_disable_all_unit(void)
{
abort(); //TODO IDF-3908
// APB_SARADC.onetime_sample.adc1_onetime_sample = 0;
// APB_SARADC.onetime_sample.adc2_onetime_sample = 0;
APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 0;
APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 0;
}
/**
@@ -946,11 +541,24 @@ static inline void adc_oneshot_ll_disable_all_unit(void)
*/
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
abort(); //TODO IDF-3908
// (void)adc_n;
// (void)channel;
// // Attenuation is for all channels, unit and channel are for compatibility
// APB_SARADC.onetime_sample.onetime_atten = atten;
(void)adc_n;
(void)channel;
// Attenuation is for all channels, unit and channel are for compatibility
APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten = atten;
}
/**
* Get the attenuation of a particular channel on ADCn.
*
* @param adc_n ADC unit.
* @param channel ADCn channel number.
* @return atten The attenuation option.
*/
static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
{
(void)adc_n;
(void)channel;
return APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten;
}
#ifdef __cplusplus