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esp32c6: add soc/ reg and struct headers
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songruojing
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Song Ruo Jing
Song Ruo Jing
parent
e7dbfd65cb
commit
a00f217341
249
components/soc/esp32c6/include/soc/trace_struct.h
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249
components/soc/esp32c6/include/soc/trace_struct.h
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/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Trace memory configuration registers */
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/** Type of mem_start_addr register
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* mem start addr
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*/
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typedef union {
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struct {
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/** mem_start_addr : R/W; bitpos: [31:0]; default: 0;
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* The start address of trace memory
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*/
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uint32_t mem_start_addr:32;
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};
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uint32_t val;
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} trace_mem_start_addr_reg_t;
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/** Type of mem_end_addr register
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* mem end addr
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*/
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typedef union {
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struct {
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/** mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
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* The end address of trace memory
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*/
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uint32_t mem_end_addr:32;
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};
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uint32_t val;
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} trace_mem_end_addr_reg_t;
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/** Type of mem_current_addr register
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* mem current addr
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*/
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typedef union {
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struct {
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/** mem_current_addr : RO; bitpos: [31:0]; default: 0;
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* current_mem_addr,indicate that next writing addr
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*/
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uint32_t mem_current_addr:32;
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};
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uint32_t val;
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} trace_mem_current_addr_reg_t;
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/** Type of mem_addr_update register
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* mem addr update
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*/
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typedef union {
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struct {
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/** mem_current_addr_update : WT; bitpos: [0]; default: 0;
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* when set this reg, the current_mem_addr will update to start_addr
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*/
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uint32_t mem_current_addr_update:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} trace_mem_addr_update_reg_t;
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/** Group: Trace fifo status register */
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/** Type of fifo_status register
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* fifo status register
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*/
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typedef union {
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struct {
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/** fifo_empty : RO; bitpos: [0]; default: 1;
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* 1 indicate that fifo is empty
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*/
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uint32_t fifo_empty:1;
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/** work_status : RO; bitpos: [1]; default: 0;
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* mem_full interrupt status
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*/
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uint32_t work_status:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} trace_fifo_status_reg_t;
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/** Group: Trace interrupt configuration registers */
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/** Type of intr_ena register
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* interrupt enable register
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*/
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typedef union {
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struct {
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/** fifo_overflow_intr_ena : R/W; bitpos: [0]; default: 0;
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* Set 1 enable fifo_overflow interrupt
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*/
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uint32_t fifo_overflow_intr_ena:1;
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/** mem_full_intr_ena : R/W; bitpos: [1]; default: 0;
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* Set 1 enable mem_full interrupt
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*/
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uint32_t mem_full_intr_ena:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} trace_intr_ena_reg_t;
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/** Type of intr_raw register
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* interrupt status register
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*/
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typedef union {
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struct {
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/** fifo_overflow_intr_raw : RO; bitpos: [0]; default: 0;
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* fifo_overflow interrupt status
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*/
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uint32_t fifo_overflow_intr_raw:1;
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/** mem_full_intr_raw : RO; bitpos: [1]; default: 0;
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* mem_full interrupt status
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*/
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uint32_t mem_full_intr_raw:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} trace_intr_raw_reg_t;
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/** Type of intr_clr register
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* interrupt clear register
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*/
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typedef union {
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struct {
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/** fifo_overflow_intr_clr : WT; bitpos: [0]; default: 0;
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* Set 1 clr fifo overflow interrupt
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*/
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uint32_t fifo_overflow_intr_clr:1;
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/** mem_full_intr_clr : WT; bitpos: [1]; default: 0;
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* Set 1 clr mem full interrupt
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*/
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uint32_t mem_full_intr_clr:1;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} trace_intr_clr_reg_t;
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/** Group: Trace configuration register */
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/** Type of trigger register
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* trigger register
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*/
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typedef union {
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struct {
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/** trigger_on : WT; bitpos: [0]; default: 0;
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* [0] set 1 start trace.
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*/
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uint32_t trigger_on:1;
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/** trigger_off : WT; bitpos: [1]; default: 0;
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* set 1 stop trace.
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*/
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uint32_t trigger_off:1;
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/** mem_loop : R/W; bitpos: [2]; default: 1;
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* if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr
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* at mem_end_addr, it will stop at the mem_end_addr
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*/
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uint32_t mem_loop:1;
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/** restart_ena : R/W; bitpos: [3]; default: 1;
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* enable encoder auto-restart, when lost package, the encoder will end, if enable
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* auto-restart, when fifo empty, encoder will restart and send a sync package.
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*/
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uint32_t restart_ena:1;
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uint32_t reserved_4:28;
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};
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uint32_t val;
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} trace_trigger_reg_t;
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/** Type of resync_prolonged register
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* resync configuration register
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*/
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typedef union {
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struct {
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/** resync_prolonged : R/W; bitpos: [23:0]; default: 128;
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* count number, when count to this value, send a sync package
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*/
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uint32_t resync_prolonged:24;
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/** resync_mode : R/W; bitpos: [24]; default: 0;
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* resyc mode sel: 0: default, cycle count 1: package num count
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*/
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uint32_t resync_mode:1;
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uint32_t reserved_25:7;
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};
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uint32_t val;
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} trace_resync_prolonged_reg_t;
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/** Group: Clock Gate Control and configuration register */
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/** Type of clock_gate register
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* Clock gate control register
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*/
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typedef union {
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struct {
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/** clk_en : R/W; bitpos: [0]; default: 1;
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* The bit is used to enable clock gate when access all registers in this module.
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*/
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uint32_t clk_en:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} trace_clock_gate_reg_t;
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/** Group: Version register */
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/** Type of date register
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* Version control register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 35663920;
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* version control register. Note that this default value stored is the latest date
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* when the hardware logic was updated.
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} trace_date_reg_t;
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typedef struct trace_dev_t {
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volatile trace_mem_start_addr_reg_t mem_start_addr;
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volatile trace_mem_end_addr_reg_t mem_end_addr;
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volatile trace_mem_current_addr_reg_t mem_current_addr;
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volatile trace_mem_addr_update_reg_t mem_addr_update;
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volatile trace_fifo_status_reg_t fifo_status;
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volatile trace_intr_ena_reg_t intr_ena;
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volatile trace_intr_raw_reg_t intr_raw;
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volatile trace_intr_clr_reg_t intr_clr;
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volatile trace_trigger_reg_t trigger;
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volatile trace_resync_prolonged_reg_t resync_prolonged;
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volatile trace_clock_gate_reg_t clock_gate;
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uint32_t reserved_02c[244];
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volatile trace_date_reg_t date;
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} trace_dev_t;
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extern trace_dev_t TRACE;
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#ifndef __cplusplus
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_Static_assert(sizeof(trace_dev_t) == 0x400, "Invalid size of trace_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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