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efuse: Updates efuse table for esp32c6

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This commit is contained in:
KonstantinKondrashov
2023-02-16 01:49:24 +08:00
parent e4bb430743
commit a0408f7324
10 changed files with 1259 additions and 898 deletions
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17
components/soc/esp32c6/include/soc/efuse_defs.h Normal file
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@@ -0,0 +1,17 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#ifdef __cplusplus
}
#endif

231
components/soc/esp32c6/include/soc/efuse_reg.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,6 +7,7 @@
#include <stdint.h>
#include "soc/soc.h"
#include "efuse_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -222,13 +223,13 @@ extern "C" {
#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U
#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13
/** EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0;
/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
* Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
*/
#define EFUSE_DIS_CAN (BIT(14))
#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S)
#define EFUSE_DIS_CAN_V 0x00000001U
#define EFUSE_DIS_CAN_S 14
#define EFUSE_DIS_TWAI (BIT(14))
#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
#define EFUSE_DIS_TWAI_V 0x00000001U
#define EFUSE_DIS_TWAI_S 14
/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
* Represents whether the selection between usb_to_jtag and pad_to_jtag through
* strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
@@ -411,27 +412,27 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU
#define EFUSE_KEY_PURPOSE_5_S 12
/** EFUSE_DPA_SEC_LEVEL : RO; bitpos: [17:16]; default: 0;
/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
* Represents the spa secure level by configuring the clock random divide mode.
*/
#define EFUSE_DPA_SEC_LEVEL 0x00000003U
#define EFUSE_DPA_SEC_LEVEL_M (EFUSE_DPA_SEC_LEVEL_V << EFUSE_DPA_SEC_LEVEL_S)
#define EFUSE_DPA_SEC_LEVEL_V 0x00000003U
#define EFUSE_DPA_SEC_LEVEL_S 16
/** EFUSE_RPT4_RESERVED2_1 : RO; bitpos: [18]; default: 0;
* Reserved.
*/
#define EFUSE_RPT4_RESERVED2_1 (BIT(18))
#define EFUSE_RPT4_RESERVED2_1_M (EFUSE_RPT4_RESERVED2_1_V << EFUSE_RPT4_RESERVED2_1_S)
#define EFUSE_RPT4_RESERVED2_1_V 0x00000001U
#define EFUSE_RPT4_RESERVED2_1_S 18
/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
#define EFUSE_SEC_DPA_LEVEL 0x00000003U
#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U
#define EFUSE_SEC_DPA_LEVEL_S 16
/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [18]; default: 0;
* Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
*/
#define EFUSE_CRYPT_DPA_ENABLE (BIT(19))
#define EFUSE_CRYPT_DPA_ENABLE (BIT(18))
#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U
#define EFUSE_CRYPT_DPA_ENABLE_S 19
#define EFUSE_CRYPT_DPA_ENABLE_S 18
/** EFUSE_RPT4_RESERVED2_1 : RO; bitpos: [19]; default: 1;
* Reserved.
*/
#define EFUSE_RPT4_RESERVED2_1 (BIT(19))
#define EFUSE_RPT4_RESERVED2_1_M (EFUSE_RPT4_RESERVED2_1_V << EFUSE_RPT4_RESERVED2_1_S)
#define EFUSE_RPT4_RESERVED2_1_V 0x00000001U
#define EFUSE_RPT4_RESERVED2_1_S 19
/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
* Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
*/
@@ -482,14 +483,14 @@ extern "C" {
#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U
#define EFUSE_DIS_DIRECT_BOOT_S 1
/** EFUSE_DIS_USB_PRINT : RO; bitpos: [2]; default: 0;
/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
* Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
* 0: enabled.
*/
#define EFUSE_DIS_USB_PRINT (BIT(2))
#define EFUSE_DIS_USB_PRINT_M (EFUSE_DIS_USB_PRINT_V << EFUSE_DIS_USB_PRINT_S)
#define EFUSE_DIS_USB_PRINT_V 0x00000001U
#define EFUSE_DIS_USB_PRINT_S 2
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2))
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2
/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0;
* Reserved.
*/
@@ -585,13 +586,27 @@ extern "C" {
* BLOCK0 data register 5.
*/
#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
/** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:0]; default: 0;
* Reserved.
/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0;
* Disables check of wafer version major
*/
#define EFUSE_RPT4_RESERVED4_1 0x00FFFFFFU
#define EFUSE_RPT4_RESERVED4_1_M (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S)
#define EFUSE_RPT4_RESERVED4_1_V 0x00FFFFFFU
#define EFUSE_RPT4_RESERVED4_1_S 0
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(0))
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 0
/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0;
* Disables check of blk version major
*/
#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(1))
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 1
/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_0_162 0x003FFFFFU
#define EFUSE_RESERVED_0_162_M (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S)
#define EFUSE_RESERVED_0_162_V 0x003FFFFFU
#define EFUSE_RESERVED_0_162_S 2
/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0;
* Reserved.
*/
@@ -661,25 +676,64 @@ extern "C" {
#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S)
#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFFU
#define EFUSE_SPI_PAD_CONF_2_S 0
/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
* Stores the first 14 bits of the zeroth part of system data.
/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [21:18]; default: 0; */
#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU
#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU
#define EFUSE_WAFER_VERSION_MINOR_S 18
/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [23:22]; default: 0; */
#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U
#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U
#define EFUSE_WAFER_VERSION_MAJOR_S 22
/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0;
* BLK_VERSION_MINOR of BLOCK2
*/
#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_S 18
#define EFUSE_BLK_VERSION_MINOR 0x00000007U
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
#define EFUSE_BLK_VERSION_MINOR_S 24
/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [28:27]; default: 0;
* BLK_VERSION_MAJOR of BLOCK2
*/
#define EFUSE_BLK_VERSION_MAJOR 0x00000003U
#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U
#define EFUSE_BLK_VERSION_MAJOR_S 27
/** EFUSE_PKG_VERSION : R; bitpos: [31:29]; default: 0;
* Package version
*/
#define EFUSE_PKG_VERSION 0x00000007U
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
#define EFUSE_PKG_VERSION_V 0x00000007U
#define EFUSE_PKG_VERSION_S 29
/** EFUSE_RD_MAC_SPI_SYS_4_REG register
* BLOCK1 data register $n.
*/
#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the zeroth part of system data.
/** EFUSE_FLASH_CAP : R; bitpos: [2:0]; default: 0; */
#define EFUSE_FLASH_CAP 0x00000007U
#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
#define EFUSE_FLASH_CAP_V 0x00000007U
#define EFUSE_FLASH_CAP_S 0
/** EFUSE_FLASH_TEMP : R; bitpos: [4:3]; default: 0; */
#define EFUSE_FLASH_TEMP 0x00000003U
#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
#define EFUSE_FLASH_TEMP_V 0x00000003U
#define EFUSE_FLASH_TEMP_S 3
/** EFUSE_FLASH_VENDOR : R; bitpos: [7:5]; default: 0; */
#define EFUSE_FLASH_VENDOR 0x00000007U
#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
#define EFUSE_FLASH_VENDOR_V 0x00000007U
#define EFUSE_FLASH_VENDOR_S 5
/** EFUSE_RESERVED_1_136 : R; bitpos: [31:8]; default: 0;
* reserved
*/
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_S 0
#define EFUSE_RESERVED_1_136 0x00FFFFFFU
#define EFUSE_RESERVED_1_136_M (EFUSE_RESERVED_1_136_V << EFUSE_RESERVED_1_136_S)
#define EFUSE_RESERVED_1_136_V 0x00FFFFFFU
#define EFUSE_RESERVED_1_136_S 8
/** EFUSE_RD_MAC_SPI_SYS_5_REG register
* BLOCK1 data register $n.
@@ -697,49 +751,49 @@ extern "C" {
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
* Stores the zeroth 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_0_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_S 0
/** EFUSE_RD_SYS_PART1_DATA1_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_1_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0
/** EFUSE_RD_SYS_PART1_DATA2_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_2_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0
/** EFUSE_RD_SYS_PART1_DATA3_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
* Stores the third 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_3_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0
/** EFUSE_RD_SYS_PART1_DATA4_REG register
* Register $n of BLOCK2 (system).
@@ -865,25 +919,39 @@ extern "C" {
* Register $n of BLOCK3 (user).
*/
#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
* Stores the sixth 32 bits of BLOCK3 (user).
/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
* reserved
*/
#define EFUSE_USR_DATA6 0xFFFFFFFFU
#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
#define EFUSE_USR_DATA6_V 0xFFFFFFFFU
#define EFUSE_USR_DATA6_S 0
#define EFUSE_RESERVED_3_192 0x000000FFU
#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
#define EFUSE_RESERVED_3_192_V 0x000000FFU
#define EFUSE_RESERVED_3_192_S 0
/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
* Custom MAC
*/
#define EFUSE_CUSTOM_MAC 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_S 8
/** EFUSE_RD_USR_DATA7_REG register
* Register $n of BLOCK3 (user).
*/
#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
* Stores the seventh 32 bits of BLOCK3 (user).
/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
* Custom MAC
*/
#define EFUSE_USR_DATA7 0xFFFFFFFFU
#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
#define EFUSE_USR_DATA7_V 0xFFFFFFFFU
#define EFUSE_USR_DATA7_S 0
#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_1_S 0
/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_3_248 0x000000FFU
#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
#define EFUSE_RESERVED_3_248_V 0x000000FFU
#define EFUSE_RESERVED_3_248_S 24
/** EFUSE_RD_KEY0_DATA0_REG register
* Register $n of BLOCK4 (KEY0).
@@ -2172,9 +2240,6 @@ extern "C" {
#define EFUSE_OP_CODE_V 0x0000FFFFU
#define EFUSE_OP_CODE_S 0
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
/** EFUSE_STATUS_REG register
* eFuse status register.
*/

389
components/soc/esp32c6/include/soc/efuse_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -155,7 +155,7 @@ typedef union {
} efuse_pgm_check_value2_reg_t;
/** Group: ******** Registers */
/** Group: Read Data Register */
/** Type of rd_wr_dis register
* BLOCK0 data register 0.
*/
@@ -213,10 +213,10 @@ typedef union {
* enabled. 1: disabled. 0: enabled.
*/
uint32_t spi_download_mspi_dis:1;
/** dis_can : RO; bitpos: [14]; default: 0;
/** dis_twai : RO; bitpos: [14]; default: 0;
* Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
*/
uint32_t dis_can:1;
uint32_t dis_twai:1;
/** jtag_sel_enable : RO; bitpos: [15]; default: 0;
* Represents whether the selection between usb_to_jtag and pad_to_jtag through
* strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
@@ -338,18 +338,18 @@ typedef union {
* Represents the purpose of Key5.
*/
uint32_t key_purpose_5:4;
/** dpa_sec_level : RO; bitpos: [17:16]; default: 0;
/** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
* Represents the spa secure level by configuring the clock random divide mode.
*/
uint32_t dpa_sec_level:2;
/** rpt4_reserved2_1 : RO; bitpos: [18]; default: 0;
* Reserved.
*/
uint32_t rpt4_reserved2_1:1;
/** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
uint32_t sec_dpa_level:2;
/** crypt_dpa_enable : RO; bitpos: [18]; default: 0;
* Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
*/
uint32_t crypt_dpa_enable:1;
/** rpt4_reserved2_1 : RO; bitpos: [19]; default: 1;
* Reserved.
*/
uint32_t rpt4_reserved2_1:1;
/** secure_boot_en : RO; bitpos: [20]; default: 0;
* Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
*/
@@ -386,11 +386,11 @@ typedef union {
* Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
*/
uint32_t dis_direct_boot:1;
/** dis_usb_print : RO; bitpos: [2]; default: 0;
/** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
* Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
* 0: enabled.
*/
uint32_t dis_usb_print:1;
uint32_t dis_usb_serial_jtag_rom_print:1;
/** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0;
* Reserved.
*/
@@ -454,10 +454,22 @@ typedef union {
*/
typedef union {
struct {
/** disable_wafer_version_major : R; bitpos: [0]; default: 0;
* Disables check of wafer version major
*/
uint32_t disable_wafer_version_major:1;
uint32_t disable_blk_version_major: 1;
uint32_t rpt4_reserved4:22; /*Reserved.*/
uint32_t reserved24:8; /*Reserved.*/
/** disable_blk_version_major : R; bitpos: [1]; default: 0;
* Disables check of blk version major
*/
uint32_t disable_blk_version_major:1;
/** reserved_0_162 : R; bitpos: [23:2]; default: 0;
* reserved
*/
uint32_t reserved_0_162:22;
/** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0;
* Reserved.
*/
uint32_t rpt4_reserved4_0:8;
};
uint32_t val;
} efuse_rd_repeat_data4_reg_t;
@@ -484,10 +496,10 @@ typedef union {
* Stores the high 16 bits of MAC address.
*/
uint32_t mac_1:16;
/** spi_pad_conf_0 : RO; bitpos: [31:16]; default: 0;
* Stores the zeroth part of SPI_PAD_CONF.
/** mac_ext : RO; bitpos: [31:16]; default: 0;
* Stores the extended bits of MAC address.
*/
uint32_t spi_pad_conf_0:16;
uint32_t mac_ext:16;
};
uint32_t val;
} efuse_rd_mac_spi_sys_1_reg_t;
@@ -497,7 +509,14 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved:32;
/** mac_spi_reserved : RO; bitpos: [13:0]; default: 0;
* Reserved.
*/
uint32_t mac_spi_reserved:14;
/** spi_pad_conf_1 : RO; bitpos: [31:14]; default: 0;
* Stores the first part of SPI_PAD_CONF.
*/
uint32_t spi_pad_conf_1:18;
};
uint32_t val;
} efuse_rd_mac_spi_sys_2_reg_t;
@@ -511,13 +530,22 @@ typedef union {
* Stores the second part of SPI_PAD_CONF.
*/
uint32_t spi_pad_conf_2:18;
uint32_t wafer_version_minor_low:3;
uint32_t pkg_version:3;
uint32_t blk_version_minor:3;
/** sys_data_part0_0 : RO; bitpos: [31:27]; default: 0;
* Stores the first 5 bits of the zeroth part of system data.
/** wafer_version_minor : R; bitpos: [21:18]; default: 0; */
uint32_t wafer_version_minor:4;
/** wafer_version_major : R; bitpos: [23:22]; default: 0; */
uint32_t wafer_version_major:2;
/** blk_version_minor : R; bitpos: [26:24]; default: 0;
* BLK_VERSION_MINOR of BLOCK2
*/
uint32_t sys_data_part0_0:5;
uint32_t blk_version_minor:3;
/** blk_version_major : R; bitpos: [28:27]; default: 0;
* BLK_VERSION_MAJOR of BLOCK2
*/
uint32_t blk_version_major:2;
/** pkg_version : R; bitpos: [31:29]; default: 0;
* Package version
*/
uint32_t pkg_version:3;
};
uint32_t val;
} efuse_rd_mac_spi_sys_3_reg_t;
@@ -527,7 +555,16 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved:32;
/** flash_cap : R; bitpos: [2:0]; default: 0; */
uint32_t flash_cap:3;
/** flash_temp : R; bitpos: [4:3]; default: 0; */
uint32_t flash_temp:2;
/** flash_vendor : R; bitpos: [7:5]; default: 0; */
uint32_t flash_vendor:3;
/** reserved_1_136 : R; bitpos: [31:8]; default: 0;
* reserved
*/
uint32_t reserved_1_136:24;
};
uint32_t val;
} efuse_rd_mac_spi_sys_4_reg_t;
@@ -537,10 +574,10 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved1:23;
uint32_t wafer_version_minor_high:1;
uint32_t wafer_version_major:2;
uint32_t reserved2:6;
/** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the zeroth part of system data.
*/
uint32_t sys_data_part0_2:32;
};
uint32_t val;
} efuse_rd_mac_spi_sys_5_reg_t;
@@ -550,10 +587,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
* Stores the zeroth 32 bits of the first part of system data.
/** optional_unique_id : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_0:32;
uint32_t optional_unique_id:32;
};
uint32_t val;
} efuse_rd_sys_part1_data0_reg_t;
@@ -563,10 +600,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the first part of system data.
/** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_1:32;
uint32_t optional_unique_id_1:32;
};
uint32_t val;
} efuse_rd_sys_part1_data1_reg_t;
@@ -576,10 +613,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the first part of system data.
/** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_2:32;
uint32_t optional_unique_id_2:32;
};
uint32_t val;
} efuse_rd_sys_part1_data2_reg_t;
@@ -589,10 +626,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
* Stores the third 32 bits of the first part of system data.
/** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_3:32;
uint32_t optional_unique_id_3:32;
};
uint32_t val;
} efuse_rd_sys_part1_data3_reg_t;
@@ -602,8 +639,10 @@ typedef union {
*/
typedef union {
struct {
uint32_t blk_version_major :2;
uint32_t reserved1:30;
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
* Stores the fourth 32 bits of the first part of system data.
*/
uint32_t sys_data_part1_4:32;
};
uint32_t val;
} efuse_rd_sys_part1_data4_reg_t;
@@ -730,10 +769,14 @@ typedef union {
*/
typedef union {
struct {
/** usr_data6 : RO; bitpos: [31:0]; default: 0;
* Stores the sixth 32 bits of BLOCK3 (user).
/** reserved_3_192 : R; bitpos: [7:0]; default: 0;
* reserved
*/
uint32_t usr_data6:32;
uint32_t reserved_3_192:8;
/** custom_mac : R; bitpos: [31:8]; default: 0;
* Custom MAC
*/
uint32_t custom_mac:24;
};
uint32_t val;
} efuse_rd_usr_data6_reg_t;
@@ -743,10 +786,14 @@ typedef union {
*/
typedef union {
struct {
/** usr_data7 : RO; bitpos: [31:0]; default: 0;
* Stores the seventh 32 bits of BLOCK3 (user).
/** custom_mac_1 : R; bitpos: [23:0]; default: 0;
* Custom MAC
*/
uint32_t usr_data7:32;
uint32_t custom_mac_1:24;
/** reserved_3_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
uint32_t reserved_3_248:8;
};
uint32_t val;
} efuse_rd_usr_data7_reg_t;
@@ -1479,6 +1526,8 @@ typedef union {
uint32_t val;
} efuse_rd_sys_part2_data7_reg_t;
/** Group: Report Register */
/** Type of rd_repeat_err0 register
* Programming error record register 0 of BLOCK0.
*/
@@ -1853,6 +1902,8 @@ typedef union {
uint32_t val;
} efuse_rd_rs_err1_reg_t;
/** Group: Configuration Register */
/** Type of clk register
* eFuse clcok configuration register.
*/
@@ -1894,48 +1945,6 @@ typedef union {
uint32_t val;
} efuse_conf_reg_t;
/** Type of status register
* eFuse status register.
*/
typedef union {
struct {
/** state : RO; bitpos: [3:0]; default: 0;
* Indicates the state of the eFuse state machine.
*/
uint32_t state:4;
/** otp_load_sw : RO; bitpos: [4]; default: 0;
* The value of OTP_LOAD_SW.
*/
uint32_t otp_load_sw:1;
/** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
* The value of OTP_VDDQ_C_SYNC2.
*/
uint32_t otp_vddq_c_sync2:1;
/** otp_strobe_sw : RO; bitpos: [6]; default: 0;
* The value of OTP_STROBE_SW.
*/
uint32_t otp_strobe_sw:1;
/** otp_csb_sw : RO; bitpos: [7]; default: 0;
* The value of OTP_CSB_SW.
*/
uint32_t otp_csb_sw:1;
/** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
* The value of OTP_PGENB_SW.
*/
uint32_t otp_pgenb_sw:1;
/** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
* The value of OTP_VDDQ_IS_SW.
*/
uint32_t otp_vddq_is_sw:1;
/** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
* Indicates the number of block valid bit.
*/
uint32_t blk0_valid_bit_cnt:10;
uint32_t reserved_20:12;
};
uint32_t val;
} efuse_status_reg_t;
/** Type of cmd register
* eFuse command register.
*/
@@ -1959,78 +1968,6 @@ typedef union {
uint32_t val;
} efuse_cmd_reg_t;
/** Type of int_raw register
* eFuse raw interrupt register.
*/
typedef union {
struct {
/** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw bit signal for read_done interrupt.
*/
uint32_t read_done_int_raw:1;
/** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw bit signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_raw_reg_t;
/** Type of int_st register
* eFuse interrupt status register.
*/
typedef union {
struct {
/** read_done_int_st : RO; bitpos: [0]; default: 0;
* The status signal for read_done interrupt.
*/
uint32_t read_done_int_st:1;
/** pgm_done_int_st : RO; bitpos: [1]; default: 0;
* The status signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_st_reg_t;
/** Type of int_ena register
* eFuse interrupt enable register.
*/
typedef union {
struct {
/** read_done_int_ena : R/W; bitpos: [0]; default: 0;
* The enable signal for read_done interrupt.
*/
uint32_t read_done_int_ena:1;
/** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
* The enable signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_ena_reg_t;
/** Type of int_clr register
* eFuse interrupt clear register.
*/
typedef union {
struct {
/** read_done_int_clr : WO; bitpos: [0]; default: 0;
* The clear signal for read_done interrupt.
*/
uint32_t read_done_int_clr:1;
/** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
* The clear signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_clr_reg_t;
/** Type of dac_conf register
* Controls the eFuse programming voltage.
*/
@@ -2147,6 +2084,126 @@ typedef union {
uint32_t val;
} efuse_wr_tim_conf0_rs_bypass_reg_t;
/** Group: Status Register */
/** Type of status register
* eFuse status register.
*/
typedef union {
struct {
/** state : RO; bitpos: [3:0]; default: 0;
* Indicates the state of the eFuse state machine.
*/
uint32_t state:4;
/** otp_load_sw : RO; bitpos: [4]; default: 0;
* The value of OTP_LOAD_SW.
*/
uint32_t otp_load_sw:1;
/** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
* The value of OTP_VDDQ_C_SYNC2.
*/
uint32_t otp_vddq_c_sync2:1;
/** otp_strobe_sw : RO; bitpos: [6]; default: 0;
* The value of OTP_STROBE_SW.
*/
uint32_t otp_strobe_sw:1;
/** otp_csb_sw : RO; bitpos: [7]; default: 0;
* The value of OTP_CSB_SW.
*/
uint32_t otp_csb_sw:1;
/** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
* The value of OTP_PGENB_SW.
*/
uint32_t otp_pgenb_sw:1;
/** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
* The value of OTP_VDDQ_IS_SW.
*/
uint32_t otp_vddq_is_sw:1;
/** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
* Indicates the number of block valid bit.
*/
uint32_t blk0_valid_bit_cnt:10;
uint32_t reserved_20:12;
};
uint32_t val;
} efuse_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* eFuse raw interrupt register.
*/
typedef union {
struct {
/** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw bit signal for read_done interrupt.
*/
uint32_t read_done_int_raw:1;
/** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw bit signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_raw_reg_t;
/** Type of int_st register
* eFuse interrupt status register.
*/
typedef union {
struct {
/** read_done_int_st : RO; bitpos: [0]; default: 0;
* The status signal for read_done interrupt.
*/
uint32_t read_done_int_st:1;
/** pgm_done_int_st : RO; bitpos: [1]; default: 0;
* The status signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_st_reg_t;
/** Type of int_ena register
* eFuse interrupt enable register.
*/
typedef union {
struct {
/** read_done_int_ena : R/W; bitpos: [0]; default: 0;
* The enable signal for read_done interrupt.
*/
uint32_t read_done_int_ena:1;
/** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
* The enable signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_ena_reg_t;
/** Type of int_clr register
* eFuse interrupt clear register.
*/
typedef union {
struct {
/** read_done_int_clr : WO; bitpos: [0]; default: 0;
* The clear signal for read_done interrupt.
*/
uint32_t read_done_int_clr:1;
/** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
* The clear signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* eFuse version register.
*/
@@ -2162,7 +2219,7 @@ typedef union {
} efuse_date_reg_t;
typedef struct efuse_dev_t {
typedef struct {
volatile efuse_pgm_data0_reg_t pgm_data0;
volatile efuse_pgm_data1_reg_t pgm_data1;
volatile efuse_pgm_data2_reg_t pgm_data2;