alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-10 04:43:33 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'refactor/cache_utils_refactor_to_cache_hal' into 'master'

Browse Source 
cache: refactor cache_utils to use cache_hal instade

Closes IDF-7172 and IDF-7385

See merge request espressif/esp-idf!23317
This commit is contained in:
Wan Lei
2023-06-19 11:54:12 +08:00
parent 81e418b1f2 0f7e39d15a
commit a0dc515143
18 changed files with 338 additions and 124 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
components/hal/esp32/cache_hal_esp32.c Normal file
View File

@@ -0,0 +1,40 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/cache_ll.h"
#include "hal/cache_hal.h"
static uint32_t s_cache_status[2];
void cache_hal_suspend(cache_type_t type)
{
s_cache_status[0] = cache_ll_l1_get_enabled_bus(0);
cache_ll_l1_disable_cache(0);
#if !CONFIG_FREERTOS_UNICORE
s_cache_status[1] = cache_ll_l1_get_enabled_bus(1);
cache_ll_l1_disable_cache(1);
#endif
}
void cache_hal_resume(cache_type_t type)
{
cache_ll_l1_enable_cache(0);
cache_ll_l1_enable_bus(0, s_cache_status[0]);
#if !CONFIG_FREERTOS_UNICORE
cache_ll_l1_enable_cache(1);
cache_ll_l1_enable_bus(1, s_cache_status[1]);
#endif
}
bool cache_hal_is_cache_enabled(cache_type_t type)
{
bool result = cache_ll_l1_is_cache_enabled(0, CACHE_TYPE_ALL);
#if !CONFIG_FREERTOS_UNICORE
result = result && cache_ll_l1_is_cache_enabled(1, CACHE_TYPE_ALL);
#endif
return result;
}

60
components/hal/esp32/include/hal/cache_ll.h
View File

@@ -19,6 +19,66 @@
extern "C" {
#endif
/**
* @brief enable a cache unit
*
* @param cache_id cache ID (when l1 cache is per core)
*/
__attribute__((always_inline))
static inline void cache_ll_l1_enable_cache(uint32_t cache_id)
{
HAL_ASSERT(cache_id == 0 || cache_id == 1);
if (cache_id == 0) {
DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
} else {
DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
}
}
/**
* @brief disable a cache unit
*
* @param cache_id cache ID (when l1 cache is per core)
*/
__attribute__((always_inline))
static inline void cache_ll_l1_disable_cache(uint32_t cache_id)
{
if (cache_id == 0) {
while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1){
;
}
DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
} else {
while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1){
;
}
DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
}
}
/**
* @brief Get the status of cache if it is enabled or not
*
* @param cache_id cache ID (when l1 cache is per core)
* @param type see `cache_type_t`
* @return enabled or not
*/
__attribute__((always_inline))
static inline bool cache_ll_l1_is_cache_enabled(uint32_t cache_id, cache_type_t type)
{
HAL_ASSERT(cache_id == 0 || cache_id == 1);
(void) type; //On 32 it shares between I and D cache
bool enabled;
if (cache_id == 0) {
enabled = DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
} else {
enabled = DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
}
return enabled;
}
/**
* @brief Get the buses of a particular cache that are mapped to a virtual address range
*