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feat(sdmmc): sdmmc full ll layer
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -144,10 +144,13 @@ typedef struct sdmmc_dev_t {
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uint32_t val;
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} ctype;
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volatile struct {
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uint32_t blksiz: 16; ///< block size, default 0x200
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uint32_t reserved: 16;
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};
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volatile union {
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struct {
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uint32_t block_size: 16; ///< block size, default 0x200
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uint32_t reserved: 16;
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};
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uint32_t val;
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} blksiz;
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volatile uint32_t bytcnt; ///< number of bytes to be transferred
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@@ -300,7 +303,7 @@ typedef struct sdmmc_dev_t {
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*/
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uint32_t bus_type_reg:1;
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/** data_width_reg : RO; bitpos: [9:7]; default: 1;
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* Regisger data widht is 32.
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* Regisger data width is 32.
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*/
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uint32_t data_width_reg:3;
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/** addr_width_reg : RO; bitpos: [15:10]; default: 19;
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@@ -309,7 +312,7 @@ typedef struct sdmmc_dev_t {
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uint32_t addr_width_reg:6;
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uint32_t reserved_16:2;
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/** dma_width_reg : RO; bitpos: [20:18]; default: 1;
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* DMA data witdth is 32.
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* DMA data width is 32.
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*/
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uint32_t dma_width_reg:3;
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/** ram_indise_reg : RO; bitpos: [21]; default: 0;
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@@ -317,7 +320,7 @@ typedef struct sdmmc_dev_t {
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*/
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uint32_t ram_indise_reg:1;
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/** hold_reg : RO; bitpos: [22]; default: 1;
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* Have a hold regiser in data path .
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* Have a hold register in data path .
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*/
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uint32_t hold_reg:1;
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uint32_t reserved_23:1;
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@@ -335,6 +338,7 @@ typedef struct sdmmc_dev_t {
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uint32_t voltage: 16; ///< voltage control for slots; no-op on ESP32.
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uint32_t ddr: 16; ///< bit N enables DDR mode for card N
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};
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uint32_t val;
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} uhs; ///< UHS related settings
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volatile union {
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