From 9056974051e8e52c9d5f9b48a2657a06d392e5a1 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Thu, 4 Sep 2025 11:39:14 +0800 Subject: [PATCH 1/2] feat(gpio): ESP32P4 ECO5 GPIO related update --- .../soc/esp32/register/soc/io_mux_reg.h | 8 +- .../soc/esp32c2/register/soc/io_mux_reg.h | 9 +- .../soc/esp32c3/register/soc/io_mux_reg.h | 9 +- .../soc/esp32c5/register/soc/io_mux_reg.h | 8 - .../soc/esp32c6/register/soc/io_mux_reg.h | 9 +- .../soc/esp32h2/register/soc/io_mux_reg.h | 9 +- components/soc/esp32p4/emac_periph.c | 6 +- .../soc/esp32p4/include/soc/gpio_sig_map.h | 18 +- .../esp32p4/register/hw_ver1/soc/io_mux_reg.h | 19 +- .../hw_ver3/soc/gpio_ext_eco5_struct.h | 772 --- .../register/hw_ver3/soc/gpio_sig_map.h | 483 -- .../register/hw_ver3/soc/io_mux_eco5_reg.h | 5466 ----------------- .../register/hw_ver3/soc/io_mux_eco5_struct.h | 3430 ----------- .../esp32p4/register/hw_ver3/soc/io_mux_reg.h | 26 +- .../register/hw_ver3/soc/io_mux_struct.h | 1 - .../soc/esp32s2/register/soc/io_mux_reg.h | 15 +- .../soc/esp32s3/register/soc/io_mux_reg.h | 14 +- 17 files changed, 24 insertions(+), 10278 deletions(-) delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h diff --git a/components/soc/esp32/register/soc/io_mux_reg.h b/components/soc/esp32/register/soc/io_mux_reg.h index 773a9b77b9..01608eb800 100644 --- a/components/soc/esp32/register/soc/io_mux_reg.h +++ b/components/soc/esp32/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -84,12 +84,6 @@ #define PIN_FUNC_GPIO 2 -#define SPI_CLK_GPIO_NUM 6 -#define SPI_CS0_GPIO_NUM 11 -#define SPI_Q_GPIO_NUM 7 -#define SPI_D_GPIO_NUM 8 -#define SPI_WP_GPIO_NUM 10 -#define SPI_HD_GPIO_NUM 9 #define XTAL32K_P_GPIO_NUM 32 #define XTAL32K_N_GPIO_NUM 33 diff --git a/components/soc/esp32c2/register/soc/io_mux_reg.h b/components/soc/esp32c2/register/soc/io_mux_reg.h index 14e32a985f..a9bbf4b915 100644 --- a/components/soc/esp32c2/register/soc/io_mux_reg.h +++ b/components/soc/esp32c2/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -122,13 +122,6 @@ #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -#define SPI_HD_GPIO_NUM 12 -#define SPI_WP_GPIO_NUM 13 -#define SPI_CS0_GPIO_NUM 14 -#define SPI_CLK_GPIO_NUM 15 -#define SPI_D_GPIO_NUM 16 -#define SPI_Q_GPIO_NUM 17 - #define MAX_RTC_GPIO_NUM 5 #define MAX_PAD_GPIO_NUM 20 #define MAX_GPIO_NUM 24 diff --git a/components/soc/esp32c3/register/soc/io_mux_reg.h b/components/soc/esp32c3/register/soc/io_mux_reg.h index a85a3434dd..18858567e8 100644 --- a/components/soc/esp32c3/register/soc/io_mux_reg.h +++ b/components/soc/esp32c3/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -123,13 +123,6 @@ #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -#define SPI_HD_GPIO_NUM 12 -#define SPI_WP_GPIO_NUM 13 -#define SPI_CS0_GPIO_NUM 14 -#define SPI_CLK_GPIO_NUM 15 -#define SPI_D_GPIO_NUM 16 -#define SPI_Q_GPIO_NUM 17 - #define SD_CLK_GPIO_NUM 12 #define SD_CMD_GPIO_NUM 11 #define SD_DATA0_GPIO_NUM 13 diff --git a/components/soc/esp32c5/register/soc/io_mux_reg.h b/components/soc/esp32c5/register/soc/io_mux_reg.h index 18365a6a87..df8cc03f1c 100644 --- a/components/soc/esp32c5/register/soc/io_mux_reg.h +++ b/components/soc/esp32c5/register/soc/io_mux_reg.h @@ -130,14 +130,6 @@ extern "C" { #define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) -#define SPI_HD_GPIO_NUM 20 -#define SPI_WP_GPIO_NUM 18 -#define SPI_CS0_GPIO_NUM 16 -#define SPI_CLK_GPIO_NUM 21 -#define SPI_D_GPIO_NUM 22 -#define SPI_Q_GPIO_NUM 17 -#define SPI_CS1_GPIO_NUM 15 - #define USB_INT_PHY0_DM_GPIO_NUM 13 #define USB_INT_PHY0_DP_GPIO_NUM 14 diff --git a/components/soc/esp32c6/register/soc/io_mux_reg.h b/components/soc/esp32c6/register/soc/io_mux_reg.h index 8769a66dae..5b95b56ea2 100644 --- a/components/soc/esp32c6/register/soc/io_mux_reg.h +++ b/components/soc/esp32c6/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -129,13 +129,6 @@ #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -#define SPI_HD_GPIO_NUM 28 -#define SPI_WP_GPIO_NUM 26 -#define SPI_CS0_GPIO_NUM 24 -#define SPI_CLK_GPIO_NUM 29 -#define SPI_D_GPIO_NUM 30 -#define SPI_Q_GPIO_NUM 25 - #define SD_CLK_GPIO_NUM 19 #define SD_CMD_GPIO_NUM 18 #define SD_DATA0_GPIO_NUM 20 diff --git a/components/soc/esp32h2/register/soc/io_mux_reg.h b/components/soc/esp32h2/register/soc/io_mux_reg.h index a765ae92db..d71e6d3e7c 100644 --- a/components/soc/esp32h2/register/soc/io_mux_reg.h +++ b/components/soc/esp32h2/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -148,13 +148,6 @@ #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -#define SPI_HD_GPIO_NUM 18 -#define SPI_WP_GPIO_NUM 17 -#define SPI_CS0_GPIO_NUM 15 -#define SPI_CLK_GPIO_NUM 19 -#define SPI_D_GPIO_NUM 20 -#define SPI_Q_GPIO_NUM 16 - #define USB_INT_PHY0_DM_GPIO_NUM 26 #define USB_INT_PHY0_DP_GPIO_NUM 27 diff --git a/components/soc/esp32p4/emac_periph.c b/components/soc/esp32p4/emac_periph.c index 9d21db47bc..19096f6f13 100644 --- a/components/soc/esp32p4/emac_periph.c +++ b/components/soc/esp32p4/emac_periph.c @@ -16,9 +16,9 @@ const emac_io_info_t emac_io_idx = { .mii_tx_clk_i_idx = EMAC_TX_CLK_PAD_IN_IDX, .mii_tx_en_o_idx = EMAC_PHY_TXEN_PAD_OUT_IDX, .mii_txd0_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX, - .mii_txd1_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX, - .mii_txd2_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX, - .mii_txd3_o_idx = EMAC_PHY_TXD0_PAD_OUT_IDX, + .mii_txd1_o_idx = EMAC_PHY_TXD1_PAD_OUT_IDX, + .mii_txd2_o_idx = EMAC_PHY_TXD2_PAD_OUT_IDX, + .mii_txd3_o_idx = EMAC_PHY_TXD3_PAD_OUT_IDX, .mii_rx_clk_i_idx = EMAC_RX_CLK_PAD_IN_IDX, .mii_rx_dv_i_idx = EMAC_PHY_RXDV_PAD_IN_IDX, .mii_rxd0_i_idx = EMAC_PHY_RXD0_PAD_IN_IDX, diff --git a/components/soc/esp32p4/include/soc/gpio_sig_map.h b/components/soc/esp32p4/include/soc/gpio_sig_map.h index 00aba01a22..756baafe93 100644 --- a/components/soc/esp32p4/include/soc/gpio_sig_map.h +++ b/components/soc/esp32p4/include/soc/gpio_sig_map.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -196,13 +196,9 @@ #define PWM1_SYNC2_PAD_IN_IDX 100 #define PWM1_CH2_B_PAD_OUT_IDX 100 #define PWM1_F0_PAD_IN_IDX 101 -#define ADP_CHRG_PAD_OUT_IDX 101 #define PWM1_F1_PAD_IN_IDX 102 -#define ADP_DISCHRG_PAD_OUT_IDX 102 #define PWM1_F2_PAD_IN_IDX 103 -#define ADP_PRB_EN_PAD_OUT_IDX 103 #define PWM1_CAP0_PAD_IN_IDX 104 -#define ADP_SNS_EN_PAD_OUT_IDX 104 #define PWM1_CAP1_PAD_IN_IDX 105 #define TWAI0_STANDBY_PAD_OUT_IDX 105 #define PWM1_CAP2_PAD_IN_IDX 106 @@ -224,7 +220,6 @@ #define USB_SRP_SESSEND_PAD_IN_IDX 114 #define USB_OTG11_DRVVBUS_PAD_OUT_IDX 114 #define USB_SRP_CHRGVBUS_PAD_OUT_IDX 115 -#define OTG_DRVVBUS_PAD_OUT_IDX 116 #define ULPI_CLK_PAD_IN_IDX 117 #define RNG_CHAIN_CLK_PAD_OUT_IDX 117 #define USB_HSPHY_REFCLK_IN_IDX 118 @@ -260,9 +255,7 @@ #define I3C_SLV_SCL_PAD_OUT_IDX 136 #define I3C_SLV_SDA_PAD_IN_IDX 137 #define I3C_SLV_SDA_PAD_OUT_IDX 137 -#define ADP_PRB_PAD_IN_IDX 138 #define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX 138 -#define ADP_SNS_PAD_IN_IDX 139 #define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX 139 #define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX 140 #define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX 140 @@ -458,13 +451,13 @@ #define CORE_GPIO_IN_PAD_IN27_IDX 241 #define CORE_GPIO_OUT_PAD_OUT27_IDX 241 #define CORE_GPIO_IN_PAD_IN28_IDX 242 -#define CORE_GPIO_OUT_PAD_OUT28_IDX 242 +#define PARLIO_TX_CS_PAD_OUT_IDX 242 #define CORE_GPIO_IN_PAD_IN29_IDX 243 -#define CORE_GPIO_OUT_PAD_OUT29_IDX 243 +#define EMAC_PTP_PPS_PAD_OUT_IDX 243 #define CORE_GPIO_IN_PAD_IN30_IDX 244 -#define CORE_GPIO_OUT_PAD_OUT30_IDX 244 +#define ANA_COMP0_OUT_IDX 244 #define CORE_GPIO_IN_PAD_IN31_IDX 245 -#define CORE_GPIO_OUT_PAD_OUT31_IDX 245 +#define ANA_COMP1_OUT_IDX 245 #define RMT_SIG_PAD_IN0_IDX 246 #define RMT_SIG_PAD_OUT0_IDX 246 #define RMT_SIG_PAD_IN1_IDX 247 @@ -485,4 +478,5 @@ #define SIG_IN_FUNC254_IDX 254 #define SIG_IN_FUNC255_IDX 255 #define SIG_IN_FUNC255_IDX 255 +// version date 230403 #define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32p4/register/hw_ver1/soc/io_mux_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/io_mux_reg.h index 4b644dc9cc..18c8e6decd 100644 --- a/components/soc/esp32p4/register/hw_ver1/soc/io_mux_reg.h +++ b/components/soc/esp32p4/register/hw_ver1/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -153,23 +153,6 @@ #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -// TODO: IDF-7499, IDF-7495 -// SPI pins defined here are all wrong. On P4, these pins are individual pins, don't use normal GPIO pins anymore. -// Please check iomux_mspi_pin_struct/reg.h -#include "soc/gpio_num.h" -#define SPI_CS1_GPIO_NUM GPIO_NUM_MAX -#define SPI_HD_GPIO_NUM GPIO_NUM_MAX -#define SPI_WP_GPIO_NUM GPIO_NUM_MAX -#define SPI_CS0_GPIO_NUM GPIO_NUM_MAX -#define SPI_CLK_GPIO_NUM GPIO_NUM_MAX -#define SPI_Q_GPIO_NUM GPIO_NUM_MAX -#define SPI_D_GPIO_NUM GPIO_NUM_MAX -#define SPI_D4_GPIO_NUM GPIO_NUM_MAX -#define SPI_D5_GPIO_NUM GPIO_NUM_MAX -#define SPI_D6_GPIO_NUM GPIO_NUM_MAX -#define SPI_D7_GPIO_NUM GPIO_NUM_MAX -#define SPI_DQS_GPIO_NUM GPIO_NUM_MAX - #define SD_CLK_GPIO_NUM 43 #define SD_CMD_GPIO_NUM 44 #define SD_DATA0_GPIO_NUM 39 diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h deleted file mode 100644 index a3b88516fa..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/gpio_ext_eco5_struct.h +++ /dev/null @@ -1,772 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: SDM Configure Registers */ -/** Type of sigmadeltan register - * Duty Cycle Configure Register of SDMn - */ -typedef union { - struct { - /** sdn_in : R/W; bitpos: [7:0]; default: 0; - * This field is used to configure the duty cycle of sigma delta modulation output. - */ - uint32_t sdn_in:8; - /** sdn_prescale : R/W; bitpos: [15:8]; default: 255; - * This field is used to set a divider value to divide APB clock. - */ - uint32_t sdn_prescale:8; - uint32_t reserved_16:16; - }; - uint32_t val; -} gpiosd_sigmadeltan_reg_t; - -/** Type of sigmadelta_misc register - * MISC Register - */ -typedef union { - struct { - uint32_t reserved_0:30; - /** function_clk_en : R/W; bitpos: [30]; default: 0; - * Clock enable bit of sigma delta modulation. - */ - uint32_t function_clk_en:1; - /** spi_swap : R/W; bitpos: [31]; default: 0; - * Reserved. - */ - uint32_t spi_swap:1; - }; - uint32_t val; -} gpiosd_sigmadelta_misc_reg_t; - - -/** Group: Glitch filter Configure Registers */ -/** Type of glitch_filter_chn register - * Glitch Filter Configure Register of Channeln - */ -typedef union { - struct { - /** filter_ch0_en : R/W; bitpos: [0]; default: 0; - * Glitch Filter channel enable bit. - */ - uint32_t filter_ch0_en:1; - /** filter_ch0_input_io_num : R/W; bitpos: [6:1]; default: 0; - * Glitch Filter input io number. - */ - uint32_t filter_ch0_input_io_num:6; - /** filter_ch0_window_thres : R/W; bitpos: [12:7]; default: 0; - * Glitch Filter window threshold. - */ - uint32_t filter_ch0_window_thres:6; - /** filter_ch0_window_width : R/W; bitpos: [18:13]; default: 0; - * Glitch Filter window width. - */ - uint32_t filter_ch0_window_width:6; - uint32_t reserved_19:13; - }; - uint32_t val; -} gpiosd_glitch_filter_chn_reg_t; - - -/** Group: Etm Configure Registers */ -/** Type of etm_event_chn_cfg register - * Etm Config register of Channeln - */ -typedef union { - struct { - /** etm_ch0_event_sel : R/W; bitpos: [5:0]; default: 0; - * Etm event channel select gpio. - */ - uint32_t etm_ch0_event_sel:6; - uint32_t reserved_6:1; - /** etm_ch0_event_en : R/W; bitpos: [7]; default: 0; - * Etm event send enable bit. - */ - uint32_t etm_ch0_event_en:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} gpiosd_etm_event_chn_cfg_reg_t; - -/** Type of etm_task_p0_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio0_en:1; - /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio0_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio1_en:1; - /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio1_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio2_en:1; - /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio2_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio3_en:1; - /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio3_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p0_cfg_reg_t; - -/** Type of etm_task_p1_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio4_en:1; - /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio4_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio5_en:1; - /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio5_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio6_en:1; - /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio6_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio7_en:1; - /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio7_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p1_cfg_reg_t; - -/** Type of etm_task_p2_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio8_en:1; - /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio8_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio9_en:1; - /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio9_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio10_en:1; - /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio10_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio11_en:1; - /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio11_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p2_cfg_reg_t; - -/** Type of etm_task_p3_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio12_en:1; - /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio12_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio13_en:1; - /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio13_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio14_en:1; - /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio14_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio15_en:1; - /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio15_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p3_cfg_reg_t; - -/** Type of etm_task_p4_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio16_en:1; - /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio16_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio17_en:1; - /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio17_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio18_en:1; - /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio18_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio19_en:1; - /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio19_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p4_cfg_reg_t; - -/** Type of etm_task_p5_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio20_en:1; - /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio20_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio21_en:1; - /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio21_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio22_en:1; - /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio22_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio23_en:1; - /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio23_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p5_cfg_reg_t; - -/** Type of etm_task_p6_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio24_en:1; - /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio24_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio25_en:1; - /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio25_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio26_en:1; - /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio26_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio27_en:1; - /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio27_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p6_cfg_reg_t; - -/** Type of etm_task_p7_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio28_en:1; - /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio28_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio29_en:1; - /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio29_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio30_en:1; - /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio30_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio31_en:1; - /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio31_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p7_cfg_reg_t; - -/** Type of etm_task_p8_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio32_en:1; - /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio32_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio33_en:1; - /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio33_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio34_en:1; - /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio34_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio35_en:1; - /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio35_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p8_cfg_reg_t; - -/** Type of etm_task_p9_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio36_en:1; - /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio36_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio37_en:1; - /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio37_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio38_en:1; - /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio38_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio39_en:1; - /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio39_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p9_cfg_reg_t; - -/** Type of etm_task_p10_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio40_en:1; - /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio40_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio41_en:1; - /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio41_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio42_en:1; - /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio42_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio43_en:1; - /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio43_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p10_cfg_reg_t; - -/** Type of etm_task_p11_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio44_en:1; - /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio44_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio45_en:1; - /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio45_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio46_en:1; - /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio46_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio47_en:1; - /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio47_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p11_cfg_reg_t; - -/** Type of etm_task_p12_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio48_en:1; - /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio48_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio49_en:1; - /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio49_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio50_en:1; - /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio50_sel:3; - uint32_t reserved_20:4; - /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio51_en:1; - /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio51_sel:3; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_etm_task_p12_cfg_reg_t; - -/** Type of etm_task_p13_cfg register - * Etm Configure Register to decide which GPIO been chosen - */ -typedef union { - struct { - /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio52_en:1; - /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio52_sel:3; - uint32_t reserved_4:4; - /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio53_en:1; - /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio53_sel:3; - uint32_t reserved_12:4; - /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0; - * Enable bit of GPIO response etm task. - */ - uint32_t etm_task_gpio54_en:1; - /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0; - * GPIO choose a etm task channel. - */ - uint32_t etm_task_gpio54_sel:3; - uint32_t reserved_20:12; - }; - uint32_t val; -} gpiosd_etm_task_p13_cfg_reg_t; - - -/** Group: Version Register */ -/** Type of version register - * Version Control Register - */ -typedef union { - struct { - /** gpio_sd_date : R/W; bitpos: [27:0]; default: 35663952; - * Version control register. - */ - uint32_t gpio_sd_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} gpiosd_version_reg_t; - - -typedef struct { - volatile gpiosd_sigmadeltan_reg_t sigmadeltan[8]; - uint32_t reserved_020; - volatile gpiosd_sigmadelta_misc_reg_t sigmadelta_misc; - uint32_t reserved_028[2]; - volatile gpiosd_glitch_filter_chn_reg_t glitch_filter_chn[8]; - uint32_t reserved_050[4]; - volatile gpiosd_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; - uint32_t reserved_080[8]; - volatile gpiosd_etm_task_p0_cfg_reg_t etm_task_p0_cfg; - volatile gpiosd_etm_task_p1_cfg_reg_t etm_task_p1_cfg; - volatile gpiosd_etm_task_p2_cfg_reg_t etm_task_p2_cfg; - volatile gpiosd_etm_task_p3_cfg_reg_t etm_task_p3_cfg; - volatile gpiosd_etm_task_p4_cfg_reg_t etm_task_p4_cfg; - volatile gpiosd_etm_task_p5_cfg_reg_t etm_task_p5_cfg; - volatile gpiosd_etm_task_p6_cfg_reg_t etm_task_p6_cfg; - volatile gpiosd_etm_task_p7_cfg_reg_t etm_task_p7_cfg; - volatile gpiosd_etm_task_p8_cfg_reg_t etm_task_p8_cfg; - volatile gpiosd_etm_task_p9_cfg_reg_t etm_task_p9_cfg; - volatile gpiosd_etm_task_p10_cfg_reg_t etm_task_p10_cfg; - volatile gpiosd_etm_task_p11_cfg_reg_t etm_task_p11_cfg; - volatile gpiosd_etm_task_p12_cfg_reg_t etm_task_p12_cfg; - volatile gpiosd_etm_task_p13_cfg_reg_t etm_task_p13_cfg; - uint32_t reserved_0d8[9]; - volatile gpiosd_version_reg_t version; -} gpiosd_dev_t; - -extern gpiosd_dev_t GPIO; - -#ifndef __cplusplus -_Static_assert(sizeof(gpiosd_dev_t) == 0x100, "Invalid size of gpiosd_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h b/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h deleted file mode 100644 index 65c4a503c0..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/gpio_sig_map.h +++ /dev/null @@ -1,483 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#define SD_CARD_CCLK_2_PAD_OUT_IDX 0 -#define SD_CARD_CCMD_2_PAD_IN_IDX 1 -#define SD_CARD_CCMD_2_PAD_OUT_IDX 1 -#define SD_CARD_CDATA0_2_PAD_IN_IDX 2 -#define SD_CARD_CDATA0_2_PAD_OUT_IDX 2 -#define SD_CARD_CDATA1_2_PAD_IN_IDX 3 -#define SD_CARD_CDATA1_2_PAD_OUT_IDX 3 -#define SD_CARD_CDATA2_2_PAD_IN_IDX 4 -#define SD_CARD_CDATA2_2_PAD_OUT_IDX 4 -#define SD_CARD_CDATA3_2_PAD_IN_IDX 5 -#define SD_CARD_CDATA3_2_PAD_OUT_IDX 5 -#define SD_CARD_CDATA4_2_PAD_IN_IDX 6 -#define SD_CARD_CDATA4_2_PAD_OUT_IDX 6 -#define SD_CARD_CDATA5_2_PAD_IN_IDX 7 -#define SD_CARD_CDATA5_2_PAD_OUT_IDX 7 -#define SD_CARD_CDATA6_2_PAD_IN_IDX 8 -#define SD_CARD_CDATA6_2_PAD_OUT_IDX 8 -#define SD_CARD_CDATA7_2_PAD_IN_IDX 9 -#define SD_CARD_CDATA7_2_PAD_OUT_IDX 9 -#define UART0_RXD_PAD_IN_IDX 10 -#define UART0_TXD_PAD_OUT_IDX 10 -#define UART0_CTS_PAD_IN_IDX 11 -#define UART0_RTS_PAD_OUT_IDX 11 -#define UART0_DSR_PAD_IN_IDX 12 -#define UART0_DTR_PAD_OUT_IDX 12 -#define UART1_RXD_PAD_IN_IDX 13 -#define UART1_TXD_PAD_OUT_IDX 13 -#define UART1_CTS_PAD_IN_IDX 14 -#define UART1_RTS_PAD_OUT_IDX 14 -#define UART1_DSR_PAD_IN_IDX 15 -#define UART1_DTR_PAD_OUT_IDX 15 -#define UART2_RXD_PAD_IN_IDX 16 -#define UART2_TXD_PAD_OUT_IDX 16 -#define UART2_CTS_PAD_IN_IDX 17 -#define UART2_RTS_PAD_OUT_IDX 17 -#define UART2_DSR_PAD_IN_IDX 18 -#define UART2_DTR_PAD_OUT_IDX 18 -#define UART3_RXD_PAD_IN_IDX 19 -#define UART3_TXD_PAD_OUT_IDX 19 -#define UART3_CTS_PAD_IN_IDX 20 -#define UART3_RTS_PAD_OUT_IDX 20 -#define UART3_DSR_PAD_IN_IDX 21 -#define UART3_DTR_PAD_OUT_IDX 21 -#define UART4_RXD_PAD_IN_IDX 22 -#define UART4_TXD_PAD_OUT_IDX 22 -#define UART4_CTS_PAD_IN_IDX 23 -#define UART4_RTS_PAD_OUT_IDX 23 -#define UART4_DSR_PAD_IN_IDX 24 -#define UART4_DTR_PAD_OUT_IDX 24 -#define I2S0_O_BCK_PAD_IN_IDX 25 -#define I2S0_O_BCK_PAD_OUT_IDX 25 -#define I2S0_MCLK_PAD_IN_IDX 26 -#define I2S0_MCLK_PAD_OUT_IDX 26 -#define I2S0_O_WS_PAD_IN_IDX 27 -#define I2S0_O_WS_PAD_OUT_IDX 27 -#define I2S0_I_SD_PAD_IN_IDX 28 -#define I2S0_O_SD_PAD_OUT_IDX 28 -#define I2S0_I_BCK_PAD_IN_IDX 29 -#define I2S0_I_BCK_PAD_OUT_IDX 29 -#define I2S0_I_WS_PAD_IN_IDX 30 -#define I2S0_I_WS_PAD_OUT_IDX 30 -#define I2S1_O_BCK_PAD_IN_IDX 31 -#define I2S1_O_BCK_PAD_OUT_IDX 31 -#define I2S1_MCLK_PAD_IN_IDX 32 -#define I2S1_MCLK_PAD_OUT_IDX 32 -#define I2S1_O_WS_PAD_IN_IDX 33 -#define I2S1_O_WS_PAD_OUT_IDX 33 -#define I2S1_I_SD_PAD_IN_IDX 34 -#define I2S1_O_SD_PAD_OUT_IDX 34 -#define I2S1_I_BCK_PAD_IN_IDX 35 -#define I2S1_I_BCK_PAD_OUT_IDX 35 -#define I2S1_I_WS_PAD_IN_IDX 36 -#define I2S1_I_WS_PAD_OUT_IDX 36 -#define I2S2_O_BCK_PAD_IN_IDX 37 -#define I2S2_O_BCK_PAD_OUT_IDX 37 -#define I2S2_MCLK_PAD_IN_IDX 38 -#define I2S2_MCLK_PAD_OUT_IDX 38 -#define I2S2_O_WS_PAD_IN_IDX 39 -#define I2S2_O_WS_PAD_OUT_IDX 39 -#define I2S2_I_SD_PAD_IN_IDX 40 -#define I2S2_O_SD_PAD_OUT_IDX 40 -#define I2S2_I_BCK_PAD_IN_IDX 41 -#define I2S2_I_BCK_PAD_OUT_IDX 41 -#define I2S2_I_WS_PAD_IN_IDX 42 -#define I2S2_I_WS_PAD_OUT_IDX 42 -#define I2S0_I_SD1_PAD_IN_IDX 43 -#define I2S0_O_SD1_PAD_OUT_IDX 43 -#define I2S0_I_SD2_PAD_IN_IDX 44 -#define SPI2_DQS_PAD_OUT_IDX 44 -#define I2S0_I_SD3_PAD_IN_IDX 45 -#define SPI3_CS2_PAD_OUT_IDX 45 -#define SPI3_CS1_PAD_OUT_IDX 46 -#define SPI3_CK_PAD_IN_IDX 47 -#define SPI3_CK_PAD_OUT_IDX 47 -#define SPI3_Q_PAD_IN_IDX 48 -#define SPI3_QO_PAD_OUT_IDX 48 -#define SPI3_D_PAD_IN_IDX 49 -#define SPI3_D_PAD_OUT_IDX 49 -#define SPI3_HOLD_PAD_IN_IDX 50 -#define SPI3_HOLD_PAD_OUT_IDX 50 -#define SPI3_WP_PAD_IN_IDX 51 -#define SPI3_WP_PAD_OUT_IDX 51 -#define SPI3_CS_PAD_IN_IDX 52 -#define SPI3_CS_PAD_OUT_IDX 52 -#define SPI2_CK_PAD_IN_IDX 53 -#define SPI2_CK_PAD_OUT_IDX 53 -#define SPI2_Q_PAD_IN_IDX 54 -#define SPI2_Q_PAD_OUT_IDX 54 -#define SPI2_D_PAD_IN_IDX 55 -#define SPI2_D_PAD_OUT_IDX 55 -#define SPI2_HOLD_PAD_IN_IDX 56 -#define SPI2_HOLD_PAD_OUT_IDX 56 -#define SPI2_WP_PAD_IN_IDX 57 -#define SPI2_WP_PAD_OUT_IDX 57 -#define SPI2_IO4_PAD_IN_IDX 58 -#define SPI2_IO4_PAD_OUT_IDX 58 -#define SPI2_IO5_PAD_IN_IDX 59 -#define SPI2_IO5_PAD_OUT_IDX 59 -#define SPI2_IO6_PAD_IN_IDX 60 -#define SPI2_IO6_PAD_OUT_IDX 60 -#define SPI2_IO7_PAD_IN_IDX 61 -#define SPI2_IO7_PAD_OUT_IDX 61 -#define SPI2_CS_PAD_IN_IDX 62 -#define SPI2_CS_PAD_OUT_IDX 62 -#define PCNT_RST_PAD_IN0_IDX 63 -#define SPI2_CS1_PAD_OUT_IDX 63 -#define PCNT_RST_PAD_IN1_IDX 64 -#define SPI2_CS2_PAD_OUT_IDX 64 -#define PCNT_RST_PAD_IN2_IDX 65 -#define SPI2_CS3_PAD_OUT_IDX 65 -#define PCNT_RST_PAD_IN3_IDX 66 -#define SPI2_CS4_PAD_OUT_IDX 66 -#define SPI2_CS5_PAD_OUT_IDX 67 -#define I2C0_SCL_PAD_IN_IDX 68 -#define I2C0_SCL_PAD_OUT_IDX 68 -#define I2C0_SDA_PAD_IN_IDX 69 -#define I2C0_SDA_PAD_OUT_IDX 69 -#define I2C1_SCL_PAD_IN_IDX 70 -#define I2C1_SCL_PAD_OUT_IDX 70 -#define I2C1_SDA_PAD_IN_IDX 71 -#define I2C1_SDA_PAD_OUT_IDX 71 -#define GPIO_SD0_OUT_IDX 72 -#define GPIO_SD1_OUT_IDX 73 -#define UART0_SLP_CLK_PAD_IN_IDX 74 -#define GPIO_SD2_OUT_IDX 74 -#define UART1_SLP_CLK_PAD_IN_IDX 75 -#define GPIO_SD3_OUT_IDX 75 -#define UART2_SLP_CLK_PAD_IN_IDX 76 -#define GPIO_SD4_OUT_IDX 76 -#define UART3_SLP_CLK_PAD_IN_IDX 77 -#define GPIO_SD5_OUT_IDX 77 -#define UART4_SLP_CLK_PAD_IN_IDX 78 -#define GPIO_SD6_OUT_IDX 78 -#define GPIO_SD7_OUT_IDX 79 -#define TWAI0_RX_PAD_IN_IDX 80 -#define TWAI0_TX_PAD_OUT_IDX 80 -#define TWAI0_BUS_OFF_ON_PAD_OUT_IDX 81 -#define TWAI0_CLKOUT_PAD_OUT_IDX 82 -#define TWAI1_RX_PAD_IN_IDX 83 -#define TWAI1_TX_PAD_OUT_IDX 83 -#define TWAI1_BUS_OFF_ON_PAD_OUT_IDX 84 -#define TWAI1_CLKOUT_PAD_OUT_IDX 85 -#define TWAI2_RX_PAD_IN_IDX 86 -#define TWAI2_TX_PAD_OUT_IDX 86 -#define TWAI2_BUS_OFF_ON_PAD_OUT_IDX 87 -#define TWAI2_CLKOUT_PAD_OUT_IDX 88 -#define PWM0_SYNC0_PAD_IN_IDX 89 -#define PWM0_CH0_A_PAD_OUT_IDX 89 -#define PWM0_SYNC1_PAD_IN_IDX 90 -#define PWM0_CH0_B_PAD_OUT_IDX 90 -#define PWM0_SYNC2_PAD_IN_IDX 91 -#define PWM0_CH1_A_PAD_OUT_IDX 91 -#define PWM0_F0_PAD_IN_IDX 92 -#define PWM0_CH1_B_PAD_OUT_IDX 92 -#define PWM0_F1_PAD_IN_IDX 93 -#define PWM0_CH2_A_PAD_OUT_IDX 93 -#define PWM0_F2_PAD_IN_IDX 94 -#define PWM0_CH2_B_PAD_OUT_IDX 94 -#define PWM0_CAP0_PAD_IN_IDX 95 -#define PWM1_CH0_A_PAD_OUT_IDX 95 -#define PWM0_CAP1_PAD_IN_IDX 96 -#define PWM1_CH0_B_PAD_OUT_IDX 96 -#define PWM0_CAP2_PAD_IN_IDX 97 -#define PWM1_CH1_A_PAD_OUT_IDX 97 -#define PWM1_SYNC0_PAD_IN_IDX 98 -#define PWM1_CH1_B_PAD_OUT_IDX 98 -#define PWM1_SYNC1_PAD_IN_IDX 99 -#define PWM1_CH2_A_PAD_OUT_IDX 99 -#define PWM1_SYNC2_PAD_IN_IDX 100 -#define PWM1_CH2_B_PAD_OUT_IDX 100 -#define PWM1_F0_PAD_IN_IDX 101 -#define PWM1_F1_PAD_IN_IDX 102 -#define PWM1_F2_PAD_IN_IDX 103 -#define PWM1_CAP0_PAD_IN_IDX 104 -#define PWM1_CAP1_PAD_IN_IDX 105 -#define TWAI0_STANDBY_PAD_OUT_IDX 105 -#define PWM1_CAP2_PAD_IN_IDX 106 -#define TWAI1_STANDBY_PAD_OUT_IDX 106 -#define GMII_MDI_PAD_IN_IDX 107 -#define TWAI2_STANDBY_PAD_OUT_IDX 107 -#define GMAC_PHY_COL_PAD_IN_IDX 108 -#define GMII_MDC_PAD_OUT_IDX 108 -#define GMAC_PHY_CRS_PAD_IN_IDX 109 -#define GMII_MDO_PAD_OUT_IDX 109 -#define USB_OTG11_IDDIG_PAD_IN_IDX 110 -#define USB_SRP_DISCHRGVBUS_PAD_OUT_IDX 110 -#define USB_OTG11_AVALID_PAD_IN_IDX 111 -#define USB_OTG11_IDPULLUP_PAD_OUT_IDX 111 -#define USB_SRP_BVALID_PAD_IN_IDX 112 -#define USB_OTG11_DPPULLDOWN_PAD_OUT_IDX 112 -#define USB_OTG11_VBUSVALID_PAD_IN_IDX 113 -#define USB_OTG11_DMPULLDOWN_PAD_OUT_IDX 113 -#define USB_SRP_SESSEND_PAD_IN_IDX 114 -#define USB_OTG11_DRVVBUS_PAD_OUT_IDX 114 -#define USB_SRP_CHRGVBUS_PAD_OUT_IDX 115 -#define ULPI_CLK_PAD_IN_IDX 117 -#define RNG_CHAIN_CLK_PAD_OUT_IDX 117 -#define USB_HSPHY_REFCLK_IN_IDX 118 -#define HP_PROBE_TOP_OUT0_IDX 118 -#define HP_PROBE_TOP_OUT1_IDX 119 -#define HP_PROBE_TOP_OUT2_IDX 120 -#define HP_PROBE_TOP_OUT3_IDX 121 -#define HP_PROBE_TOP_OUT4_IDX 122 -#define HP_PROBE_TOP_OUT5_IDX 123 -#define HP_PROBE_TOP_OUT6_IDX 124 -#define HP_PROBE_TOP_OUT7_IDX 125 -#define SD_CARD_DETECT_N_1_PAD_IN_IDX 126 -#define LEDC_LS_SIG_OUT_PAD_OUT0_IDX 126 -#define SD_CARD_DETECT_N_2_PAD_IN_IDX 127 -#define LEDC_LS_SIG_OUT_PAD_OUT1_IDX 127 -#define SD_CARD_INT_N_1_PAD_IN_IDX 128 -#define LEDC_LS_SIG_OUT_PAD_OUT2_IDX 128 -#define SD_CARD_INT_N_2_PAD_IN_IDX 129 -#define LEDC_LS_SIG_OUT_PAD_OUT3_IDX 129 -#define SD_CARD_WRITE_PRT_1_PAD_IN_IDX 130 -#define LEDC_LS_SIG_OUT_PAD_OUT4_IDX 130 -#define SD_CARD_WRITE_PRT_2_PAD_IN_IDX 131 -#define LEDC_LS_SIG_OUT_PAD_OUT5_IDX 131 -#define SD_DATA_STROBE_1_PAD_IN_IDX 132 -#define LEDC_LS_SIG_OUT_PAD_OUT6_IDX 132 -#define SD_DATA_STROBE_2_PAD_IN_IDX 133 -#define LEDC_LS_SIG_OUT_PAD_OUT7_IDX 133 -#define I3C_MST_SCL_PAD_IN_IDX 134 -#define I3C_MST_SCL_PAD_OUT_IDX 134 -#define I3C_MST_SDA_PAD_IN_IDX 135 -#define I3C_MST_SDA_PAD_OUT_IDX 135 -#define I3C_SLV_SCL_PAD_IN_IDX 136 -#define I3C_SLV_SCL_PAD_OUT_IDX 136 -#define I3C_SLV_SDA_PAD_IN_IDX 137 -#define I3C_SLV_SDA_PAD_OUT_IDX 137 -#define I3C_MST_SCL_PULLUP_EN_PAD_OUT_IDX 138 -#define I3C_MST_SDA_PULLUP_EN_PAD_OUT_IDX 139 -#define USB_JTAG_TDO_BRIDGE_PAD_IN_IDX 140 -#define USB_JTAG_TDI_BRIDGE_PAD_OUT_IDX 140 -#define PCNT_SIG_CH0_PAD_IN0_IDX 141 -#define USB_JTAG_TMS_BRIDGE_PAD_OUT_IDX 141 -#define PCNT_SIG_CH0_PAD_IN1_IDX 142 -#define USB_JTAG_TCK_BRIDGE_PAD_OUT_IDX 142 -#define PCNT_SIG_CH0_PAD_IN2_IDX 143 -#define USB_JTAG_TRST_BRIDGE_PAD_OUT_IDX 143 -#define PCNT_SIG_CH0_PAD_IN3_IDX 144 -#define LCD_CS_PAD_OUT_IDX 144 -#define PCNT_SIG_CH1_PAD_IN0_IDX 145 -#define LCD_DC_PAD_OUT_IDX 145 -#define PCNT_SIG_CH1_PAD_IN1_IDX 146 -#define SD_RST_N_1_PAD_OUT_IDX 146 -#define PCNT_SIG_CH1_PAD_IN2_IDX 147 -#define SD_RST_N_2_PAD_OUT_IDX 147 -#define PCNT_SIG_CH1_PAD_IN3_IDX 148 -#define SD_CCMD_OD_PULLUP_EN_N_PAD_OUT_IDX 148 -#define PCNT_CTRL_CH0_PAD_IN0_IDX 149 -#define LCD_PCLK_PAD_OUT_IDX 149 -#define PCNT_CTRL_CH0_PAD_IN1_IDX 150 -#define CAM_CLK_PAD_OUT_IDX 150 -#define PCNT_CTRL_CH0_PAD_IN2_IDX 151 -#define LCD_H_ENABLE_PAD_OUT_IDX 151 -#define PCNT_CTRL_CH0_PAD_IN3_IDX 152 -#define LCD_H_SYNC_PAD_OUT_IDX 152 -#define PCNT_CTRL_CH1_PAD_IN0_IDX 153 -#define LCD_V_SYNC_PAD_OUT_IDX 153 -#define PCNT_CTRL_CH1_PAD_IN1_IDX 154 -#define LCD_DATA_OUT_PAD_OUT0_IDX 154 -#define PCNT_CTRL_CH1_PAD_IN2_IDX 155 -#define LCD_DATA_OUT_PAD_OUT1_IDX 155 -#define PCNT_CTRL_CH1_PAD_IN3_IDX 156 -#define LCD_DATA_OUT_PAD_OUT2_IDX 156 -#define LCD_DATA_OUT_PAD_OUT3_IDX 157 -#define CAM_PCLK_PAD_IN_IDX 158 -#define LCD_DATA_OUT_PAD_OUT4_IDX 158 -#define CAM_H_ENABLE_PAD_IN_IDX 159 -#define LCD_DATA_OUT_PAD_OUT5_IDX 159 -#define CAM_H_SYNC_PAD_IN_IDX 160 -#define LCD_DATA_OUT_PAD_OUT6_IDX 160 -#define CAM_V_SYNC_PAD_IN_IDX 161 -#define LCD_DATA_OUT_PAD_OUT7_IDX 161 -#define CAM_DATA_IN_PAD_IN0_IDX 162 -#define LCD_DATA_OUT_PAD_OUT8_IDX 162 -#define CAM_DATA_IN_PAD_IN1_IDX 163 -#define LCD_DATA_OUT_PAD_OUT9_IDX 163 -#define CAM_DATA_IN_PAD_IN2_IDX 164 -#define LCD_DATA_OUT_PAD_OUT10_IDX 164 -#define CAM_DATA_IN_PAD_IN3_IDX 165 -#define LCD_DATA_OUT_PAD_OUT11_IDX 165 -#define CAM_DATA_IN_PAD_IN4_IDX 166 -#define LCD_DATA_OUT_PAD_OUT12_IDX 166 -#define CAM_DATA_IN_PAD_IN5_IDX 167 -#define LCD_DATA_OUT_PAD_OUT13_IDX 167 -#define CAM_DATA_IN_PAD_IN6_IDX 168 -#define LCD_DATA_OUT_PAD_OUT14_IDX 168 -#define CAM_DATA_IN_PAD_IN7_IDX 169 -#define LCD_DATA_OUT_PAD_OUT15_IDX 169 -#define CAM_DATA_IN_PAD_IN8_IDX 170 -#define LCD_DATA_OUT_PAD_OUT16_IDX 170 -#define CAM_DATA_IN_PAD_IN9_IDX 171 -#define LCD_DATA_OUT_PAD_OUT17_IDX 171 -#define CAM_DATA_IN_PAD_IN10_IDX 172 -#define LCD_DATA_OUT_PAD_OUT18_IDX 172 -#define CAM_DATA_IN_PAD_IN11_IDX 173 -#define LCD_DATA_OUT_PAD_OUT19_IDX 173 -#define CAM_DATA_IN_PAD_IN12_IDX 174 -#define LCD_DATA_OUT_PAD_OUT20_IDX 174 -#define CAM_DATA_IN_PAD_IN13_IDX 175 -#define LCD_DATA_OUT_PAD_OUT21_IDX 175 -#define CAM_DATA_IN_PAD_IN14_IDX 176 -#define LCD_DATA_OUT_PAD_OUT22_IDX 176 -#define CAM_DATA_IN_PAD_IN15_IDX 177 -#define LCD_DATA_OUT_PAD_OUT23_IDX 177 -#define GMAC_PHY_RXDV_PAD_IN_IDX 178 -#define GMAC_PHY_TXEN_PAD_OUT_IDX 178 -#define GMAC_PHY_RXD0_PAD_IN_IDX 179 -#define GMAC_PHY_TXD0_PAD_OUT_IDX 179 -#define GMAC_PHY_RXD1_PAD_IN_IDX 180 -#define GMAC_PHY_TXD1_PAD_OUT_IDX 180 -#define GMAC_PHY_RXD2_PAD_IN_IDX 181 -#define GMAC_PHY_TXD2_PAD_OUT_IDX 181 -#define GMAC_PHY_RXD3_PAD_IN_IDX 182 -#define GMAC_PHY_TXD3_PAD_OUT_IDX 182 -#define GMAC_PHY_RXER_PAD_IN_IDX 183 -#define GMAC_PHY_TXER_PAD_OUT_IDX 183 -#define GMAC_RX_CLK_PAD_IN_IDX 184 -#define DBG_CH0_CLK_IDX 184 -#define GMAC_TX_CLK_PAD_IN_IDX 185 -#define DBG_CH1_CLK_IDX 185 -#define PARLIO_RX_CLK_PAD_IN_IDX 186 -#define PARLIO_RX_CLK_PAD_OUT_IDX 186 -#define PARLIO_TX_CLK_PAD_IN_IDX 187 -#define PARLIO_TX_CLK_PAD_OUT_IDX 187 -#define PARLIO_RX_DATA0_PAD_IN_IDX 188 -#define PARLIO_TX_DATA0_PAD_OUT_IDX 188 -#define PARLIO_RX_DATA1_PAD_IN_IDX 189 -#define PARLIO_TX_DATA1_PAD_OUT_IDX 189 -#define PARLIO_RX_DATA2_PAD_IN_IDX 190 -#define PARLIO_TX_DATA2_PAD_OUT_IDX 190 -#define PARLIO_RX_DATA3_PAD_IN_IDX 191 -#define PARLIO_TX_DATA3_PAD_OUT_IDX 191 -#define PARLIO_RX_DATA4_PAD_IN_IDX 192 -#define PARLIO_TX_DATA4_PAD_OUT_IDX 192 -#define PARLIO_RX_DATA5_PAD_IN_IDX 193 -#define PARLIO_TX_DATA5_PAD_OUT_IDX 193 -#define PARLIO_RX_DATA6_PAD_IN_IDX 194 -#define PARLIO_TX_DATA6_PAD_OUT_IDX 194 -#define PARLIO_RX_DATA7_PAD_IN_IDX 195 -#define PARLIO_TX_DATA7_PAD_OUT_IDX 195 -#define PARLIO_RX_DATA8_PAD_IN_IDX 196 -#define PARLIO_TX_DATA8_PAD_OUT_IDX 196 -#define PARLIO_RX_DATA9_PAD_IN_IDX 197 -#define PARLIO_TX_DATA9_PAD_OUT_IDX 197 -#define PARLIO_RX_DATA10_PAD_IN_IDX 198 -#define PARLIO_TX_DATA10_PAD_OUT_IDX 198 -#define PARLIO_RX_DATA11_PAD_IN_IDX 199 -#define PARLIO_TX_DATA11_PAD_OUT_IDX 199 -#define PARLIO_RX_DATA12_PAD_IN_IDX 200 -#define PARLIO_TX_DATA12_PAD_OUT_IDX 200 -#define PARLIO_RX_DATA13_PAD_IN_IDX 201 -#define PARLIO_TX_DATA13_PAD_OUT_IDX 201 -#define PARLIO_RX_DATA14_PAD_IN_IDX 202 -#define PARLIO_TX_DATA14_PAD_OUT_IDX 202 -#define PARLIO_RX_DATA15_PAD_IN_IDX 203 -#define PARLIO_TX_DATA15_PAD_OUT_IDX 203 -#define HP_PROBE_TOP_OUT8_IDX 204 -#define HP_PROBE_TOP_OUT9_IDX 205 -#define HP_PROBE_TOP_OUT10_IDX 206 -#define HP_PROBE_TOP_OUT11_IDX 207 -#define HP_PROBE_TOP_OUT12_IDX 208 -#define HP_PROBE_TOP_OUT13_IDX 209 -#define HP_PROBE_TOP_OUT14_IDX 210 -#define HP_PROBE_TOP_OUT15_IDX 211 -#define CONSTANT0_PAD_OUT_IDX 212 -#define CONSTANT1_PAD_OUT_IDX 213 -#define CORE_GPIO_IN_PAD_IN0_IDX 214 -#define CORE_GPIO_OUT_PAD_OUT0_IDX 214 -#define CORE_GPIO_IN_PAD_IN1_IDX 215 -#define CORE_GPIO_OUT_PAD_OUT1_IDX 215 -#define CORE_GPIO_IN_PAD_IN2_IDX 216 -#define CORE_GPIO_OUT_PAD_OUT2_IDX 216 -#define CORE_GPIO_IN_PAD_IN3_IDX 217 -#define CORE_GPIO_OUT_PAD_OUT3_IDX 217 -#define CORE_GPIO_IN_PAD_IN4_IDX 218 -#define CORE_GPIO_OUT_PAD_OUT4_IDX 218 -#define CORE_GPIO_IN_PAD_IN5_IDX 219 -#define CORE_GPIO_OUT_PAD_OUT5_IDX 219 -#define CORE_GPIO_IN_PAD_IN6_IDX 220 -#define CORE_GPIO_OUT_PAD_OUT6_IDX 220 -#define CORE_GPIO_IN_PAD_IN7_IDX 221 -#define CORE_GPIO_OUT_PAD_OUT7_IDX 221 -#define CORE_GPIO_IN_PAD_IN8_IDX 222 -#define CORE_GPIO_OUT_PAD_OUT8_IDX 222 -#define CORE_GPIO_IN_PAD_IN9_IDX 223 -#define CORE_GPIO_OUT_PAD_OUT9_IDX 223 -#define CORE_GPIO_IN_PAD_IN10_IDX 224 -#define CORE_GPIO_OUT_PAD_OUT10_IDX 224 -#define CORE_GPIO_IN_PAD_IN11_IDX 225 -#define CORE_GPIO_OUT_PAD_OUT11_IDX 225 -#define CORE_GPIO_IN_PAD_IN12_IDX 226 -#define CORE_GPIO_OUT_PAD_OUT12_IDX 226 -#define CORE_GPIO_IN_PAD_IN13_IDX 227 -#define CORE_GPIO_OUT_PAD_OUT13_IDX 227 -#define CORE_GPIO_IN_PAD_IN14_IDX 228 -#define CORE_GPIO_OUT_PAD_OUT14_IDX 228 -#define CORE_GPIO_IN_PAD_IN15_IDX 229 -#define CORE_GPIO_OUT_PAD_OUT15_IDX 229 -#define CORE_GPIO_IN_PAD_IN16_IDX 230 -#define CORE_GPIO_OUT_PAD_OUT16_IDX 230 -#define CORE_GPIO_IN_PAD_IN17_IDX 231 -#define CORE_GPIO_OUT_PAD_OUT17_IDX 231 -#define CORE_GPIO_IN_PAD_IN18_IDX 232 -#define CORE_GPIO_OUT_PAD_OUT18_IDX 232 -#define CORE_GPIO_IN_PAD_IN19_IDX 233 -#define CORE_GPIO_OUT_PAD_OUT19_IDX 233 -#define CORE_GPIO_IN_PAD_IN20_IDX 234 -#define CORE_GPIO_OUT_PAD_OUT20_IDX 234 -#define CORE_GPIO_IN_PAD_IN21_IDX 235 -#define CORE_GPIO_OUT_PAD_OUT21_IDX 235 -#define CORE_GPIO_IN_PAD_IN22_IDX 236 -#define CORE_GPIO_OUT_PAD_OUT22_IDX 236 -#define CORE_GPIO_IN_PAD_IN23_IDX 237 -#define CORE_GPIO_OUT_PAD_OUT23_IDX 237 -#define CORE_GPIO_IN_PAD_IN24_IDX 238 -#define CORE_GPIO_OUT_PAD_OUT24_IDX 238 -#define CORE_GPIO_IN_PAD_IN25_IDX 239 -#define CORE_GPIO_OUT_PAD_OUT25_IDX 239 -#define CORE_GPIO_IN_PAD_IN26_IDX 240 -#define CORE_GPIO_OUT_PAD_OUT26_IDX 240 -#define CORE_GPIO_IN_PAD_IN27_IDX 241 -#define CORE_GPIO_OUT_PAD_OUT27_IDX 241 -#define CORE_GPIO_IN_PAD_IN28_IDX 242 -#define PARLIO_TX_CS_PAD_OUT_IDX 242 -#define CORE_GPIO_IN_PAD_IN29_IDX 243 -#define EMAC_PTP_PPS_PAD_OUT_IDX 243 -#define CORE_GPIO_IN_PAD_IN30_IDX 244 -#define ANA_COMP0_OUT_IDX 244 -#define CORE_GPIO_IN_PAD_IN31_IDX 245 -#define ANA_COMP1_OUT_IDX 245 -#define RMT_SIG_PAD_IN0_IDX 246 -#define RMT_SIG_PAD_OUT0_IDX 246 -#define RMT_SIG_PAD_IN1_IDX 247 -#define RMT_SIG_PAD_OUT1_IDX 247 -#define RMT_SIG_PAD_IN2_IDX 248 -#define RMT_SIG_PAD_OUT2_IDX 248 -#define RMT_SIG_PAD_IN3_IDX 249 -#define RMT_SIG_PAD_OUT3_IDX 249 -#define SIG_IN_FUNC250_IDX 250 -#define SIG_IN_FUNC250_IDX 250 -#define SIG_IN_FUNC251_IDX 251 -#define SIG_IN_FUNC251_IDX 251 -#define SIG_IN_FUNC252_IDX 252 -#define SIG_IN_FUNC252_IDX 252 -#define SIG_IN_FUNC253_IDX 253 -#define SIG_IN_FUNC253_IDX 253 -#define SIG_IN_FUNC254_IDX 254 -#define SIG_IN_FUNC254_IDX 254 -#define SIG_IN_FUNC255_IDX 255 -#define SIG_IN_FUNC255_IDX 255 -// version date 230403 -#define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h deleted file mode 100644 index c651fb6e56..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_reg.h +++ /dev/null @@ -1,5466 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -// definitions below are generated from pin_txt.csv -#define PERIPHS_IO_MUX_U_PAD_GPIO0 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO0_GPIO0_0 0 -#define FUNC_GPIO0_GPIO0 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO1 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO1_GPIO1_0 0 -#define FUNC_GPIO1_GPIO1 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO2_MTCK 0 -#define FUNC_GPIO2_GPIO2 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO3 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO3_MTDI 0 -#define FUNC_GPIO3_GPIO3 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO4 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO4_MTMS 0 -#define FUNC_GPIO4_GPIO4 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO5 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO5_MTDO 0 -#define FUNC_GPIO5_GPIO5 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO6 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO6_GPIO6_0 0 -#define FUNC_GPIO6_GPIO6 1 -#define FUNC_GPIO6_SPI2_HOLD_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO7_GPIO7_0 0 -#define FUNC_GPIO7_GPIO7 1 -#define FUNC_GPIO7_SPI2_CS_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO8_GPIO8_0 0 -#define FUNC_GPIO8_GPIO8 1 -#define FUNC_GPIO8_UART0_RTS_PAD 2 -#define FUNC_GPIO8_SPI2_D_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO9_GPIO9_0 0 -#define FUNC_GPIO9_GPIO9 1 -#define FUNC_GPIO9_UART0_CTS_PAD 2 -#define FUNC_GPIO9_SPI2_CK_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO10 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO10_GPIO10_0 0 -#define FUNC_GPIO10_GPIO10 1 -#define FUNC_GPIO10_UART1_TXD_PAD 2 -#define FUNC_GPIO10_SPI2_Q_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO11 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO11_GPIO11_0 0 -#define FUNC_GPIO11_GPIO11 1 -#define FUNC_GPIO11_UART1_RXD_PAD 2 -#define FUNC_GPIO11_SPI2_WP_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO12_GPIO12_0 0 -#define FUNC_GPIO12_GPIO12 1 -#define FUNC_GPIO12_UART1_RTS_PAD 2 - -#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO13_GPIO13_0 0 -#define FUNC_GPIO13_GPIO13 1 -#define FUNC_GPIO13_UART1_CTS_PAD 2 - -#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO14_GPIO14_0 0 -#define FUNC_GPIO14_GPIO14 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO15 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO15_GPIO15_0 0 -#define FUNC_GPIO15_GPIO15 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO16 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO16_GPIO16_0 0 -#define FUNC_GPIO16_GPIO16 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO17_GPIO17_0 0 -#define FUNC_GPIO17_GPIO17 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO18_GPIO18_0 0 -#define FUNC_GPIO18_GPIO18 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO19 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO19_GPIO19_0 0 -#define FUNC_GPIO19_GPIO19 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO20 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO20_GPIO20_0 0 -#define FUNC_GPIO20_GPIO20 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO21 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO21_GPIO21_0 0 -#define FUNC_GPIO21_GPIO21 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO22_GPIO22_0 0 -#define FUNC_GPIO22_GPIO22 1 -#define FUNC_GPIO22_DBG_PSRAM_CK_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO23_GPIO23_0 0 -#define FUNC_GPIO23_GPIO23 1 -#define FUNC_GPIO23_REF_50M_CLK_PAD 3 -#define FUNC_GPIO23_DBG_PSRAM_CS_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO24_GPIO24_0 0 -#define FUNC_GPIO24_GPIO24 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO25_GPIO25_0 0 -#define FUNC_GPIO25_GPIO25 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO26_GPIO26_0 0 -#define FUNC_GPIO26_GPIO26 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO27 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO27_GPIO27_0 0 -#define FUNC_GPIO27_GPIO27 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO28 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO28_GPIO28_0 0 -#define FUNC_GPIO28_GPIO28 1 -#define FUNC_GPIO28_SPI2_CS_PAD 2 -#define FUNC_GPIO28_GMAC_PHY_RXDV_PAD 3 -#define FUNC_GPIO28_DBG_PSRAM_D_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO29 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO29_GPIO29_0 0 -#define FUNC_GPIO29_GPIO29 1 -#define FUNC_GPIO29_SPI2_D_PAD 2 -#define FUNC_GPIO29_GMAC_PHY_RXD0_PAD 3 -#define FUNC_GPIO29_DBG_PSRAM_Q_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO30 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO30_GPIO30_0 0 -#define FUNC_GPIO30_GPIO30 1 -#define FUNC_GPIO30_SPI2_CK_PAD 2 -#define FUNC_GPIO30_GMAC_PHY_RXD1_PAD 3 -#define FUNC_GPIO30_DBG_PSRAM_WP_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO31 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO31_GPIO31_0 0 -#define FUNC_GPIO31_GPIO31 1 -#define FUNC_GPIO31_SPI2_Q_PAD 2 -#define FUNC_GPIO31_GMAC_PHY_RXER_PAD 3 -#define FUNC_GPIO31_DBG_PSRAM_HOLD_PAD 4 - -// Strapping: Diag Group Sel1 -#define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO32_GPIO32_0 0 -#define FUNC_GPIO32_GPIO32 1 -#define FUNC_GPIO32_SPI2_HOLD_PAD 2 -#define FUNC_GPIO32_GMAC_RMII_CLK_PAD 3 -#define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD 4 - -// Strapping: Diag Group Sel0 -#define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO33_GPIO33_0 0 -#define FUNC_GPIO33_GPIO33 1 -#define FUNC_GPIO33_SPI2_WP_PAD 2 -#define FUNC_GPIO33_GMAC_PHY_TXEN_PAD 3 -#define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD 4 - -// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag -#define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO34_GPIO34_0 0 -#define FUNC_GPIO34_GPIO34 1 -#define FUNC_GPIO34_SPI2_IO4_PAD 2 -#define FUNC_GPIO34_GMAC_PHY_TXD0_PAD 3 -#define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD 4 - -// Strapping: Boot Mode select 3 -#define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO35_GPIO35_0 0 -#define FUNC_GPIO35_GPIO35 1 -#define FUNC_GPIO35_SPI2_IO5_PAD 2 -#define FUNC_GPIO35_GMAC_PHY_TXD1_PAD 3 -#define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD 4 - -// Strapping: Boot Mode select 2 -#define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO36_GPIO36_0 0 -#define FUNC_GPIO36_GPIO36 1 -#define FUNC_GPIO36_SPI2_IO6_PAD 2 -#define FUNC_GPIO36_GMAC_PHY_TXER_PAD 3 -#define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD 4 - -// Strapping: Boot Mode select 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO37_UART0_TXD_PAD 0 -#define FUNC_GPIO37_GPIO37 1 -#define FUNC_GPIO37_SPI2_IO7_PAD 2 - -// Strapping: Boot Mode select 0 -#define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO38_UART0_RXD_PAD 0 -#define FUNC_GPIO38_GPIO38 1 -#define FUNC_GPIO38_SPI2_DQS_PAD 2 - -#define PERIPHS_IO_MUX_U_PAD_GPIO39 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO39_SD1_CDATA0_PAD 0 -#define FUNC_GPIO39_GPIO39 1 -#define FUNC_GPIO39_BIST_PAD 2 -#define FUNC_GPIO39_REF_50M_CLK_PAD 3 -#define FUNC_GPIO39_DBG_PSRAM_DQ8_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO40 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO40_SD1_CDATA1_PAD 0 -#define FUNC_GPIO40_GPIO40 1 -#define FUNC_GPIO40_BIST_PAD 2 -#define FUNC_GPIO40_GMAC_PHY_TXEN_PAD 3 -#define FUNC_GPIO40_DBG_PSRAM_DQ9_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO41 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO41_SD1_CDATA2_PAD 0 -#define FUNC_GPIO41_GPIO41 1 -#define FUNC_GPIO41_BIST_PAD 2 -#define FUNC_GPIO41_GMAC_PHY_TXD0_PAD 3 -#define FUNC_GPIO41_DBG_PSRAM_DQ10_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO42 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO42_SD1_CDATA3_PAD 0 -#define FUNC_GPIO42_GPIO42 1 -#define FUNC_GPIO42_BIST_PAD 2 -#define FUNC_GPIO42_GMAC_PHY_TXD1_PAD 3 -#define FUNC_GPIO42_DBG_PSRAM_DQ11_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO43 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO43_SD1_CCLK_PAD 0 -#define FUNC_GPIO43_GPIO43 1 -#define FUNC_GPIO43_BIST_PAD 2 -#define FUNC_GPIO43_GMAC_PHY_TXER_PAD 3 -#define FUNC_GPIO43_DBG_PSRAM_DQ12_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO44 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO44_SD1_CCMD_PAD 0 -#define FUNC_GPIO44_GPIO44 1 -#define FUNC_GPIO44_BIST_PAD 2 -#define FUNC_GPIO44_GMAC_RMII_CLK_PAD 3 -#define FUNC_GPIO44_DBG_PSRAM_DQ13_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO45 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO45_SD1_CDATA4_PAD 0 -#define FUNC_GPIO45_GPIO45 1 -#define FUNC_GPIO45_BIST_PAD 2 -#define FUNC_GPIO45_GMAC_PHY_RXDV_PAD 3 -#define FUNC_GPIO45_DBG_PSRAM_DQ14_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO46 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO46_SD1_CDATA5_PAD 0 -#define FUNC_GPIO46_GPIO46 1 -#define FUNC_GPIO46_BIST_PAD 2 -#define FUNC_GPIO46_GMAC_PHY_RXD0_PAD 3 -#define FUNC_GPIO46_DBG_PSRAM_DQ15_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO47 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO47_SD1_CDATA6_PAD 0 -#define FUNC_GPIO47_GPIO47 1 -#define FUNC_GPIO47_BIST_PAD 2 -#define FUNC_GPIO47_GMAC_PHY_RXD1_PAD 3 -#define FUNC_GPIO47_DBG_PSRAM_DQS_1_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO48 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO48_SD1_CDATA7_PAD 0 -#define FUNC_GPIO48_GPIO48 1 -#define FUNC_GPIO48_BIST_PAD 2 -#define FUNC_GPIO48_GMAC_PHY_RXER_PAD 3 - -#define PERIPHS_IO_MUX_U_PAD_GPIO49 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO49_GPIO49_0 0 -#define FUNC_GPIO49_GPIO49 1 -#define FUNC_GPIO49_GMAC_PHY_TXEN_PAD 3 -#define FUNC_GPIO49_DBG_FLASH_CS_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO50 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO50_GPIO50_0 0 -#define FUNC_GPIO50_GPIO50 1 -#define FUNC_GPIO50_GMAC_RMII_CLK_PAD 3 -#define FUNC_GPIO50_DBG_FLASH_Q_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO51 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO51_GPIO51_0 0 -#define FUNC_GPIO51_GPIO51 1 -#define FUNC_GPIO51_GMAC_PHY_RXDV_PAD 3 -#define FUNC_GPIO51_DBG_FLASH_WP_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO52 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO52_GPIO52_0 0 -#define FUNC_GPIO52_GPIO52 1 -#define FUNC_GPIO52_GMAC_PHY_RXD0_PAD 3 -#define FUNC_GPIO52_DBG_FLASH_HOLD_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO53 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO53_GPIO53_0 0 -#define FUNC_GPIO53_GPIO53 1 -#define FUNC_GPIO53_GMAC_PHY_RXD1_PAD 3 -#define FUNC_GPIO53_DBG_FLASH_CK_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO54 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO54_GPIO54_0 0 -#define FUNC_GPIO54_GPIO54 1 -#define FUNC_GPIO54_GMAC_PHY_RXER_PAD 3 -#define FUNC_GPIO54_DBG_FLASH_D_PAD 4 - -#define PERIPHS_IO_MUX_U_PAD_GPIO55 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO55_GPIO55_0 0 -#define FUNC_GPIO55_GPIO55 1 - -#define PERIPHS_IO_MUX_U_PAD_GPIO56 (REG_IO_MUX_BASE + 0x0) -#define FUNC_GPIO56_GPIO56_0 0 -#define FUNC_GPIO56_GPIO56 1 - - -/** IO_MUX_gpio0_REG register - * iomux control register for gpio0 - */ -#define IO_MUX_GPIO0_REG (DR_REG_IO_MUX_BASE + 0x4) -/** IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_OE (BIT(0)) -#define IO_MUX_GPIO0_MCU_OE_M (IO_MUX_GPIO0_MCU_OE_V << IO_MUX_GPIO0_MCU_OE_S) -#define IO_MUX_GPIO0_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO0_MCU_OE_S 0 -/** IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO0_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO0_SLP_SEL_M (IO_MUX_GPIO0_SLP_SEL_V << IO_MUX_GPIO0_SLP_SEL_S) -#define IO_MUX_GPIO0_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO0_SLP_SEL_S 1 -/** IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO0_MCU_WPD_M (IO_MUX_GPIO0_MCU_WPD_V << IO_MUX_GPIO0_MCU_WPD_S) -#define IO_MUX_GPIO0_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO0_MCU_WPD_S 2 -/** IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO0_MCU_WPU_M (IO_MUX_GPIO0_MCU_WPU_V << IO_MUX_GPIO0_MCU_WPU_S) -#define IO_MUX_GPIO0_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO0_MCU_WPU_S 3 -/** IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO0_MCU_IE (BIT(4)) -#define IO_MUX_GPIO0_MCU_IE_M (IO_MUX_GPIO0_MCU_IE_V << IO_MUX_GPIO0_MCU_IE_S) -#define IO_MUX_GPIO0_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO0_MCU_IE_S 4 -/** IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO0_MCU_DRV 0x00000003U -#define IO_MUX_GPIO0_MCU_DRV_M (IO_MUX_GPIO0_MCU_DRV_V << IO_MUX_GPIO0_MCU_DRV_S) -#define IO_MUX_GPIO0_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO0_MCU_DRV_S 5 -/** IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO0_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO0_FUN_WPD_M (IO_MUX_GPIO0_FUN_WPD_V << IO_MUX_GPIO0_FUN_WPD_S) -#define IO_MUX_GPIO0_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO0_FUN_WPD_S 7 -/** IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO0_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO0_FUN_WPU_M (IO_MUX_GPIO0_FUN_WPU_V << IO_MUX_GPIO0_FUN_WPU_S) -#define IO_MUX_GPIO0_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO0_FUN_WPU_S 8 -/** IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO0_FUN_IE (BIT(9)) -#define IO_MUX_GPIO0_FUN_IE_M (IO_MUX_GPIO0_FUN_IE_V << IO_MUX_GPIO0_FUN_IE_S) -#define IO_MUX_GPIO0_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO0_FUN_IE_S 9 -/** IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO0_FUN_DRV 0x00000003U -#define IO_MUX_GPIO0_FUN_DRV_M (IO_MUX_GPIO0_FUN_DRV_V << IO_MUX_GPIO0_FUN_DRV_S) -#define IO_MUX_GPIO0_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO0_FUN_DRV_S 10 -/** IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO0_MCU_SEL 0x00000007U -#define IO_MUX_GPIO0_MCU_SEL_M (IO_MUX_GPIO0_MCU_SEL_V << IO_MUX_GPIO0_MCU_SEL_S) -#define IO_MUX_GPIO0_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO0_MCU_SEL_S 12 -/** IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO0_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO0_FILTER_EN_M (IO_MUX_GPIO0_FILTER_EN_V << IO_MUX_GPIO0_FILTER_EN_S) -#define IO_MUX_GPIO0_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO0_FILTER_EN_S 15 - -/** IO_MUX_gpio1_REG register - * iomux control register for gpio1 - */ -#define IO_MUX_GPIO1_REG (DR_REG_IO_MUX_BASE + 0x8) -/** IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_OE (BIT(0)) -#define IO_MUX_GPIO1_MCU_OE_M (IO_MUX_GPIO1_MCU_OE_V << IO_MUX_GPIO1_MCU_OE_S) -#define IO_MUX_GPIO1_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO1_MCU_OE_S 0 -/** IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO1_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO1_SLP_SEL_M (IO_MUX_GPIO1_SLP_SEL_V << IO_MUX_GPIO1_SLP_SEL_S) -#define IO_MUX_GPIO1_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO1_SLP_SEL_S 1 -/** IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO1_MCU_WPD_M (IO_MUX_GPIO1_MCU_WPD_V << IO_MUX_GPIO1_MCU_WPD_S) -#define IO_MUX_GPIO1_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO1_MCU_WPD_S 2 -/** IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO1_MCU_WPU_M (IO_MUX_GPIO1_MCU_WPU_V << IO_MUX_GPIO1_MCU_WPU_S) -#define IO_MUX_GPIO1_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO1_MCU_WPU_S 3 -/** IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO1_MCU_IE (BIT(4)) -#define IO_MUX_GPIO1_MCU_IE_M (IO_MUX_GPIO1_MCU_IE_V << IO_MUX_GPIO1_MCU_IE_S) -#define IO_MUX_GPIO1_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO1_MCU_IE_S 4 -/** IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO1_MCU_DRV 0x00000003U -#define IO_MUX_GPIO1_MCU_DRV_M (IO_MUX_GPIO1_MCU_DRV_V << IO_MUX_GPIO1_MCU_DRV_S) -#define IO_MUX_GPIO1_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO1_MCU_DRV_S 5 -/** IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO1_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO1_FUN_WPD_M (IO_MUX_GPIO1_FUN_WPD_V << IO_MUX_GPIO1_FUN_WPD_S) -#define IO_MUX_GPIO1_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO1_FUN_WPD_S 7 -/** IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO1_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO1_FUN_WPU_M (IO_MUX_GPIO1_FUN_WPU_V << IO_MUX_GPIO1_FUN_WPU_S) -#define IO_MUX_GPIO1_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO1_FUN_WPU_S 8 -/** IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO1_FUN_IE (BIT(9)) -#define IO_MUX_GPIO1_FUN_IE_M (IO_MUX_GPIO1_FUN_IE_V << IO_MUX_GPIO1_FUN_IE_S) -#define IO_MUX_GPIO1_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO1_FUN_IE_S 9 -/** IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO1_FUN_DRV 0x00000003U -#define IO_MUX_GPIO1_FUN_DRV_M (IO_MUX_GPIO1_FUN_DRV_V << IO_MUX_GPIO1_FUN_DRV_S) -#define IO_MUX_GPIO1_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO1_FUN_DRV_S 10 -/** IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO1_MCU_SEL 0x00000007U -#define IO_MUX_GPIO1_MCU_SEL_M (IO_MUX_GPIO1_MCU_SEL_V << IO_MUX_GPIO1_MCU_SEL_S) -#define IO_MUX_GPIO1_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO1_MCU_SEL_S 12 -/** IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO1_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO1_FILTER_EN_M (IO_MUX_GPIO1_FILTER_EN_V << IO_MUX_GPIO1_FILTER_EN_S) -#define IO_MUX_GPIO1_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO1_FILTER_EN_S 15 - -/** IO_MUX_gpio2_REG register - * iomux control register for gpio2 - */ -#define IO_MUX_GPIO2_REG (DR_REG_IO_MUX_BASE + 0xc) -/** IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_OE (BIT(0)) -#define IO_MUX_GPIO2_MCU_OE_M (IO_MUX_GPIO2_MCU_OE_V << IO_MUX_GPIO2_MCU_OE_S) -#define IO_MUX_GPIO2_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO2_MCU_OE_S 0 -/** IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO2_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO2_SLP_SEL_M (IO_MUX_GPIO2_SLP_SEL_V << IO_MUX_GPIO2_SLP_SEL_S) -#define IO_MUX_GPIO2_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO2_SLP_SEL_S 1 -/** IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO2_MCU_WPD_M (IO_MUX_GPIO2_MCU_WPD_V << IO_MUX_GPIO2_MCU_WPD_S) -#define IO_MUX_GPIO2_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO2_MCU_WPD_S 2 -/** IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO2_MCU_WPU_M (IO_MUX_GPIO2_MCU_WPU_V << IO_MUX_GPIO2_MCU_WPU_S) -#define IO_MUX_GPIO2_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO2_MCU_WPU_S 3 -/** IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO2_MCU_IE (BIT(4)) -#define IO_MUX_GPIO2_MCU_IE_M (IO_MUX_GPIO2_MCU_IE_V << IO_MUX_GPIO2_MCU_IE_S) -#define IO_MUX_GPIO2_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO2_MCU_IE_S 4 -/** IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO2_MCU_DRV 0x00000003U -#define IO_MUX_GPIO2_MCU_DRV_M (IO_MUX_GPIO2_MCU_DRV_V << IO_MUX_GPIO2_MCU_DRV_S) -#define IO_MUX_GPIO2_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO2_MCU_DRV_S 5 -/** IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO2_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO2_FUN_WPD_M (IO_MUX_GPIO2_FUN_WPD_V << IO_MUX_GPIO2_FUN_WPD_S) -#define IO_MUX_GPIO2_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO2_FUN_WPD_S 7 -/** IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO2_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO2_FUN_WPU_M (IO_MUX_GPIO2_FUN_WPU_V << IO_MUX_GPIO2_FUN_WPU_S) -#define IO_MUX_GPIO2_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO2_FUN_WPU_S 8 -/** IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO2_FUN_IE (BIT(9)) -#define IO_MUX_GPIO2_FUN_IE_M (IO_MUX_GPIO2_FUN_IE_V << IO_MUX_GPIO2_FUN_IE_S) -#define IO_MUX_GPIO2_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO2_FUN_IE_S 9 -/** IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO2_FUN_DRV 0x00000003U -#define IO_MUX_GPIO2_FUN_DRV_M (IO_MUX_GPIO2_FUN_DRV_V << IO_MUX_GPIO2_FUN_DRV_S) -#define IO_MUX_GPIO2_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO2_FUN_DRV_S 10 -/** IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO2_MCU_SEL 0x00000007U -#define IO_MUX_GPIO2_MCU_SEL_M (IO_MUX_GPIO2_MCU_SEL_V << IO_MUX_GPIO2_MCU_SEL_S) -#define IO_MUX_GPIO2_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO2_MCU_SEL_S 12 -/** IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO2_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO2_FILTER_EN_M (IO_MUX_GPIO2_FILTER_EN_V << IO_MUX_GPIO2_FILTER_EN_S) -#define IO_MUX_GPIO2_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO2_FILTER_EN_S 15 - -/** IO_MUX_gpio3_REG register - * iomux control register for gpio3 - */ -#define IO_MUX_GPIO3_REG (DR_REG_IO_MUX_BASE + 0x10) -/** IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_OE (BIT(0)) -#define IO_MUX_GPIO3_MCU_OE_M (IO_MUX_GPIO3_MCU_OE_V << IO_MUX_GPIO3_MCU_OE_S) -#define IO_MUX_GPIO3_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO3_MCU_OE_S 0 -/** IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO3_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO3_SLP_SEL_M (IO_MUX_GPIO3_SLP_SEL_V << IO_MUX_GPIO3_SLP_SEL_S) -#define IO_MUX_GPIO3_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO3_SLP_SEL_S 1 -/** IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO3_MCU_WPD_M (IO_MUX_GPIO3_MCU_WPD_V << IO_MUX_GPIO3_MCU_WPD_S) -#define IO_MUX_GPIO3_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO3_MCU_WPD_S 2 -/** IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO3_MCU_WPU_M (IO_MUX_GPIO3_MCU_WPU_V << IO_MUX_GPIO3_MCU_WPU_S) -#define IO_MUX_GPIO3_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO3_MCU_WPU_S 3 -/** IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO3_MCU_IE (BIT(4)) -#define IO_MUX_GPIO3_MCU_IE_M (IO_MUX_GPIO3_MCU_IE_V << IO_MUX_GPIO3_MCU_IE_S) -#define IO_MUX_GPIO3_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO3_MCU_IE_S 4 -/** IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO3_MCU_DRV 0x00000003U -#define IO_MUX_GPIO3_MCU_DRV_M (IO_MUX_GPIO3_MCU_DRV_V << IO_MUX_GPIO3_MCU_DRV_S) -#define IO_MUX_GPIO3_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO3_MCU_DRV_S 5 -/** IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO3_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO3_FUN_WPD_M (IO_MUX_GPIO3_FUN_WPD_V << IO_MUX_GPIO3_FUN_WPD_S) -#define IO_MUX_GPIO3_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO3_FUN_WPD_S 7 -/** IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO3_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO3_FUN_WPU_M (IO_MUX_GPIO3_FUN_WPU_V << IO_MUX_GPIO3_FUN_WPU_S) -#define IO_MUX_GPIO3_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO3_FUN_WPU_S 8 -/** IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO3_FUN_IE (BIT(9)) -#define IO_MUX_GPIO3_FUN_IE_M (IO_MUX_GPIO3_FUN_IE_V << IO_MUX_GPIO3_FUN_IE_S) -#define IO_MUX_GPIO3_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO3_FUN_IE_S 9 -/** IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO3_FUN_DRV 0x00000003U -#define IO_MUX_GPIO3_FUN_DRV_M (IO_MUX_GPIO3_FUN_DRV_V << IO_MUX_GPIO3_FUN_DRV_S) -#define IO_MUX_GPIO3_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO3_FUN_DRV_S 10 -/** IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO3_MCU_SEL 0x00000007U -#define IO_MUX_GPIO3_MCU_SEL_M (IO_MUX_GPIO3_MCU_SEL_V << IO_MUX_GPIO3_MCU_SEL_S) -#define IO_MUX_GPIO3_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO3_MCU_SEL_S 12 -/** IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO3_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO3_FILTER_EN_M (IO_MUX_GPIO3_FILTER_EN_V << IO_MUX_GPIO3_FILTER_EN_S) -#define IO_MUX_GPIO3_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO3_FILTER_EN_S 15 - -/** IO_MUX_gpio4_REG register - * iomux control register for gpio4 - */ -#define IO_MUX_GPIO4_REG (DR_REG_IO_MUX_BASE + 0x14) -/** IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_OE (BIT(0)) -#define IO_MUX_GPIO4_MCU_OE_M (IO_MUX_GPIO4_MCU_OE_V << IO_MUX_GPIO4_MCU_OE_S) -#define IO_MUX_GPIO4_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO4_MCU_OE_S 0 -/** IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO4_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO4_SLP_SEL_M (IO_MUX_GPIO4_SLP_SEL_V << IO_MUX_GPIO4_SLP_SEL_S) -#define IO_MUX_GPIO4_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO4_SLP_SEL_S 1 -/** IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO4_MCU_WPD_M (IO_MUX_GPIO4_MCU_WPD_V << IO_MUX_GPIO4_MCU_WPD_S) -#define IO_MUX_GPIO4_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO4_MCU_WPD_S 2 -/** IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO4_MCU_WPU_M (IO_MUX_GPIO4_MCU_WPU_V << IO_MUX_GPIO4_MCU_WPU_S) -#define IO_MUX_GPIO4_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO4_MCU_WPU_S 3 -/** IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO4_MCU_IE (BIT(4)) -#define IO_MUX_GPIO4_MCU_IE_M (IO_MUX_GPIO4_MCU_IE_V << IO_MUX_GPIO4_MCU_IE_S) -#define IO_MUX_GPIO4_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO4_MCU_IE_S 4 -/** IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO4_MCU_DRV 0x00000003U -#define IO_MUX_GPIO4_MCU_DRV_M (IO_MUX_GPIO4_MCU_DRV_V << IO_MUX_GPIO4_MCU_DRV_S) -#define IO_MUX_GPIO4_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO4_MCU_DRV_S 5 -/** IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO4_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO4_FUN_WPD_M (IO_MUX_GPIO4_FUN_WPD_V << IO_MUX_GPIO4_FUN_WPD_S) -#define IO_MUX_GPIO4_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO4_FUN_WPD_S 7 -/** IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO4_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO4_FUN_WPU_M (IO_MUX_GPIO4_FUN_WPU_V << IO_MUX_GPIO4_FUN_WPU_S) -#define IO_MUX_GPIO4_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO4_FUN_WPU_S 8 -/** IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO4_FUN_IE (BIT(9)) -#define IO_MUX_GPIO4_FUN_IE_M (IO_MUX_GPIO4_FUN_IE_V << IO_MUX_GPIO4_FUN_IE_S) -#define IO_MUX_GPIO4_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO4_FUN_IE_S 9 -/** IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO4_FUN_DRV 0x00000003U -#define IO_MUX_GPIO4_FUN_DRV_M (IO_MUX_GPIO4_FUN_DRV_V << IO_MUX_GPIO4_FUN_DRV_S) -#define IO_MUX_GPIO4_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO4_FUN_DRV_S 10 -/** IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO4_MCU_SEL 0x00000007U -#define IO_MUX_GPIO4_MCU_SEL_M (IO_MUX_GPIO4_MCU_SEL_V << IO_MUX_GPIO4_MCU_SEL_S) -#define IO_MUX_GPIO4_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO4_MCU_SEL_S 12 -/** IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO4_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO4_FILTER_EN_M (IO_MUX_GPIO4_FILTER_EN_V << IO_MUX_GPIO4_FILTER_EN_S) -#define IO_MUX_GPIO4_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO4_FILTER_EN_S 15 - -/** IO_MUX_gpio5_REG register - * iomux control register for gpio5 - */ -#define IO_MUX_GPIO5_REG (DR_REG_IO_MUX_BASE + 0x18) -/** IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_OE (BIT(0)) -#define IO_MUX_GPIO5_MCU_OE_M (IO_MUX_GPIO5_MCU_OE_V << IO_MUX_GPIO5_MCU_OE_S) -#define IO_MUX_GPIO5_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO5_MCU_OE_S 0 -/** IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO5_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO5_SLP_SEL_M (IO_MUX_GPIO5_SLP_SEL_V << IO_MUX_GPIO5_SLP_SEL_S) -#define IO_MUX_GPIO5_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO5_SLP_SEL_S 1 -/** IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO5_MCU_WPD_M (IO_MUX_GPIO5_MCU_WPD_V << IO_MUX_GPIO5_MCU_WPD_S) -#define IO_MUX_GPIO5_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO5_MCU_WPD_S 2 -/** IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO5_MCU_WPU_M (IO_MUX_GPIO5_MCU_WPU_V << IO_MUX_GPIO5_MCU_WPU_S) -#define IO_MUX_GPIO5_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO5_MCU_WPU_S 3 -/** IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO5_MCU_IE (BIT(4)) -#define IO_MUX_GPIO5_MCU_IE_M (IO_MUX_GPIO5_MCU_IE_V << IO_MUX_GPIO5_MCU_IE_S) -#define IO_MUX_GPIO5_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO5_MCU_IE_S 4 -/** IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO5_MCU_DRV 0x00000003U -#define IO_MUX_GPIO5_MCU_DRV_M (IO_MUX_GPIO5_MCU_DRV_V << IO_MUX_GPIO5_MCU_DRV_S) -#define IO_MUX_GPIO5_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO5_MCU_DRV_S 5 -/** IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO5_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO5_FUN_WPD_M (IO_MUX_GPIO5_FUN_WPD_V << IO_MUX_GPIO5_FUN_WPD_S) -#define IO_MUX_GPIO5_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO5_FUN_WPD_S 7 -/** IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO5_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO5_FUN_WPU_M (IO_MUX_GPIO5_FUN_WPU_V << IO_MUX_GPIO5_FUN_WPU_S) -#define IO_MUX_GPIO5_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO5_FUN_WPU_S 8 -/** IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO5_FUN_IE (BIT(9)) -#define IO_MUX_GPIO5_FUN_IE_M (IO_MUX_GPIO5_FUN_IE_V << IO_MUX_GPIO5_FUN_IE_S) -#define IO_MUX_GPIO5_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO5_FUN_IE_S 9 -/** IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO5_FUN_DRV 0x00000003U -#define IO_MUX_GPIO5_FUN_DRV_M (IO_MUX_GPIO5_FUN_DRV_V << IO_MUX_GPIO5_FUN_DRV_S) -#define IO_MUX_GPIO5_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO5_FUN_DRV_S 10 -/** IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO5_MCU_SEL 0x00000007U -#define IO_MUX_GPIO5_MCU_SEL_M (IO_MUX_GPIO5_MCU_SEL_V << IO_MUX_GPIO5_MCU_SEL_S) -#define IO_MUX_GPIO5_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO5_MCU_SEL_S 12 -/** IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO5_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO5_FILTER_EN_M (IO_MUX_GPIO5_FILTER_EN_V << IO_MUX_GPIO5_FILTER_EN_S) -#define IO_MUX_GPIO5_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO5_FILTER_EN_S 15 - -/** IO_MUX_gpio6_REG register - * iomux control register for gpio6 - */ -#define IO_MUX_GPIO6_REG (DR_REG_IO_MUX_BASE + 0x1c) -/** IO_MUX_GPIO6_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_OE (BIT(0)) -#define IO_MUX_GPIO6_MCU_OE_M (IO_MUX_GPIO6_MCU_OE_V << IO_MUX_GPIO6_MCU_OE_S) -#define IO_MUX_GPIO6_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO6_MCU_OE_S 0 -/** IO_MUX_GPIO6_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO6_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO6_SLP_SEL_M (IO_MUX_GPIO6_SLP_SEL_V << IO_MUX_GPIO6_SLP_SEL_S) -#define IO_MUX_GPIO6_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO6_SLP_SEL_S 1 -/** IO_MUX_GPIO6_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO6_MCU_WPD_M (IO_MUX_GPIO6_MCU_WPD_V << IO_MUX_GPIO6_MCU_WPD_S) -#define IO_MUX_GPIO6_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO6_MCU_WPD_S 2 -/** IO_MUX_GPIO6_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO6_MCU_WPU_M (IO_MUX_GPIO6_MCU_WPU_V << IO_MUX_GPIO6_MCU_WPU_S) -#define IO_MUX_GPIO6_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO6_MCU_WPU_S 3 -/** IO_MUX_GPIO6_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO6_MCU_IE (BIT(4)) -#define IO_MUX_GPIO6_MCU_IE_M (IO_MUX_GPIO6_MCU_IE_V << IO_MUX_GPIO6_MCU_IE_S) -#define IO_MUX_GPIO6_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO6_MCU_IE_S 4 -/** IO_MUX_GPIO6_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO6_MCU_DRV 0x00000003U -#define IO_MUX_GPIO6_MCU_DRV_M (IO_MUX_GPIO6_MCU_DRV_V << IO_MUX_GPIO6_MCU_DRV_S) -#define IO_MUX_GPIO6_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO6_MCU_DRV_S 5 -/** IO_MUX_GPIO6_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO6_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO6_FUN_WPD_M (IO_MUX_GPIO6_FUN_WPD_V << IO_MUX_GPIO6_FUN_WPD_S) -#define IO_MUX_GPIO6_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO6_FUN_WPD_S 7 -/** IO_MUX_GPIO6_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO6_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO6_FUN_WPU_M (IO_MUX_GPIO6_FUN_WPU_V << IO_MUX_GPIO6_FUN_WPU_S) -#define IO_MUX_GPIO6_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO6_FUN_WPU_S 8 -/** IO_MUX_GPIO6_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO6_FUN_IE (BIT(9)) -#define IO_MUX_GPIO6_FUN_IE_M (IO_MUX_GPIO6_FUN_IE_V << IO_MUX_GPIO6_FUN_IE_S) -#define IO_MUX_GPIO6_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO6_FUN_IE_S 9 -/** IO_MUX_GPIO6_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO6_FUN_DRV 0x00000003U -#define IO_MUX_GPIO6_FUN_DRV_M (IO_MUX_GPIO6_FUN_DRV_V << IO_MUX_GPIO6_FUN_DRV_S) -#define IO_MUX_GPIO6_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO6_FUN_DRV_S 10 -/** IO_MUX_GPIO6_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO6_MCU_SEL 0x00000007U -#define IO_MUX_GPIO6_MCU_SEL_M (IO_MUX_GPIO6_MCU_SEL_V << IO_MUX_GPIO6_MCU_SEL_S) -#define IO_MUX_GPIO6_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO6_MCU_SEL_S 12 -/** IO_MUX_GPIO6_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO6_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO6_FILTER_EN_M (IO_MUX_GPIO6_FILTER_EN_V << IO_MUX_GPIO6_FILTER_EN_S) -#define IO_MUX_GPIO6_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO6_FILTER_EN_S 15 - -/** IO_MUX_gpio7_REG register - * iomux control register for gpio7 - */ -#define IO_MUX_GPIO7_REG (DR_REG_IO_MUX_BASE + 0x20) -/** IO_MUX_GPIO7_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_OE (BIT(0)) -#define IO_MUX_GPIO7_MCU_OE_M (IO_MUX_GPIO7_MCU_OE_V << IO_MUX_GPIO7_MCU_OE_S) -#define IO_MUX_GPIO7_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO7_MCU_OE_S 0 -/** IO_MUX_GPIO7_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO7_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO7_SLP_SEL_M (IO_MUX_GPIO7_SLP_SEL_V << IO_MUX_GPIO7_SLP_SEL_S) -#define IO_MUX_GPIO7_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO7_SLP_SEL_S 1 -/** IO_MUX_GPIO7_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO7_MCU_WPD_M (IO_MUX_GPIO7_MCU_WPD_V << IO_MUX_GPIO7_MCU_WPD_S) -#define IO_MUX_GPIO7_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO7_MCU_WPD_S 2 -/** IO_MUX_GPIO7_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO7_MCU_WPU_M (IO_MUX_GPIO7_MCU_WPU_V << IO_MUX_GPIO7_MCU_WPU_S) -#define IO_MUX_GPIO7_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO7_MCU_WPU_S 3 -/** IO_MUX_GPIO7_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO7_MCU_IE (BIT(4)) -#define IO_MUX_GPIO7_MCU_IE_M (IO_MUX_GPIO7_MCU_IE_V << IO_MUX_GPIO7_MCU_IE_S) -#define IO_MUX_GPIO7_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO7_MCU_IE_S 4 -/** IO_MUX_GPIO7_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO7_MCU_DRV 0x00000003U -#define IO_MUX_GPIO7_MCU_DRV_M (IO_MUX_GPIO7_MCU_DRV_V << IO_MUX_GPIO7_MCU_DRV_S) -#define IO_MUX_GPIO7_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO7_MCU_DRV_S 5 -/** IO_MUX_GPIO7_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO7_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO7_FUN_WPD_M (IO_MUX_GPIO7_FUN_WPD_V << IO_MUX_GPIO7_FUN_WPD_S) -#define IO_MUX_GPIO7_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO7_FUN_WPD_S 7 -/** IO_MUX_GPIO7_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO7_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO7_FUN_WPU_M (IO_MUX_GPIO7_FUN_WPU_V << IO_MUX_GPIO7_FUN_WPU_S) -#define IO_MUX_GPIO7_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO7_FUN_WPU_S 8 -/** IO_MUX_GPIO7_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO7_FUN_IE (BIT(9)) -#define IO_MUX_GPIO7_FUN_IE_M (IO_MUX_GPIO7_FUN_IE_V << IO_MUX_GPIO7_FUN_IE_S) -#define IO_MUX_GPIO7_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO7_FUN_IE_S 9 -/** IO_MUX_GPIO7_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO7_FUN_DRV 0x00000003U -#define IO_MUX_GPIO7_FUN_DRV_M (IO_MUX_GPIO7_FUN_DRV_V << IO_MUX_GPIO7_FUN_DRV_S) -#define IO_MUX_GPIO7_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO7_FUN_DRV_S 10 -/** IO_MUX_GPIO7_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO7_MCU_SEL 0x00000007U -#define IO_MUX_GPIO7_MCU_SEL_M (IO_MUX_GPIO7_MCU_SEL_V << IO_MUX_GPIO7_MCU_SEL_S) -#define IO_MUX_GPIO7_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO7_MCU_SEL_S 12 -/** IO_MUX_GPIO7_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO7_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO7_FILTER_EN_M (IO_MUX_GPIO7_FILTER_EN_V << IO_MUX_GPIO7_FILTER_EN_S) -#define IO_MUX_GPIO7_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO7_FILTER_EN_S 15 - -/** IO_MUX_gpio8_REG register - * iomux control register for gpio8 - */ -#define IO_MUX_GPIO8_REG (DR_REG_IO_MUX_BASE + 0x24) -/** IO_MUX_GPIO8_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_OE (BIT(0)) -#define IO_MUX_GPIO8_MCU_OE_M (IO_MUX_GPIO8_MCU_OE_V << IO_MUX_GPIO8_MCU_OE_S) -#define IO_MUX_GPIO8_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO8_MCU_OE_S 0 -/** IO_MUX_GPIO8_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO8_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO8_SLP_SEL_M (IO_MUX_GPIO8_SLP_SEL_V << IO_MUX_GPIO8_SLP_SEL_S) -#define IO_MUX_GPIO8_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO8_SLP_SEL_S 1 -/** IO_MUX_GPIO8_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO8_MCU_WPD_M (IO_MUX_GPIO8_MCU_WPD_V << IO_MUX_GPIO8_MCU_WPD_S) -#define IO_MUX_GPIO8_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO8_MCU_WPD_S 2 -/** IO_MUX_GPIO8_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO8_MCU_WPU_M (IO_MUX_GPIO8_MCU_WPU_V << IO_MUX_GPIO8_MCU_WPU_S) -#define IO_MUX_GPIO8_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO8_MCU_WPU_S 3 -/** IO_MUX_GPIO8_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO8_MCU_IE (BIT(4)) -#define IO_MUX_GPIO8_MCU_IE_M (IO_MUX_GPIO8_MCU_IE_V << IO_MUX_GPIO8_MCU_IE_S) -#define IO_MUX_GPIO8_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO8_MCU_IE_S 4 -/** IO_MUX_GPIO8_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO8_MCU_DRV 0x00000003U -#define IO_MUX_GPIO8_MCU_DRV_M (IO_MUX_GPIO8_MCU_DRV_V << IO_MUX_GPIO8_MCU_DRV_S) -#define IO_MUX_GPIO8_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO8_MCU_DRV_S 5 -/** IO_MUX_GPIO8_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO8_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO8_FUN_WPD_M (IO_MUX_GPIO8_FUN_WPD_V << IO_MUX_GPIO8_FUN_WPD_S) -#define IO_MUX_GPIO8_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO8_FUN_WPD_S 7 -/** IO_MUX_GPIO8_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO8_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO8_FUN_WPU_M (IO_MUX_GPIO8_FUN_WPU_V << IO_MUX_GPIO8_FUN_WPU_S) -#define IO_MUX_GPIO8_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO8_FUN_WPU_S 8 -/** IO_MUX_GPIO8_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO8_FUN_IE (BIT(9)) -#define IO_MUX_GPIO8_FUN_IE_M (IO_MUX_GPIO8_FUN_IE_V << IO_MUX_GPIO8_FUN_IE_S) -#define IO_MUX_GPIO8_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO8_FUN_IE_S 9 -/** IO_MUX_GPIO8_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO8_FUN_DRV 0x00000003U -#define IO_MUX_GPIO8_FUN_DRV_M (IO_MUX_GPIO8_FUN_DRV_V << IO_MUX_GPIO8_FUN_DRV_S) -#define IO_MUX_GPIO8_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO8_FUN_DRV_S 10 -/** IO_MUX_GPIO8_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO8_MCU_SEL 0x00000007U -#define IO_MUX_GPIO8_MCU_SEL_M (IO_MUX_GPIO8_MCU_SEL_V << IO_MUX_GPIO8_MCU_SEL_S) -#define IO_MUX_GPIO8_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO8_MCU_SEL_S 12 -/** IO_MUX_GPIO8_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO8_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO8_FILTER_EN_M (IO_MUX_GPIO8_FILTER_EN_V << IO_MUX_GPIO8_FILTER_EN_S) -#define IO_MUX_GPIO8_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO8_FILTER_EN_S 15 - -/** IO_MUX_gpio9_REG register - * iomux control register for gpio9 - */ -#define IO_MUX_GPIO9_REG (DR_REG_IO_MUX_BASE + 0x28) -/** IO_MUX_GPIO9_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_OE (BIT(0)) -#define IO_MUX_GPIO9_MCU_OE_M (IO_MUX_GPIO9_MCU_OE_V << IO_MUX_GPIO9_MCU_OE_S) -#define IO_MUX_GPIO9_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO9_MCU_OE_S 0 -/** IO_MUX_GPIO9_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO9_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO9_SLP_SEL_M (IO_MUX_GPIO9_SLP_SEL_V << IO_MUX_GPIO9_SLP_SEL_S) -#define IO_MUX_GPIO9_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO9_SLP_SEL_S 1 -/** IO_MUX_GPIO9_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO9_MCU_WPD_M (IO_MUX_GPIO9_MCU_WPD_V << IO_MUX_GPIO9_MCU_WPD_S) -#define IO_MUX_GPIO9_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO9_MCU_WPD_S 2 -/** IO_MUX_GPIO9_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO9_MCU_WPU_M (IO_MUX_GPIO9_MCU_WPU_V << IO_MUX_GPIO9_MCU_WPU_S) -#define IO_MUX_GPIO9_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO9_MCU_WPU_S 3 -/** IO_MUX_GPIO9_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO9_MCU_IE (BIT(4)) -#define IO_MUX_GPIO9_MCU_IE_M (IO_MUX_GPIO9_MCU_IE_V << IO_MUX_GPIO9_MCU_IE_S) -#define IO_MUX_GPIO9_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO9_MCU_IE_S 4 -/** IO_MUX_GPIO9_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO9_MCU_DRV 0x00000003U -#define IO_MUX_GPIO9_MCU_DRV_M (IO_MUX_GPIO9_MCU_DRV_V << IO_MUX_GPIO9_MCU_DRV_S) -#define IO_MUX_GPIO9_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO9_MCU_DRV_S 5 -/** IO_MUX_GPIO9_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO9_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO9_FUN_WPD_M (IO_MUX_GPIO9_FUN_WPD_V << IO_MUX_GPIO9_FUN_WPD_S) -#define IO_MUX_GPIO9_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO9_FUN_WPD_S 7 -/** IO_MUX_GPIO9_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO9_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO9_FUN_WPU_M (IO_MUX_GPIO9_FUN_WPU_V << IO_MUX_GPIO9_FUN_WPU_S) -#define IO_MUX_GPIO9_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO9_FUN_WPU_S 8 -/** IO_MUX_GPIO9_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO9_FUN_IE (BIT(9)) -#define IO_MUX_GPIO9_FUN_IE_M (IO_MUX_GPIO9_FUN_IE_V << IO_MUX_GPIO9_FUN_IE_S) -#define IO_MUX_GPIO9_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO9_FUN_IE_S 9 -/** IO_MUX_GPIO9_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO9_FUN_DRV 0x00000003U -#define IO_MUX_GPIO9_FUN_DRV_M (IO_MUX_GPIO9_FUN_DRV_V << IO_MUX_GPIO9_FUN_DRV_S) -#define IO_MUX_GPIO9_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO9_FUN_DRV_S 10 -/** IO_MUX_GPIO9_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO9_MCU_SEL 0x00000007U -#define IO_MUX_GPIO9_MCU_SEL_M (IO_MUX_GPIO9_MCU_SEL_V << IO_MUX_GPIO9_MCU_SEL_S) -#define IO_MUX_GPIO9_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO9_MCU_SEL_S 12 -/** IO_MUX_GPIO9_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO9_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO9_FILTER_EN_M (IO_MUX_GPIO9_FILTER_EN_V << IO_MUX_GPIO9_FILTER_EN_S) -#define IO_MUX_GPIO9_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO9_FILTER_EN_S 15 - -/** IO_MUX_gpio10_REG register - * iomux control register for gpio10 - */ -#define IO_MUX_GPIO10_REG (DR_REG_IO_MUX_BASE + 0x2c) -/** IO_MUX_GPIO10_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_OE (BIT(0)) -#define IO_MUX_GPIO10_MCU_OE_M (IO_MUX_GPIO10_MCU_OE_V << IO_MUX_GPIO10_MCU_OE_S) -#define IO_MUX_GPIO10_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO10_MCU_OE_S 0 -/** IO_MUX_GPIO10_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO10_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO10_SLP_SEL_M (IO_MUX_GPIO10_SLP_SEL_V << IO_MUX_GPIO10_SLP_SEL_S) -#define IO_MUX_GPIO10_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO10_SLP_SEL_S 1 -/** IO_MUX_GPIO10_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO10_MCU_WPD_M (IO_MUX_GPIO10_MCU_WPD_V << IO_MUX_GPIO10_MCU_WPD_S) -#define IO_MUX_GPIO10_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO10_MCU_WPD_S 2 -/** IO_MUX_GPIO10_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO10_MCU_WPU_M (IO_MUX_GPIO10_MCU_WPU_V << IO_MUX_GPIO10_MCU_WPU_S) -#define IO_MUX_GPIO10_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO10_MCU_WPU_S 3 -/** IO_MUX_GPIO10_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO10_MCU_IE (BIT(4)) -#define IO_MUX_GPIO10_MCU_IE_M (IO_MUX_GPIO10_MCU_IE_V << IO_MUX_GPIO10_MCU_IE_S) -#define IO_MUX_GPIO10_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO10_MCU_IE_S 4 -/** IO_MUX_GPIO10_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO10_MCU_DRV 0x00000003U -#define IO_MUX_GPIO10_MCU_DRV_M (IO_MUX_GPIO10_MCU_DRV_V << IO_MUX_GPIO10_MCU_DRV_S) -#define IO_MUX_GPIO10_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO10_MCU_DRV_S 5 -/** IO_MUX_GPIO10_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO10_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO10_FUN_WPD_M (IO_MUX_GPIO10_FUN_WPD_V << IO_MUX_GPIO10_FUN_WPD_S) -#define IO_MUX_GPIO10_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO10_FUN_WPD_S 7 -/** IO_MUX_GPIO10_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO10_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO10_FUN_WPU_M (IO_MUX_GPIO10_FUN_WPU_V << IO_MUX_GPIO10_FUN_WPU_S) -#define IO_MUX_GPIO10_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO10_FUN_WPU_S 8 -/** IO_MUX_GPIO10_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO10_FUN_IE (BIT(9)) -#define IO_MUX_GPIO10_FUN_IE_M (IO_MUX_GPIO10_FUN_IE_V << IO_MUX_GPIO10_FUN_IE_S) -#define IO_MUX_GPIO10_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO10_FUN_IE_S 9 -/** IO_MUX_GPIO10_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO10_FUN_DRV 0x00000003U -#define IO_MUX_GPIO10_FUN_DRV_M (IO_MUX_GPIO10_FUN_DRV_V << IO_MUX_GPIO10_FUN_DRV_S) -#define IO_MUX_GPIO10_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO10_FUN_DRV_S 10 -/** IO_MUX_GPIO10_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO10_MCU_SEL 0x00000007U -#define IO_MUX_GPIO10_MCU_SEL_M (IO_MUX_GPIO10_MCU_SEL_V << IO_MUX_GPIO10_MCU_SEL_S) -#define IO_MUX_GPIO10_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO10_MCU_SEL_S 12 -/** IO_MUX_GPIO10_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO10_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO10_FILTER_EN_M (IO_MUX_GPIO10_FILTER_EN_V << IO_MUX_GPIO10_FILTER_EN_S) -#define IO_MUX_GPIO10_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO10_FILTER_EN_S 15 - -/** IO_MUX_gpio11_REG register - * iomux control register for gpio11 - */ -#define IO_MUX_GPIO11_REG (DR_REG_IO_MUX_BASE + 0x30) -/** IO_MUX_GPIO11_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_OE (BIT(0)) -#define IO_MUX_GPIO11_MCU_OE_M (IO_MUX_GPIO11_MCU_OE_V << IO_MUX_GPIO11_MCU_OE_S) -#define IO_MUX_GPIO11_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO11_MCU_OE_S 0 -/** IO_MUX_GPIO11_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO11_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO11_SLP_SEL_M (IO_MUX_GPIO11_SLP_SEL_V << IO_MUX_GPIO11_SLP_SEL_S) -#define IO_MUX_GPIO11_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO11_SLP_SEL_S 1 -/** IO_MUX_GPIO11_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO11_MCU_WPD_M (IO_MUX_GPIO11_MCU_WPD_V << IO_MUX_GPIO11_MCU_WPD_S) -#define IO_MUX_GPIO11_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO11_MCU_WPD_S 2 -/** IO_MUX_GPIO11_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO11_MCU_WPU_M (IO_MUX_GPIO11_MCU_WPU_V << IO_MUX_GPIO11_MCU_WPU_S) -#define IO_MUX_GPIO11_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO11_MCU_WPU_S 3 -/** IO_MUX_GPIO11_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO11_MCU_IE (BIT(4)) -#define IO_MUX_GPIO11_MCU_IE_M (IO_MUX_GPIO11_MCU_IE_V << IO_MUX_GPIO11_MCU_IE_S) -#define IO_MUX_GPIO11_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO11_MCU_IE_S 4 -/** IO_MUX_GPIO11_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO11_MCU_DRV 0x00000003U -#define IO_MUX_GPIO11_MCU_DRV_M (IO_MUX_GPIO11_MCU_DRV_V << IO_MUX_GPIO11_MCU_DRV_S) -#define IO_MUX_GPIO11_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO11_MCU_DRV_S 5 -/** IO_MUX_GPIO11_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO11_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO11_FUN_WPD_M (IO_MUX_GPIO11_FUN_WPD_V << IO_MUX_GPIO11_FUN_WPD_S) -#define IO_MUX_GPIO11_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO11_FUN_WPD_S 7 -/** IO_MUX_GPIO11_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO11_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO11_FUN_WPU_M (IO_MUX_GPIO11_FUN_WPU_V << IO_MUX_GPIO11_FUN_WPU_S) -#define IO_MUX_GPIO11_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO11_FUN_WPU_S 8 -/** IO_MUX_GPIO11_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO11_FUN_IE (BIT(9)) -#define IO_MUX_GPIO11_FUN_IE_M (IO_MUX_GPIO11_FUN_IE_V << IO_MUX_GPIO11_FUN_IE_S) -#define IO_MUX_GPIO11_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO11_FUN_IE_S 9 -/** IO_MUX_GPIO11_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO11_FUN_DRV 0x00000003U -#define IO_MUX_GPIO11_FUN_DRV_M (IO_MUX_GPIO11_FUN_DRV_V << IO_MUX_GPIO11_FUN_DRV_S) -#define IO_MUX_GPIO11_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO11_FUN_DRV_S 10 -/** IO_MUX_GPIO11_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO11_MCU_SEL 0x00000007U -#define IO_MUX_GPIO11_MCU_SEL_M (IO_MUX_GPIO11_MCU_SEL_V << IO_MUX_GPIO11_MCU_SEL_S) -#define IO_MUX_GPIO11_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO11_MCU_SEL_S 12 -/** IO_MUX_GPIO11_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO11_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO11_FILTER_EN_M (IO_MUX_GPIO11_FILTER_EN_V << IO_MUX_GPIO11_FILTER_EN_S) -#define IO_MUX_GPIO11_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO11_FILTER_EN_S 15 - -/** IO_MUX_gpio12_REG register - * iomux control register for gpio12 - */ -#define IO_MUX_GPIO12_REG (DR_REG_IO_MUX_BASE + 0x34) -/** IO_MUX_GPIO12_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_OE (BIT(0)) -#define IO_MUX_GPIO12_MCU_OE_M (IO_MUX_GPIO12_MCU_OE_V << IO_MUX_GPIO12_MCU_OE_S) -#define IO_MUX_GPIO12_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO12_MCU_OE_S 0 -/** IO_MUX_GPIO12_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO12_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO12_SLP_SEL_M (IO_MUX_GPIO12_SLP_SEL_V << IO_MUX_GPIO12_SLP_SEL_S) -#define IO_MUX_GPIO12_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO12_SLP_SEL_S 1 -/** IO_MUX_GPIO12_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO12_MCU_WPD_M (IO_MUX_GPIO12_MCU_WPD_V << IO_MUX_GPIO12_MCU_WPD_S) -#define IO_MUX_GPIO12_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO12_MCU_WPD_S 2 -/** IO_MUX_GPIO12_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO12_MCU_WPU_M (IO_MUX_GPIO12_MCU_WPU_V << IO_MUX_GPIO12_MCU_WPU_S) -#define IO_MUX_GPIO12_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO12_MCU_WPU_S 3 -/** IO_MUX_GPIO12_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO12_MCU_IE (BIT(4)) -#define IO_MUX_GPIO12_MCU_IE_M (IO_MUX_GPIO12_MCU_IE_V << IO_MUX_GPIO12_MCU_IE_S) -#define IO_MUX_GPIO12_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO12_MCU_IE_S 4 -/** IO_MUX_GPIO12_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO12_MCU_DRV 0x00000003U -#define IO_MUX_GPIO12_MCU_DRV_M (IO_MUX_GPIO12_MCU_DRV_V << IO_MUX_GPIO12_MCU_DRV_S) -#define IO_MUX_GPIO12_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO12_MCU_DRV_S 5 -/** IO_MUX_GPIO12_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO12_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO12_FUN_WPD_M (IO_MUX_GPIO12_FUN_WPD_V << IO_MUX_GPIO12_FUN_WPD_S) -#define IO_MUX_GPIO12_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO12_FUN_WPD_S 7 -/** IO_MUX_GPIO12_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO12_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO12_FUN_WPU_M (IO_MUX_GPIO12_FUN_WPU_V << IO_MUX_GPIO12_FUN_WPU_S) -#define IO_MUX_GPIO12_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO12_FUN_WPU_S 8 -/** IO_MUX_GPIO12_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO12_FUN_IE (BIT(9)) -#define IO_MUX_GPIO12_FUN_IE_M (IO_MUX_GPIO12_FUN_IE_V << IO_MUX_GPIO12_FUN_IE_S) -#define IO_MUX_GPIO12_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO12_FUN_IE_S 9 -/** IO_MUX_GPIO12_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO12_FUN_DRV 0x00000003U -#define IO_MUX_GPIO12_FUN_DRV_M (IO_MUX_GPIO12_FUN_DRV_V << IO_MUX_GPIO12_FUN_DRV_S) -#define IO_MUX_GPIO12_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO12_FUN_DRV_S 10 -/** IO_MUX_GPIO12_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO12_MCU_SEL 0x00000007U -#define IO_MUX_GPIO12_MCU_SEL_M (IO_MUX_GPIO12_MCU_SEL_V << IO_MUX_GPIO12_MCU_SEL_S) -#define IO_MUX_GPIO12_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO12_MCU_SEL_S 12 -/** IO_MUX_GPIO12_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO12_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO12_FILTER_EN_M (IO_MUX_GPIO12_FILTER_EN_V << IO_MUX_GPIO12_FILTER_EN_S) -#define IO_MUX_GPIO12_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO12_FILTER_EN_S 15 - -/** IO_MUX_gpio13_REG register - * iomux control register for gpio13 - */ -#define IO_MUX_GPIO13_REG (DR_REG_IO_MUX_BASE + 0x38) -/** IO_MUX_GPIO13_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_OE (BIT(0)) -#define IO_MUX_GPIO13_MCU_OE_M (IO_MUX_GPIO13_MCU_OE_V << IO_MUX_GPIO13_MCU_OE_S) -#define IO_MUX_GPIO13_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO13_MCU_OE_S 0 -/** IO_MUX_GPIO13_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO13_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO13_SLP_SEL_M (IO_MUX_GPIO13_SLP_SEL_V << IO_MUX_GPIO13_SLP_SEL_S) -#define IO_MUX_GPIO13_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO13_SLP_SEL_S 1 -/** IO_MUX_GPIO13_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO13_MCU_WPD_M (IO_MUX_GPIO13_MCU_WPD_V << IO_MUX_GPIO13_MCU_WPD_S) -#define IO_MUX_GPIO13_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO13_MCU_WPD_S 2 -/** IO_MUX_GPIO13_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO13_MCU_WPU_M (IO_MUX_GPIO13_MCU_WPU_V << IO_MUX_GPIO13_MCU_WPU_S) -#define IO_MUX_GPIO13_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO13_MCU_WPU_S 3 -/** IO_MUX_GPIO13_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO13_MCU_IE (BIT(4)) -#define IO_MUX_GPIO13_MCU_IE_M (IO_MUX_GPIO13_MCU_IE_V << IO_MUX_GPIO13_MCU_IE_S) -#define IO_MUX_GPIO13_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO13_MCU_IE_S 4 -/** IO_MUX_GPIO13_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO13_MCU_DRV 0x00000003U -#define IO_MUX_GPIO13_MCU_DRV_M (IO_MUX_GPIO13_MCU_DRV_V << IO_MUX_GPIO13_MCU_DRV_S) -#define IO_MUX_GPIO13_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO13_MCU_DRV_S 5 -/** IO_MUX_GPIO13_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO13_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO13_FUN_WPD_M (IO_MUX_GPIO13_FUN_WPD_V << IO_MUX_GPIO13_FUN_WPD_S) -#define IO_MUX_GPIO13_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO13_FUN_WPD_S 7 -/** IO_MUX_GPIO13_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO13_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO13_FUN_WPU_M (IO_MUX_GPIO13_FUN_WPU_V << IO_MUX_GPIO13_FUN_WPU_S) -#define IO_MUX_GPIO13_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO13_FUN_WPU_S 8 -/** IO_MUX_GPIO13_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO13_FUN_IE (BIT(9)) -#define IO_MUX_GPIO13_FUN_IE_M (IO_MUX_GPIO13_FUN_IE_V << IO_MUX_GPIO13_FUN_IE_S) -#define IO_MUX_GPIO13_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO13_FUN_IE_S 9 -/** IO_MUX_GPIO13_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO13_FUN_DRV 0x00000003U -#define IO_MUX_GPIO13_FUN_DRV_M (IO_MUX_GPIO13_FUN_DRV_V << IO_MUX_GPIO13_FUN_DRV_S) -#define IO_MUX_GPIO13_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO13_FUN_DRV_S 10 -/** IO_MUX_GPIO13_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO13_MCU_SEL 0x00000007U -#define IO_MUX_GPIO13_MCU_SEL_M (IO_MUX_GPIO13_MCU_SEL_V << IO_MUX_GPIO13_MCU_SEL_S) -#define IO_MUX_GPIO13_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO13_MCU_SEL_S 12 -/** IO_MUX_GPIO13_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO13_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO13_FILTER_EN_M (IO_MUX_GPIO13_FILTER_EN_V << IO_MUX_GPIO13_FILTER_EN_S) -#define IO_MUX_GPIO13_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO13_FILTER_EN_S 15 - -/** IO_MUX_gpio14_REG register - * iomux control register for gpio14 - */ -#define IO_MUX_GPIO14_REG (DR_REG_IO_MUX_BASE + 0x3c) -/** IO_MUX_GPIO14_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_OE (BIT(0)) -#define IO_MUX_GPIO14_MCU_OE_M (IO_MUX_GPIO14_MCU_OE_V << IO_MUX_GPIO14_MCU_OE_S) -#define IO_MUX_GPIO14_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO14_MCU_OE_S 0 -/** IO_MUX_GPIO14_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO14_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO14_SLP_SEL_M (IO_MUX_GPIO14_SLP_SEL_V << IO_MUX_GPIO14_SLP_SEL_S) -#define IO_MUX_GPIO14_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO14_SLP_SEL_S 1 -/** IO_MUX_GPIO14_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO14_MCU_WPD_M (IO_MUX_GPIO14_MCU_WPD_V << IO_MUX_GPIO14_MCU_WPD_S) -#define IO_MUX_GPIO14_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO14_MCU_WPD_S 2 -/** IO_MUX_GPIO14_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO14_MCU_WPU_M (IO_MUX_GPIO14_MCU_WPU_V << IO_MUX_GPIO14_MCU_WPU_S) -#define IO_MUX_GPIO14_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO14_MCU_WPU_S 3 -/** IO_MUX_GPIO14_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO14_MCU_IE (BIT(4)) -#define IO_MUX_GPIO14_MCU_IE_M (IO_MUX_GPIO14_MCU_IE_V << IO_MUX_GPIO14_MCU_IE_S) -#define IO_MUX_GPIO14_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO14_MCU_IE_S 4 -/** IO_MUX_GPIO14_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO14_MCU_DRV 0x00000003U -#define IO_MUX_GPIO14_MCU_DRV_M (IO_MUX_GPIO14_MCU_DRV_V << IO_MUX_GPIO14_MCU_DRV_S) -#define IO_MUX_GPIO14_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO14_MCU_DRV_S 5 -/** IO_MUX_GPIO14_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO14_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO14_FUN_WPD_M (IO_MUX_GPIO14_FUN_WPD_V << IO_MUX_GPIO14_FUN_WPD_S) -#define IO_MUX_GPIO14_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO14_FUN_WPD_S 7 -/** IO_MUX_GPIO14_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO14_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO14_FUN_WPU_M (IO_MUX_GPIO14_FUN_WPU_V << IO_MUX_GPIO14_FUN_WPU_S) -#define IO_MUX_GPIO14_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO14_FUN_WPU_S 8 -/** IO_MUX_GPIO14_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO14_FUN_IE (BIT(9)) -#define IO_MUX_GPIO14_FUN_IE_M (IO_MUX_GPIO14_FUN_IE_V << IO_MUX_GPIO14_FUN_IE_S) -#define IO_MUX_GPIO14_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO14_FUN_IE_S 9 -/** IO_MUX_GPIO14_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO14_FUN_DRV 0x00000003U -#define IO_MUX_GPIO14_FUN_DRV_M (IO_MUX_GPIO14_FUN_DRV_V << IO_MUX_GPIO14_FUN_DRV_S) -#define IO_MUX_GPIO14_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO14_FUN_DRV_S 10 -/** IO_MUX_GPIO14_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO14_MCU_SEL 0x00000007U -#define IO_MUX_GPIO14_MCU_SEL_M (IO_MUX_GPIO14_MCU_SEL_V << IO_MUX_GPIO14_MCU_SEL_S) -#define IO_MUX_GPIO14_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO14_MCU_SEL_S 12 -/** IO_MUX_GPIO14_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO14_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO14_FILTER_EN_M (IO_MUX_GPIO14_FILTER_EN_V << IO_MUX_GPIO14_FILTER_EN_S) -#define IO_MUX_GPIO14_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO14_FILTER_EN_S 15 - -/** IO_MUX_gpio15_REG register - * iomux control register for gpio15 - */ -#define IO_MUX_GPIO15_REG (DR_REG_IO_MUX_BASE + 0x40) -/** IO_MUX_GPIO15_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_OE (BIT(0)) -#define IO_MUX_GPIO15_MCU_OE_M (IO_MUX_GPIO15_MCU_OE_V << IO_MUX_GPIO15_MCU_OE_S) -#define IO_MUX_GPIO15_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO15_MCU_OE_S 0 -/** IO_MUX_GPIO15_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO15_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO15_SLP_SEL_M (IO_MUX_GPIO15_SLP_SEL_V << IO_MUX_GPIO15_SLP_SEL_S) -#define IO_MUX_GPIO15_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO15_SLP_SEL_S 1 -/** IO_MUX_GPIO15_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO15_MCU_WPD_M (IO_MUX_GPIO15_MCU_WPD_V << IO_MUX_GPIO15_MCU_WPD_S) -#define IO_MUX_GPIO15_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO15_MCU_WPD_S 2 -/** IO_MUX_GPIO15_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO15_MCU_WPU_M (IO_MUX_GPIO15_MCU_WPU_V << IO_MUX_GPIO15_MCU_WPU_S) -#define IO_MUX_GPIO15_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO15_MCU_WPU_S 3 -/** IO_MUX_GPIO15_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO15_MCU_IE (BIT(4)) -#define IO_MUX_GPIO15_MCU_IE_M (IO_MUX_GPIO15_MCU_IE_V << IO_MUX_GPIO15_MCU_IE_S) -#define IO_MUX_GPIO15_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO15_MCU_IE_S 4 -/** IO_MUX_GPIO15_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO15_MCU_DRV 0x00000003U -#define IO_MUX_GPIO15_MCU_DRV_M (IO_MUX_GPIO15_MCU_DRV_V << IO_MUX_GPIO15_MCU_DRV_S) -#define IO_MUX_GPIO15_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO15_MCU_DRV_S 5 -/** IO_MUX_GPIO15_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO15_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO15_FUN_WPD_M (IO_MUX_GPIO15_FUN_WPD_V << IO_MUX_GPIO15_FUN_WPD_S) -#define IO_MUX_GPIO15_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO15_FUN_WPD_S 7 -/** IO_MUX_GPIO15_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO15_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO15_FUN_WPU_M (IO_MUX_GPIO15_FUN_WPU_V << IO_MUX_GPIO15_FUN_WPU_S) -#define IO_MUX_GPIO15_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO15_FUN_WPU_S 8 -/** IO_MUX_GPIO15_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO15_FUN_IE (BIT(9)) -#define IO_MUX_GPIO15_FUN_IE_M (IO_MUX_GPIO15_FUN_IE_V << IO_MUX_GPIO15_FUN_IE_S) -#define IO_MUX_GPIO15_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO15_FUN_IE_S 9 -/** IO_MUX_GPIO15_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO15_FUN_DRV 0x00000003U -#define IO_MUX_GPIO15_FUN_DRV_M (IO_MUX_GPIO15_FUN_DRV_V << IO_MUX_GPIO15_FUN_DRV_S) -#define IO_MUX_GPIO15_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO15_FUN_DRV_S 10 -/** IO_MUX_GPIO15_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO15_MCU_SEL 0x00000007U -#define IO_MUX_GPIO15_MCU_SEL_M (IO_MUX_GPIO15_MCU_SEL_V << IO_MUX_GPIO15_MCU_SEL_S) -#define IO_MUX_GPIO15_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO15_MCU_SEL_S 12 -/** IO_MUX_GPIO15_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO15_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO15_FILTER_EN_M (IO_MUX_GPIO15_FILTER_EN_V << IO_MUX_GPIO15_FILTER_EN_S) -#define IO_MUX_GPIO15_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO15_FILTER_EN_S 15 - -/** IO_MUX_gpio16_REG register - * iomux control register for gpio16 - */ -#define IO_MUX_GPIO16_REG (DR_REG_IO_MUX_BASE + 0x44) -/** IO_MUX_GPIO16_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_OE (BIT(0)) -#define IO_MUX_GPIO16_MCU_OE_M (IO_MUX_GPIO16_MCU_OE_V << IO_MUX_GPIO16_MCU_OE_S) -#define IO_MUX_GPIO16_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO16_MCU_OE_S 0 -/** IO_MUX_GPIO16_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO16_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO16_SLP_SEL_M (IO_MUX_GPIO16_SLP_SEL_V << IO_MUX_GPIO16_SLP_SEL_S) -#define IO_MUX_GPIO16_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO16_SLP_SEL_S 1 -/** IO_MUX_GPIO16_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO16_MCU_WPD_M (IO_MUX_GPIO16_MCU_WPD_V << IO_MUX_GPIO16_MCU_WPD_S) -#define IO_MUX_GPIO16_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO16_MCU_WPD_S 2 -/** IO_MUX_GPIO16_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO16_MCU_WPU_M (IO_MUX_GPIO16_MCU_WPU_V << IO_MUX_GPIO16_MCU_WPU_S) -#define IO_MUX_GPIO16_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO16_MCU_WPU_S 3 -/** IO_MUX_GPIO16_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO16_MCU_IE (BIT(4)) -#define IO_MUX_GPIO16_MCU_IE_M (IO_MUX_GPIO16_MCU_IE_V << IO_MUX_GPIO16_MCU_IE_S) -#define IO_MUX_GPIO16_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO16_MCU_IE_S 4 -/** IO_MUX_GPIO16_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO16_MCU_DRV 0x00000003U -#define IO_MUX_GPIO16_MCU_DRV_M (IO_MUX_GPIO16_MCU_DRV_V << IO_MUX_GPIO16_MCU_DRV_S) -#define IO_MUX_GPIO16_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO16_MCU_DRV_S 5 -/** IO_MUX_GPIO16_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO16_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO16_FUN_WPD_M (IO_MUX_GPIO16_FUN_WPD_V << IO_MUX_GPIO16_FUN_WPD_S) -#define IO_MUX_GPIO16_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO16_FUN_WPD_S 7 -/** IO_MUX_GPIO16_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO16_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO16_FUN_WPU_M (IO_MUX_GPIO16_FUN_WPU_V << IO_MUX_GPIO16_FUN_WPU_S) -#define IO_MUX_GPIO16_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO16_FUN_WPU_S 8 -/** IO_MUX_GPIO16_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO16_FUN_IE (BIT(9)) -#define IO_MUX_GPIO16_FUN_IE_M (IO_MUX_GPIO16_FUN_IE_V << IO_MUX_GPIO16_FUN_IE_S) -#define IO_MUX_GPIO16_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO16_FUN_IE_S 9 -/** IO_MUX_GPIO16_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO16_FUN_DRV 0x00000003U -#define IO_MUX_GPIO16_FUN_DRV_M (IO_MUX_GPIO16_FUN_DRV_V << IO_MUX_GPIO16_FUN_DRV_S) -#define IO_MUX_GPIO16_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO16_FUN_DRV_S 10 -/** IO_MUX_GPIO16_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO16_MCU_SEL 0x00000007U -#define IO_MUX_GPIO16_MCU_SEL_M (IO_MUX_GPIO16_MCU_SEL_V << IO_MUX_GPIO16_MCU_SEL_S) -#define IO_MUX_GPIO16_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO16_MCU_SEL_S 12 -/** IO_MUX_GPIO16_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO16_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO16_FILTER_EN_M (IO_MUX_GPIO16_FILTER_EN_V << IO_MUX_GPIO16_FILTER_EN_S) -#define IO_MUX_GPIO16_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO16_FILTER_EN_S 15 - -/** IO_MUX_gpio17_REG register - * iomux control register for gpio17 - */ -#define IO_MUX_GPIO17_REG (DR_REG_IO_MUX_BASE + 0x48) -/** IO_MUX_GPIO17_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_OE (BIT(0)) -#define IO_MUX_GPIO17_MCU_OE_M (IO_MUX_GPIO17_MCU_OE_V << IO_MUX_GPIO17_MCU_OE_S) -#define IO_MUX_GPIO17_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO17_MCU_OE_S 0 -/** IO_MUX_GPIO17_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO17_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO17_SLP_SEL_M (IO_MUX_GPIO17_SLP_SEL_V << IO_MUX_GPIO17_SLP_SEL_S) -#define IO_MUX_GPIO17_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO17_SLP_SEL_S 1 -/** IO_MUX_GPIO17_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO17_MCU_WPD_M (IO_MUX_GPIO17_MCU_WPD_V << IO_MUX_GPIO17_MCU_WPD_S) -#define IO_MUX_GPIO17_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO17_MCU_WPD_S 2 -/** IO_MUX_GPIO17_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO17_MCU_WPU_M (IO_MUX_GPIO17_MCU_WPU_V << IO_MUX_GPIO17_MCU_WPU_S) -#define IO_MUX_GPIO17_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO17_MCU_WPU_S 3 -/** IO_MUX_GPIO17_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO17_MCU_IE (BIT(4)) -#define IO_MUX_GPIO17_MCU_IE_M (IO_MUX_GPIO17_MCU_IE_V << IO_MUX_GPIO17_MCU_IE_S) -#define IO_MUX_GPIO17_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO17_MCU_IE_S 4 -/** IO_MUX_GPIO17_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO17_MCU_DRV 0x00000003U -#define IO_MUX_GPIO17_MCU_DRV_M (IO_MUX_GPIO17_MCU_DRV_V << IO_MUX_GPIO17_MCU_DRV_S) -#define IO_MUX_GPIO17_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO17_MCU_DRV_S 5 -/** IO_MUX_GPIO17_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO17_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO17_FUN_WPD_M (IO_MUX_GPIO17_FUN_WPD_V << IO_MUX_GPIO17_FUN_WPD_S) -#define IO_MUX_GPIO17_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO17_FUN_WPD_S 7 -/** IO_MUX_GPIO17_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO17_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO17_FUN_WPU_M (IO_MUX_GPIO17_FUN_WPU_V << IO_MUX_GPIO17_FUN_WPU_S) -#define IO_MUX_GPIO17_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO17_FUN_WPU_S 8 -/** IO_MUX_GPIO17_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO17_FUN_IE (BIT(9)) -#define IO_MUX_GPIO17_FUN_IE_M (IO_MUX_GPIO17_FUN_IE_V << IO_MUX_GPIO17_FUN_IE_S) -#define IO_MUX_GPIO17_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO17_FUN_IE_S 9 -/** IO_MUX_GPIO17_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO17_FUN_DRV 0x00000003U -#define IO_MUX_GPIO17_FUN_DRV_M (IO_MUX_GPIO17_FUN_DRV_V << IO_MUX_GPIO17_FUN_DRV_S) -#define IO_MUX_GPIO17_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO17_FUN_DRV_S 10 -/** IO_MUX_GPIO17_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO17_MCU_SEL 0x00000007U -#define IO_MUX_GPIO17_MCU_SEL_M (IO_MUX_GPIO17_MCU_SEL_V << IO_MUX_GPIO17_MCU_SEL_S) -#define IO_MUX_GPIO17_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO17_MCU_SEL_S 12 -/** IO_MUX_GPIO17_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO17_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO17_FILTER_EN_M (IO_MUX_GPIO17_FILTER_EN_V << IO_MUX_GPIO17_FILTER_EN_S) -#define IO_MUX_GPIO17_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO17_FILTER_EN_S 15 - -/** IO_MUX_gpio18_REG register - * iomux control register for gpio18 - */ -#define IO_MUX_GPIO18_REG (DR_REG_IO_MUX_BASE + 0x4c) -/** IO_MUX_GPIO18_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_OE (BIT(0)) -#define IO_MUX_GPIO18_MCU_OE_M (IO_MUX_GPIO18_MCU_OE_V << IO_MUX_GPIO18_MCU_OE_S) -#define IO_MUX_GPIO18_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO18_MCU_OE_S 0 -/** IO_MUX_GPIO18_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO18_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO18_SLP_SEL_M (IO_MUX_GPIO18_SLP_SEL_V << IO_MUX_GPIO18_SLP_SEL_S) -#define IO_MUX_GPIO18_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO18_SLP_SEL_S 1 -/** IO_MUX_GPIO18_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO18_MCU_WPD_M (IO_MUX_GPIO18_MCU_WPD_V << IO_MUX_GPIO18_MCU_WPD_S) -#define IO_MUX_GPIO18_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO18_MCU_WPD_S 2 -/** IO_MUX_GPIO18_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO18_MCU_WPU_M (IO_MUX_GPIO18_MCU_WPU_V << IO_MUX_GPIO18_MCU_WPU_S) -#define IO_MUX_GPIO18_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO18_MCU_WPU_S 3 -/** IO_MUX_GPIO18_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO18_MCU_IE (BIT(4)) -#define IO_MUX_GPIO18_MCU_IE_M (IO_MUX_GPIO18_MCU_IE_V << IO_MUX_GPIO18_MCU_IE_S) -#define IO_MUX_GPIO18_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO18_MCU_IE_S 4 -/** IO_MUX_GPIO18_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO18_MCU_DRV 0x00000003U -#define IO_MUX_GPIO18_MCU_DRV_M (IO_MUX_GPIO18_MCU_DRV_V << IO_MUX_GPIO18_MCU_DRV_S) -#define IO_MUX_GPIO18_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO18_MCU_DRV_S 5 -/** IO_MUX_GPIO18_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO18_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO18_FUN_WPD_M (IO_MUX_GPIO18_FUN_WPD_V << IO_MUX_GPIO18_FUN_WPD_S) -#define IO_MUX_GPIO18_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO18_FUN_WPD_S 7 -/** IO_MUX_GPIO18_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO18_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO18_FUN_WPU_M (IO_MUX_GPIO18_FUN_WPU_V << IO_MUX_GPIO18_FUN_WPU_S) -#define IO_MUX_GPIO18_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO18_FUN_WPU_S 8 -/** IO_MUX_GPIO18_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO18_FUN_IE (BIT(9)) -#define IO_MUX_GPIO18_FUN_IE_M (IO_MUX_GPIO18_FUN_IE_V << IO_MUX_GPIO18_FUN_IE_S) -#define IO_MUX_GPIO18_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO18_FUN_IE_S 9 -/** IO_MUX_GPIO18_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO18_FUN_DRV 0x00000003U -#define IO_MUX_GPIO18_FUN_DRV_M (IO_MUX_GPIO18_FUN_DRV_V << IO_MUX_GPIO18_FUN_DRV_S) -#define IO_MUX_GPIO18_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO18_FUN_DRV_S 10 -/** IO_MUX_GPIO18_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO18_MCU_SEL 0x00000007U -#define IO_MUX_GPIO18_MCU_SEL_M (IO_MUX_GPIO18_MCU_SEL_V << IO_MUX_GPIO18_MCU_SEL_S) -#define IO_MUX_GPIO18_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO18_MCU_SEL_S 12 -/** IO_MUX_GPIO18_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO18_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO18_FILTER_EN_M (IO_MUX_GPIO18_FILTER_EN_V << IO_MUX_GPIO18_FILTER_EN_S) -#define IO_MUX_GPIO18_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO18_FILTER_EN_S 15 - -/** IO_MUX_gpio19_REG register - * iomux control register for gpio19 - */ -#define IO_MUX_GPIO19_REG (DR_REG_IO_MUX_BASE + 0x50) -/** IO_MUX_GPIO19_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_OE (BIT(0)) -#define IO_MUX_GPIO19_MCU_OE_M (IO_MUX_GPIO19_MCU_OE_V << IO_MUX_GPIO19_MCU_OE_S) -#define IO_MUX_GPIO19_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO19_MCU_OE_S 0 -/** IO_MUX_GPIO19_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO19_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO19_SLP_SEL_M (IO_MUX_GPIO19_SLP_SEL_V << IO_MUX_GPIO19_SLP_SEL_S) -#define IO_MUX_GPIO19_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO19_SLP_SEL_S 1 -/** IO_MUX_GPIO19_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO19_MCU_WPD_M (IO_MUX_GPIO19_MCU_WPD_V << IO_MUX_GPIO19_MCU_WPD_S) -#define IO_MUX_GPIO19_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO19_MCU_WPD_S 2 -/** IO_MUX_GPIO19_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO19_MCU_WPU_M (IO_MUX_GPIO19_MCU_WPU_V << IO_MUX_GPIO19_MCU_WPU_S) -#define IO_MUX_GPIO19_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO19_MCU_WPU_S 3 -/** IO_MUX_GPIO19_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO19_MCU_IE (BIT(4)) -#define IO_MUX_GPIO19_MCU_IE_M (IO_MUX_GPIO19_MCU_IE_V << IO_MUX_GPIO19_MCU_IE_S) -#define IO_MUX_GPIO19_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO19_MCU_IE_S 4 -/** IO_MUX_GPIO19_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO19_MCU_DRV 0x00000003U -#define IO_MUX_GPIO19_MCU_DRV_M (IO_MUX_GPIO19_MCU_DRV_V << IO_MUX_GPIO19_MCU_DRV_S) -#define IO_MUX_GPIO19_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO19_MCU_DRV_S 5 -/** IO_MUX_GPIO19_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO19_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO19_FUN_WPD_M (IO_MUX_GPIO19_FUN_WPD_V << IO_MUX_GPIO19_FUN_WPD_S) -#define IO_MUX_GPIO19_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO19_FUN_WPD_S 7 -/** IO_MUX_GPIO19_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO19_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO19_FUN_WPU_M (IO_MUX_GPIO19_FUN_WPU_V << IO_MUX_GPIO19_FUN_WPU_S) -#define IO_MUX_GPIO19_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO19_FUN_WPU_S 8 -/** IO_MUX_GPIO19_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO19_FUN_IE (BIT(9)) -#define IO_MUX_GPIO19_FUN_IE_M (IO_MUX_GPIO19_FUN_IE_V << IO_MUX_GPIO19_FUN_IE_S) -#define IO_MUX_GPIO19_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO19_FUN_IE_S 9 -/** IO_MUX_GPIO19_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO19_FUN_DRV 0x00000003U -#define IO_MUX_GPIO19_FUN_DRV_M (IO_MUX_GPIO19_FUN_DRV_V << IO_MUX_GPIO19_FUN_DRV_S) -#define IO_MUX_GPIO19_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO19_FUN_DRV_S 10 -/** IO_MUX_GPIO19_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO19_MCU_SEL 0x00000007U -#define IO_MUX_GPIO19_MCU_SEL_M (IO_MUX_GPIO19_MCU_SEL_V << IO_MUX_GPIO19_MCU_SEL_S) -#define IO_MUX_GPIO19_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO19_MCU_SEL_S 12 -/** IO_MUX_GPIO19_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO19_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO19_FILTER_EN_M (IO_MUX_GPIO19_FILTER_EN_V << IO_MUX_GPIO19_FILTER_EN_S) -#define IO_MUX_GPIO19_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO19_FILTER_EN_S 15 - -/** IO_MUX_gpio20_REG register - * iomux control register for gpio20 - */ -#define IO_MUX_GPIO20_REG (DR_REG_IO_MUX_BASE + 0x54) -/** IO_MUX_GPIO20_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_OE (BIT(0)) -#define IO_MUX_GPIO20_MCU_OE_M (IO_MUX_GPIO20_MCU_OE_V << IO_MUX_GPIO20_MCU_OE_S) -#define IO_MUX_GPIO20_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO20_MCU_OE_S 0 -/** IO_MUX_GPIO20_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO20_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO20_SLP_SEL_M (IO_MUX_GPIO20_SLP_SEL_V << IO_MUX_GPIO20_SLP_SEL_S) -#define IO_MUX_GPIO20_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO20_SLP_SEL_S 1 -/** IO_MUX_GPIO20_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO20_MCU_WPD_M (IO_MUX_GPIO20_MCU_WPD_V << IO_MUX_GPIO20_MCU_WPD_S) -#define IO_MUX_GPIO20_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO20_MCU_WPD_S 2 -/** IO_MUX_GPIO20_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO20_MCU_WPU_M (IO_MUX_GPIO20_MCU_WPU_V << IO_MUX_GPIO20_MCU_WPU_S) -#define IO_MUX_GPIO20_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO20_MCU_WPU_S 3 -/** IO_MUX_GPIO20_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO20_MCU_IE (BIT(4)) -#define IO_MUX_GPIO20_MCU_IE_M (IO_MUX_GPIO20_MCU_IE_V << IO_MUX_GPIO20_MCU_IE_S) -#define IO_MUX_GPIO20_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO20_MCU_IE_S 4 -/** IO_MUX_GPIO20_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO20_MCU_DRV 0x00000003U -#define IO_MUX_GPIO20_MCU_DRV_M (IO_MUX_GPIO20_MCU_DRV_V << IO_MUX_GPIO20_MCU_DRV_S) -#define IO_MUX_GPIO20_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO20_MCU_DRV_S 5 -/** IO_MUX_GPIO20_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO20_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO20_FUN_WPD_M (IO_MUX_GPIO20_FUN_WPD_V << IO_MUX_GPIO20_FUN_WPD_S) -#define IO_MUX_GPIO20_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO20_FUN_WPD_S 7 -/** IO_MUX_GPIO20_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO20_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO20_FUN_WPU_M (IO_MUX_GPIO20_FUN_WPU_V << IO_MUX_GPIO20_FUN_WPU_S) -#define IO_MUX_GPIO20_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO20_FUN_WPU_S 8 -/** IO_MUX_GPIO20_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO20_FUN_IE (BIT(9)) -#define IO_MUX_GPIO20_FUN_IE_M (IO_MUX_GPIO20_FUN_IE_V << IO_MUX_GPIO20_FUN_IE_S) -#define IO_MUX_GPIO20_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO20_FUN_IE_S 9 -/** IO_MUX_GPIO20_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO20_FUN_DRV 0x00000003U -#define IO_MUX_GPIO20_FUN_DRV_M (IO_MUX_GPIO20_FUN_DRV_V << IO_MUX_GPIO20_FUN_DRV_S) -#define IO_MUX_GPIO20_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO20_FUN_DRV_S 10 -/** IO_MUX_GPIO20_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO20_MCU_SEL 0x00000007U -#define IO_MUX_GPIO20_MCU_SEL_M (IO_MUX_GPIO20_MCU_SEL_V << IO_MUX_GPIO20_MCU_SEL_S) -#define IO_MUX_GPIO20_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO20_MCU_SEL_S 12 -/** IO_MUX_GPIO20_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO20_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO20_FILTER_EN_M (IO_MUX_GPIO20_FILTER_EN_V << IO_MUX_GPIO20_FILTER_EN_S) -#define IO_MUX_GPIO20_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO20_FILTER_EN_S 15 - -/** IO_MUX_gpio21_REG register - * iomux control register for gpio21 - */ -#define IO_MUX_GPIO21_REG (DR_REG_IO_MUX_BASE + 0x58) -/** IO_MUX_GPIO21_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_OE (BIT(0)) -#define IO_MUX_GPIO21_MCU_OE_M (IO_MUX_GPIO21_MCU_OE_V << IO_MUX_GPIO21_MCU_OE_S) -#define IO_MUX_GPIO21_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO21_MCU_OE_S 0 -/** IO_MUX_GPIO21_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO21_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO21_SLP_SEL_M (IO_MUX_GPIO21_SLP_SEL_V << IO_MUX_GPIO21_SLP_SEL_S) -#define IO_MUX_GPIO21_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO21_SLP_SEL_S 1 -/** IO_MUX_GPIO21_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO21_MCU_WPD_M (IO_MUX_GPIO21_MCU_WPD_V << IO_MUX_GPIO21_MCU_WPD_S) -#define IO_MUX_GPIO21_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO21_MCU_WPD_S 2 -/** IO_MUX_GPIO21_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO21_MCU_WPU_M (IO_MUX_GPIO21_MCU_WPU_V << IO_MUX_GPIO21_MCU_WPU_S) -#define IO_MUX_GPIO21_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO21_MCU_WPU_S 3 -/** IO_MUX_GPIO21_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO21_MCU_IE (BIT(4)) -#define IO_MUX_GPIO21_MCU_IE_M (IO_MUX_GPIO21_MCU_IE_V << IO_MUX_GPIO21_MCU_IE_S) -#define IO_MUX_GPIO21_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO21_MCU_IE_S 4 -/** IO_MUX_GPIO21_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO21_MCU_DRV 0x00000003U -#define IO_MUX_GPIO21_MCU_DRV_M (IO_MUX_GPIO21_MCU_DRV_V << IO_MUX_GPIO21_MCU_DRV_S) -#define IO_MUX_GPIO21_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO21_MCU_DRV_S 5 -/** IO_MUX_GPIO21_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO21_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO21_FUN_WPD_M (IO_MUX_GPIO21_FUN_WPD_V << IO_MUX_GPIO21_FUN_WPD_S) -#define IO_MUX_GPIO21_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO21_FUN_WPD_S 7 -/** IO_MUX_GPIO21_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO21_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO21_FUN_WPU_M (IO_MUX_GPIO21_FUN_WPU_V << IO_MUX_GPIO21_FUN_WPU_S) -#define IO_MUX_GPIO21_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO21_FUN_WPU_S 8 -/** IO_MUX_GPIO21_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO21_FUN_IE (BIT(9)) -#define IO_MUX_GPIO21_FUN_IE_M (IO_MUX_GPIO21_FUN_IE_V << IO_MUX_GPIO21_FUN_IE_S) -#define IO_MUX_GPIO21_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO21_FUN_IE_S 9 -/** IO_MUX_GPIO21_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO21_FUN_DRV 0x00000003U -#define IO_MUX_GPIO21_FUN_DRV_M (IO_MUX_GPIO21_FUN_DRV_V << IO_MUX_GPIO21_FUN_DRV_S) -#define IO_MUX_GPIO21_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO21_FUN_DRV_S 10 -/** IO_MUX_GPIO21_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO21_MCU_SEL 0x00000007U -#define IO_MUX_GPIO21_MCU_SEL_M (IO_MUX_GPIO21_MCU_SEL_V << IO_MUX_GPIO21_MCU_SEL_S) -#define IO_MUX_GPIO21_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO21_MCU_SEL_S 12 -/** IO_MUX_GPIO21_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO21_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO21_FILTER_EN_M (IO_MUX_GPIO21_FILTER_EN_V << IO_MUX_GPIO21_FILTER_EN_S) -#define IO_MUX_GPIO21_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO21_FILTER_EN_S 15 - -/** IO_MUX_gpio22_REG register - * iomux control register for gpio22 - */ -#define IO_MUX_GPIO22_REG (DR_REG_IO_MUX_BASE + 0x5c) -/** IO_MUX_GPIO22_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_OE (BIT(0)) -#define IO_MUX_GPIO22_MCU_OE_M (IO_MUX_GPIO22_MCU_OE_V << IO_MUX_GPIO22_MCU_OE_S) -#define IO_MUX_GPIO22_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO22_MCU_OE_S 0 -/** IO_MUX_GPIO22_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO22_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO22_SLP_SEL_M (IO_MUX_GPIO22_SLP_SEL_V << IO_MUX_GPIO22_SLP_SEL_S) -#define IO_MUX_GPIO22_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO22_SLP_SEL_S 1 -/** IO_MUX_GPIO22_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO22_MCU_WPD_M (IO_MUX_GPIO22_MCU_WPD_V << IO_MUX_GPIO22_MCU_WPD_S) -#define IO_MUX_GPIO22_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO22_MCU_WPD_S 2 -/** IO_MUX_GPIO22_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO22_MCU_WPU_M (IO_MUX_GPIO22_MCU_WPU_V << IO_MUX_GPIO22_MCU_WPU_S) -#define IO_MUX_GPIO22_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO22_MCU_WPU_S 3 -/** IO_MUX_GPIO22_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO22_MCU_IE (BIT(4)) -#define IO_MUX_GPIO22_MCU_IE_M (IO_MUX_GPIO22_MCU_IE_V << IO_MUX_GPIO22_MCU_IE_S) -#define IO_MUX_GPIO22_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO22_MCU_IE_S 4 -/** IO_MUX_GPIO22_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO22_MCU_DRV 0x00000003U -#define IO_MUX_GPIO22_MCU_DRV_M (IO_MUX_GPIO22_MCU_DRV_V << IO_MUX_GPIO22_MCU_DRV_S) -#define IO_MUX_GPIO22_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO22_MCU_DRV_S 5 -/** IO_MUX_GPIO22_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO22_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO22_FUN_WPD_M (IO_MUX_GPIO22_FUN_WPD_V << IO_MUX_GPIO22_FUN_WPD_S) -#define IO_MUX_GPIO22_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO22_FUN_WPD_S 7 -/** IO_MUX_GPIO22_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO22_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO22_FUN_WPU_M (IO_MUX_GPIO22_FUN_WPU_V << IO_MUX_GPIO22_FUN_WPU_S) -#define IO_MUX_GPIO22_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO22_FUN_WPU_S 8 -/** IO_MUX_GPIO22_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO22_FUN_IE (BIT(9)) -#define IO_MUX_GPIO22_FUN_IE_M (IO_MUX_GPIO22_FUN_IE_V << IO_MUX_GPIO22_FUN_IE_S) -#define IO_MUX_GPIO22_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO22_FUN_IE_S 9 -/** IO_MUX_GPIO22_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO22_FUN_DRV 0x00000003U -#define IO_MUX_GPIO22_FUN_DRV_M (IO_MUX_GPIO22_FUN_DRV_V << IO_MUX_GPIO22_FUN_DRV_S) -#define IO_MUX_GPIO22_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO22_FUN_DRV_S 10 -/** IO_MUX_GPIO22_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO22_MCU_SEL 0x00000007U -#define IO_MUX_GPIO22_MCU_SEL_M (IO_MUX_GPIO22_MCU_SEL_V << IO_MUX_GPIO22_MCU_SEL_S) -#define IO_MUX_GPIO22_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO22_MCU_SEL_S 12 -/** IO_MUX_GPIO22_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO22_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO22_FILTER_EN_M (IO_MUX_GPIO22_FILTER_EN_V << IO_MUX_GPIO22_FILTER_EN_S) -#define IO_MUX_GPIO22_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO22_FILTER_EN_S 15 - -/** IO_MUX_gpio23_REG register - * iomux control register for gpio23 - */ -#define IO_MUX_GPIO23_REG (DR_REG_IO_MUX_BASE + 0x60) -/** IO_MUX_GPIO23_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_OE (BIT(0)) -#define IO_MUX_GPIO23_MCU_OE_M (IO_MUX_GPIO23_MCU_OE_V << IO_MUX_GPIO23_MCU_OE_S) -#define IO_MUX_GPIO23_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO23_MCU_OE_S 0 -/** IO_MUX_GPIO23_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO23_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO23_SLP_SEL_M (IO_MUX_GPIO23_SLP_SEL_V << IO_MUX_GPIO23_SLP_SEL_S) -#define IO_MUX_GPIO23_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO23_SLP_SEL_S 1 -/** IO_MUX_GPIO23_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO23_MCU_WPD_M (IO_MUX_GPIO23_MCU_WPD_V << IO_MUX_GPIO23_MCU_WPD_S) -#define IO_MUX_GPIO23_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO23_MCU_WPD_S 2 -/** IO_MUX_GPIO23_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO23_MCU_WPU_M (IO_MUX_GPIO23_MCU_WPU_V << IO_MUX_GPIO23_MCU_WPU_S) -#define IO_MUX_GPIO23_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO23_MCU_WPU_S 3 -/** IO_MUX_GPIO23_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO23_MCU_IE (BIT(4)) -#define IO_MUX_GPIO23_MCU_IE_M (IO_MUX_GPIO23_MCU_IE_V << IO_MUX_GPIO23_MCU_IE_S) -#define IO_MUX_GPIO23_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO23_MCU_IE_S 4 -/** IO_MUX_GPIO23_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO23_MCU_DRV 0x00000003U -#define IO_MUX_GPIO23_MCU_DRV_M (IO_MUX_GPIO23_MCU_DRV_V << IO_MUX_GPIO23_MCU_DRV_S) -#define IO_MUX_GPIO23_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO23_MCU_DRV_S 5 -/** IO_MUX_GPIO23_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO23_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO23_FUN_WPD_M (IO_MUX_GPIO23_FUN_WPD_V << IO_MUX_GPIO23_FUN_WPD_S) -#define IO_MUX_GPIO23_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO23_FUN_WPD_S 7 -/** IO_MUX_GPIO23_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO23_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO23_FUN_WPU_M (IO_MUX_GPIO23_FUN_WPU_V << IO_MUX_GPIO23_FUN_WPU_S) -#define IO_MUX_GPIO23_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO23_FUN_WPU_S 8 -/** IO_MUX_GPIO23_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO23_FUN_IE (BIT(9)) -#define IO_MUX_GPIO23_FUN_IE_M (IO_MUX_GPIO23_FUN_IE_V << IO_MUX_GPIO23_FUN_IE_S) -#define IO_MUX_GPIO23_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO23_FUN_IE_S 9 -/** IO_MUX_GPIO23_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO23_FUN_DRV 0x00000003U -#define IO_MUX_GPIO23_FUN_DRV_M (IO_MUX_GPIO23_FUN_DRV_V << IO_MUX_GPIO23_FUN_DRV_S) -#define IO_MUX_GPIO23_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO23_FUN_DRV_S 10 -/** IO_MUX_GPIO23_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO23_MCU_SEL 0x00000007U -#define IO_MUX_GPIO23_MCU_SEL_M (IO_MUX_GPIO23_MCU_SEL_V << IO_MUX_GPIO23_MCU_SEL_S) -#define IO_MUX_GPIO23_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO23_MCU_SEL_S 12 -/** IO_MUX_GPIO23_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO23_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO23_FILTER_EN_M (IO_MUX_GPIO23_FILTER_EN_V << IO_MUX_GPIO23_FILTER_EN_S) -#define IO_MUX_GPIO23_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO23_FILTER_EN_S 15 - -/** IO_MUX_gpio24_REG register - * iomux control register for gpio24 - */ -#define IO_MUX_GPIO24_REG (DR_REG_IO_MUX_BASE + 0x64) -/** IO_MUX_GPIO24_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_OE (BIT(0)) -#define IO_MUX_GPIO24_MCU_OE_M (IO_MUX_GPIO24_MCU_OE_V << IO_MUX_GPIO24_MCU_OE_S) -#define IO_MUX_GPIO24_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO24_MCU_OE_S 0 -/** IO_MUX_GPIO24_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO24_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO24_SLP_SEL_M (IO_MUX_GPIO24_SLP_SEL_V << IO_MUX_GPIO24_SLP_SEL_S) -#define IO_MUX_GPIO24_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO24_SLP_SEL_S 1 -/** IO_MUX_GPIO24_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO24_MCU_WPD_M (IO_MUX_GPIO24_MCU_WPD_V << IO_MUX_GPIO24_MCU_WPD_S) -#define IO_MUX_GPIO24_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO24_MCU_WPD_S 2 -/** IO_MUX_GPIO24_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO24_MCU_WPU_M (IO_MUX_GPIO24_MCU_WPU_V << IO_MUX_GPIO24_MCU_WPU_S) -#define IO_MUX_GPIO24_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO24_MCU_WPU_S 3 -/** IO_MUX_GPIO24_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO24_MCU_IE (BIT(4)) -#define IO_MUX_GPIO24_MCU_IE_M (IO_MUX_GPIO24_MCU_IE_V << IO_MUX_GPIO24_MCU_IE_S) -#define IO_MUX_GPIO24_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO24_MCU_IE_S 4 -/** IO_MUX_GPIO24_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO24_MCU_DRV 0x00000003U -#define IO_MUX_GPIO24_MCU_DRV_M (IO_MUX_GPIO24_MCU_DRV_V << IO_MUX_GPIO24_MCU_DRV_S) -#define IO_MUX_GPIO24_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO24_MCU_DRV_S 5 -/** IO_MUX_GPIO24_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO24_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO24_FUN_WPD_M (IO_MUX_GPIO24_FUN_WPD_V << IO_MUX_GPIO24_FUN_WPD_S) -#define IO_MUX_GPIO24_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO24_FUN_WPD_S 7 -/** IO_MUX_GPIO24_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO24_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO24_FUN_WPU_M (IO_MUX_GPIO24_FUN_WPU_V << IO_MUX_GPIO24_FUN_WPU_S) -#define IO_MUX_GPIO24_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO24_FUN_WPU_S 8 -/** IO_MUX_GPIO24_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO24_FUN_IE (BIT(9)) -#define IO_MUX_GPIO24_FUN_IE_M (IO_MUX_GPIO24_FUN_IE_V << IO_MUX_GPIO24_FUN_IE_S) -#define IO_MUX_GPIO24_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO24_FUN_IE_S 9 -/** IO_MUX_GPIO24_FUN_DRV : R/W; bitpos: [11:10]; default: 3; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO24_FUN_DRV 0x00000003U -#define IO_MUX_GPIO24_FUN_DRV_M (IO_MUX_GPIO24_FUN_DRV_V << IO_MUX_GPIO24_FUN_DRV_S) -#define IO_MUX_GPIO24_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO24_FUN_DRV_S 10 -/** IO_MUX_GPIO24_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO24_MCU_SEL 0x00000007U -#define IO_MUX_GPIO24_MCU_SEL_M (IO_MUX_GPIO24_MCU_SEL_V << IO_MUX_GPIO24_MCU_SEL_S) -#define IO_MUX_GPIO24_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO24_MCU_SEL_S 12 -/** IO_MUX_GPIO24_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO24_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO24_FILTER_EN_M (IO_MUX_GPIO24_FILTER_EN_V << IO_MUX_GPIO24_FILTER_EN_S) -#define IO_MUX_GPIO24_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO24_FILTER_EN_S 15 - -/** IO_MUX_gpio25_REG register - * iomux control register for gpio25 - */ -#define IO_MUX_GPIO25_REG (DR_REG_IO_MUX_BASE + 0x68) -/** IO_MUX_GPIO25_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_OE (BIT(0)) -#define IO_MUX_GPIO25_MCU_OE_M (IO_MUX_GPIO25_MCU_OE_V << IO_MUX_GPIO25_MCU_OE_S) -#define IO_MUX_GPIO25_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO25_MCU_OE_S 0 -/** IO_MUX_GPIO25_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO25_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO25_SLP_SEL_M (IO_MUX_GPIO25_SLP_SEL_V << IO_MUX_GPIO25_SLP_SEL_S) -#define IO_MUX_GPIO25_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO25_SLP_SEL_S 1 -/** IO_MUX_GPIO25_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO25_MCU_WPD_M (IO_MUX_GPIO25_MCU_WPD_V << IO_MUX_GPIO25_MCU_WPD_S) -#define IO_MUX_GPIO25_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO25_MCU_WPD_S 2 -/** IO_MUX_GPIO25_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO25_MCU_WPU_M (IO_MUX_GPIO25_MCU_WPU_V << IO_MUX_GPIO25_MCU_WPU_S) -#define IO_MUX_GPIO25_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO25_MCU_WPU_S 3 -/** IO_MUX_GPIO25_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO25_MCU_IE (BIT(4)) -#define IO_MUX_GPIO25_MCU_IE_M (IO_MUX_GPIO25_MCU_IE_V << IO_MUX_GPIO25_MCU_IE_S) -#define IO_MUX_GPIO25_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO25_MCU_IE_S 4 -/** IO_MUX_GPIO25_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO25_MCU_DRV 0x00000003U -#define IO_MUX_GPIO25_MCU_DRV_M (IO_MUX_GPIO25_MCU_DRV_V << IO_MUX_GPIO25_MCU_DRV_S) -#define IO_MUX_GPIO25_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO25_MCU_DRV_S 5 -/** IO_MUX_GPIO25_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO25_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO25_FUN_WPD_M (IO_MUX_GPIO25_FUN_WPD_V << IO_MUX_GPIO25_FUN_WPD_S) -#define IO_MUX_GPIO25_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO25_FUN_WPD_S 7 -/** IO_MUX_GPIO25_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO25_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO25_FUN_WPU_M (IO_MUX_GPIO25_FUN_WPU_V << IO_MUX_GPIO25_FUN_WPU_S) -#define IO_MUX_GPIO25_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO25_FUN_WPU_S 8 -/** IO_MUX_GPIO25_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO25_FUN_IE (BIT(9)) -#define IO_MUX_GPIO25_FUN_IE_M (IO_MUX_GPIO25_FUN_IE_V << IO_MUX_GPIO25_FUN_IE_S) -#define IO_MUX_GPIO25_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO25_FUN_IE_S 9 -/** IO_MUX_GPIO25_FUN_DRV : R/W; bitpos: [11:10]; default: 3; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO25_FUN_DRV 0x00000003U -#define IO_MUX_GPIO25_FUN_DRV_M (IO_MUX_GPIO25_FUN_DRV_V << IO_MUX_GPIO25_FUN_DRV_S) -#define IO_MUX_GPIO25_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO25_FUN_DRV_S 10 -/** IO_MUX_GPIO25_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO25_MCU_SEL 0x00000007U -#define IO_MUX_GPIO25_MCU_SEL_M (IO_MUX_GPIO25_MCU_SEL_V << IO_MUX_GPIO25_MCU_SEL_S) -#define IO_MUX_GPIO25_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO25_MCU_SEL_S 12 -/** IO_MUX_GPIO25_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO25_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO25_FILTER_EN_M (IO_MUX_GPIO25_FILTER_EN_V << IO_MUX_GPIO25_FILTER_EN_S) -#define IO_MUX_GPIO25_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO25_FILTER_EN_S 15 - -/** IO_MUX_gpio26_REG register - * iomux control register for gpio26 - */ -#define IO_MUX_GPIO26_REG (DR_REG_IO_MUX_BASE + 0x6c) -/** IO_MUX_GPIO26_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_OE (BIT(0)) -#define IO_MUX_GPIO26_MCU_OE_M (IO_MUX_GPIO26_MCU_OE_V << IO_MUX_GPIO26_MCU_OE_S) -#define IO_MUX_GPIO26_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO26_MCU_OE_S 0 -/** IO_MUX_GPIO26_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO26_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO26_SLP_SEL_M (IO_MUX_GPIO26_SLP_SEL_V << IO_MUX_GPIO26_SLP_SEL_S) -#define IO_MUX_GPIO26_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO26_SLP_SEL_S 1 -/** IO_MUX_GPIO26_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO26_MCU_WPD_M (IO_MUX_GPIO26_MCU_WPD_V << IO_MUX_GPIO26_MCU_WPD_S) -#define IO_MUX_GPIO26_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO26_MCU_WPD_S 2 -/** IO_MUX_GPIO26_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO26_MCU_WPU_M (IO_MUX_GPIO26_MCU_WPU_V << IO_MUX_GPIO26_MCU_WPU_S) -#define IO_MUX_GPIO26_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO26_MCU_WPU_S 3 -/** IO_MUX_GPIO26_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO26_MCU_IE (BIT(4)) -#define IO_MUX_GPIO26_MCU_IE_M (IO_MUX_GPIO26_MCU_IE_V << IO_MUX_GPIO26_MCU_IE_S) -#define IO_MUX_GPIO26_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO26_MCU_IE_S 4 -/** IO_MUX_GPIO26_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO26_MCU_DRV 0x00000003U -#define IO_MUX_GPIO26_MCU_DRV_M (IO_MUX_GPIO26_MCU_DRV_V << IO_MUX_GPIO26_MCU_DRV_S) -#define IO_MUX_GPIO26_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO26_MCU_DRV_S 5 -/** IO_MUX_GPIO26_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO26_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO26_FUN_WPD_M (IO_MUX_GPIO26_FUN_WPD_V << IO_MUX_GPIO26_FUN_WPD_S) -#define IO_MUX_GPIO26_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO26_FUN_WPD_S 7 -/** IO_MUX_GPIO26_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO26_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO26_FUN_WPU_M (IO_MUX_GPIO26_FUN_WPU_V << IO_MUX_GPIO26_FUN_WPU_S) -#define IO_MUX_GPIO26_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO26_FUN_WPU_S 8 -/** IO_MUX_GPIO26_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO26_FUN_IE (BIT(9)) -#define IO_MUX_GPIO26_FUN_IE_M (IO_MUX_GPIO26_FUN_IE_V << IO_MUX_GPIO26_FUN_IE_S) -#define IO_MUX_GPIO26_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO26_FUN_IE_S 9 -/** IO_MUX_GPIO26_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO26_FUN_DRV 0x00000003U -#define IO_MUX_GPIO26_FUN_DRV_M (IO_MUX_GPIO26_FUN_DRV_V << IO_MUX_GPIO26_FUN_DRV_S) -#define IO_MUX_GPIO26_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO26_FUN_DRV_S 10 -/** IO_MUX_GPIO26_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO26_MCU_SEL 0x00000007U -#define IO_MUX_GPIO26_MCU_SEL_M (IO_MUX_GPIO26_MCU_SEL_V << IO_MUX_GPIO26_MCU_SEL_S) -#define IO_MUX_GPIO26_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO26_MCU_SEL_S 12 -/** IO_MUX_GPIO26_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO26_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO26_FILTER_EN_M (IO_MUX_GPIO26_FILTER_EN_V << IO_MUX_GPIO26_FILTER_EN_S) -#define IO_MUX_GPIO26_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO26_FILTER_EN_S 15 - -/** IO_MUX_gpio27_REG register - * iomux control register for gpio27 - */ -#define IO_MUX_GPIO27_REG (DR_REG_IO_MUX_BASE + 0x70) -/** IO_MUX_GPIO27_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_OE (BIT(0)) -#define IO_MUX_GPIO27_MCU_OE_M (IO_MUX_GPIO27_MCU_OE_V << IO_MUX_GPIO27_MCU_OE_S) -#define IO_MUX_GPIO27_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO27_MCU_OE_S 0 -/** IO_MUX_GPIO27_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO27_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO27_SLP_SEL_M (IO_MUX_GPIO27_SLP_SEL_V << IO_MUX_GPIO27_SLP_SEL_S) -#define IO_MUX_GPIO27_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO27_SLP_SEL_S 1 -/** IO_MUX_GPIO27_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO27_MCU_WPD_M (IO_MUX_GPIO27_MCU_WPD_V << IO_MUX_GPIO27_MCU_WPD_S) -#define IO_MUX_GPIO27_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO27_MCU_WPD_S 2 -/** IO_MUX_GPIO27_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO27_MCU_WPU_M (IO_MUX_GPIO27_MCU_WPU_V << IO_MUX_GPIO27_MCU_WPU_S) -#define IO_MUX_GPIO27_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO27_MCU_WPU_S 3 -/** IO_MUX_GPIO27_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO27_MCU_IE (BIT(4)) -#define IO_MUX_GPIO27_MCU_IE_M (IO_MUX_GPIO27_MCU_IE_V << IO_MUX_GPIO27_MCU_IE_S) -#define IO_MUX_GPIO27_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO27_MCU_IE_S 4 -/** IO_MUX_GPIO27_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO27_MCU_DRV 0x00000003U -#define IO_MUX_GPIO27_MCU_DRV_M (IO_MUX_GPIO27_MCU_DRV_V << IO_MUX_GPIO27_MCU_DRV_S) -#define IO_MUX_GPIO27_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO27_MCU_DRV_S 5 -/** IO_MUX_GPIO27_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO27_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO27_FUN_WPD_M (IO_MUX_GPIO27_FUN_WPD_V << IO_MUX_GPIO27_FUN_WPD_S) -#define IO_MUX_GPIO27_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO27_FUN_WPD_S 7 -/** IO_MUX_GPIO27_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO27_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO27_FUN_WPU_M (IO_MUX_GPIO27_FUN_WPU_V << IO_MUX_GPIO27_FUN_WPU_S) -#define IO_MUX_GPIO27_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO27_FUN_WPU_S 8 -/** IO_MUX_GPIO27_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO27_FUN_IE (BIT(9)) -#define IO_MUX_GPIO27_FUN_IE_M (IO_MUX_GPIO27_FUN_IE_V << IO_MUX_GPIO27_FUN_IE_S) -#define IO_MUX_GPIO27_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO27_FUN_IE_S 9 -/** IO_MUX_GPIO27_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO27_FUN_DRV 0x00000003U -#define IO_MUX_GPIO27_FUN_DRV_M (IO_MUX_GPIO27_FUN_DRV_V << IO_MUX_GPIO27_FUN_DRV_S) -#define IO_MUX_GPIO27_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO27_FUN_DRV_S 10 -/** IO_MUX_GPIO27_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO27_MCU_SEL 0x00000007U -#define IO_MUX_GPIO27_MCU_SEL_M (IO_MUX_GPIO27_MCU_SEL_V << IO_MUX_GPIO27_MCU_SEL_S) -#define IO_MUX_GPIO27_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO27_MCU_SEL_S 12 -/** IO_MUX_GPIO27_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO27_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO27_FILTER_EN_M (IO_MUX_GPIO27_FILTER_EN_V << IO_MUX_GPIO27_FILTER_EN_S) -#define IO_MUX_GPIO27_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO27_FILTER_EN_S 15 - -/** IO_MUX_gpio28_REG register - * iomux control register for gpio28 - */ -#define IO_MUX_GPIO28_REG (DR_REG_IO_MUX_BASE + 0x74) -/** IO_MUX_GPIO28_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_OE (BIT(0)) -#define IO_MUX_GPIO28_MCU_OE_M (IO_MUX_GPIO28_MCU_OE_V << IO_MUX_GPIO28_MCU_OE_S) -#define IO_MUX_GPIO28_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO28_MCU_OE_S 0 -/** IO_MUX_GPIO28_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO28_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO28_SLP_SEL_M (IO_MUX_GPIO28_SLP_SEL_V << IO_MUX_GPIO28_SLP_SEL_S) -#define IO_MUX_GPIO28_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO28_SLP_SEL_S 1 -/** IO_MUX_GPIO28_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO28_MCU_WPD_M (IO_MUX_GPIO28_MCU_WPD_V << IO_MUX_GPIO28_MCU_WPD_S) -#define IO_MUX_GPIO28_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO28_MCU_WPD_S 2 -/** IO_MUX_GPIO28_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO28_MCU_WPU_M (IO_MUX_GPIO28_MCU_WPU_V << IO_MUX_GPIO28_MCU_WPU_S) -#define IO_MUX_GPIO28_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO28_MCU_WPU_S 3 -/** IO_MUX_GPIO28_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO28_MCU_IE (BIT(4)) -#define IO_MUX_GPIO28_MCU_IE_M (IO_MUX_GPIO28_MCU_IE_V << IO_MUX_GPIO28_MCU_IE_S) -#define IO_MUX_GPIO28_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO28_MCU_IE_S 4 -/** IO_MUX_GPIO28_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO28_MCU_DRV 0x00000003U -#define IO_MUX_GPIO28_MCU_DRV_M (IO_MUX_GPIO28_MCU_DRV_V << IO_MUX_GPIO28_MCU_DRV_S) -#define IO_MUX_GPIO28_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO28_MCU_DRV_S 5 -/** IO_MUX_GPIO28_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO28_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO28_FUN_WPD_M (IO_MUX_GPIO28_FUN_WPD_V << IO_MUX_GPIO28_FUN_WPD_S) -#define IO_MUX_GPIO28_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO28_FUN_WPD_S 7 -/** IO_MUX_GPIO28_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO28_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO28_FUN_WPU_M (IO_MUX_GPIO28_FUN_WPU_V << IO_MUX_GPIO28_FUN_WPU_S) -#define IO_MUX_GPIO28_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO28_FUN_WPU_S 8 -/** IO_MUX_GPIO28_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO28_FUN_IE (BIT(9)) -#define IO_MUX_GPIO28_FUN_IE_M (IO_MUX_GPIO28_FUN_IE_V << IO_MUX_GPIO28_FUN_IE_S) -#define IO_MUX_GPIO28_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO28_FUN_IE_S 9 -/** IO_MUX_GPIO28_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO28_FUN_DRV 0x00000003U -#define IO_MUX_GPIO28_FUN_DRV_M (IO_MUX_GPIO28_FUN_DRV_V << IO_MUX_GPIO28_FUN_DRV_S) -#define IO_MUX_GPIO28_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO28_FUN_DRV_S 10 -/** IO_MUX_GPIO28_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO28_MCU_SEL 0x00000007U -#define IO_MUX_GPIO28_MCU_SEL_M (IO_MUX_GPIO28_MCU_SEL_V << IO_MUX_GPIO28_MCU_SEL_S) -#define IO_MUX_GPIO28_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO28_MCU_SEL_S 12 -/** IO_MUX_GPIO28_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO28_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO28_FILTER_EN_M (IO_MUX_GPIO28_FILTER_EN_V << IO_MUX_GPIO28_FILTER_EN_S) -#define IO_MUX_GPIO28_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO28_FILTER_EN_S 15 - -/** IO_MUX_gpio29_REG register - * iomux control register for gpio29 - */ -#define IO_MUX_GPIO29_REG (DR_REG_IO_MUX_BASE + 0x78) -/** IO_MUX_GPIO29_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_OE (BIT(0)) -#define IO_MUX_GPIO29_MCU_OE_M (IO_MUX_GPIO29_MCU_OE_V << IO_MUX_GPIO29_MCU_OE_S) -#define IO_MUX_GPIO29_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO29_MCU_OE_S 0 -/** IO_MUX_GPIO29_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO29_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO29_SLP_SEL_M (IO_MUX_GPIO29_SLP_SEL_V << IO_MUX_GPIO29_SLP_SEL_S) -#define IO_MUX_GPIO29_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO29_SLP_SEL_S 1 -/** IO_MUX_GPIO29_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO29_MCU_WPD_M (IO_MUX_GPIO29_MCU_WPD_V << IO_MUX_GPIO29_MCU_WPD_S) -#define IO_MUX_GPIO29_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO29_MCU_WPD_S 2 -/** IO_MUX_GPIO29_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO29_MCU_WPU_M (IO_MUX_GPIO29_MCU_WPU_V << IO_MUX_GPIO29_MCU_WPU_S) -#define IO_MUX_GPIO29_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO29_MCU_WPU_S 3 -/** IO_MUX_GPIO29_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO29_MCU_IE (BIT(4)) -#define IO_MUX_GPIO29_MCU_IE_M (IO_MUX_GPIO29_MCU_IE_V << IO_MUX_GPIO29_MCU_IE_S) -#define IO_MUX_GPIO29_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO29_MCU_IE_S 4 -/** IO_MUX_GPIO29_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO29_MCU_DRV 0x00000003U -#define IO_MUX_GPIO29_MCU_DRV_M (IO_MUX_GPIO29_MCU_DRV_V << IO_MUX_GPIO29_MCU_DRV_S) -#define IO_MUX_GPIO29_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO29_MCU_DRV_S 5 -/** IO_MUX_GPIO29_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO29_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO29_FUN_WPD_M (IO_MUX_GPIO29_FUN_WPD_V << IO_MUX_GPIO29_FUN_WPD_S) -#define IO_MUX_GPIO29_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO29_FUN_WPD_S 7 -/** IO_MUX_GPIO29_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO29_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO29_FUN_WPU_M (IO_MUX_GPIO29_FUN_WPU_V << IO_MUX_GPIO29_FUN_WPU_S) -#define IO_MUX_GPIO29_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO29_FUN_WPU_S 8 -/** IO_MUX_GPIO29_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO29_FUN_IE (BIT(9)) -#define IO_MUX_GPIO29_FUN_IE_M (IO_MUX_GPIO29_FUN_IE_V << IO_MUX_GPIO29_FUN_IE_S) -#define IO_MUX_GPIO29_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO29_FUN_IE_S 9 -/** IO_MUX_GPIO29_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO29_FUN_DRV 0x00000003U -#define IO_MUX_GPIO29_FUN_DRV_M (IO_MUX_GPIO29_FUN_DRV_V << IO_MUX_GPIO29_FUN_DRV_S) -#define IO_MUX_GPIO29_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO29_FUN_DRV_S 10 -/** IO_MUX_GPIO29_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO29_MCU_SEL 0x00000007U -#define IO_MUX_GPIO29_MCU_SEL_M (IO_MUX_GPIO29_MCU_SEL_V << IO_MUX_GPIO29_MCU_SEL_S) -#define IO_MUX_GPIO29_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO29_MCU_SEL_S 12 -/** IO_MUX_GPIO29_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO29_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO29_FILTER_EN_M (IO_MUX_GPIO29_FILTER_EN_V << IO_MUX_GPIO29_FILTER_EN_S) -#define IO_MUX_GPIO29_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO29_FILTER_EN_S 15 - -/** IO_MUX_gpio30_REG register - * iomux control register for gpio30 - */ -#define IO_MUX_GPIO30_REG (DR_REG_IO_MUX_BASE + 0x7c) -/** IO_MUX_GPIO30_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_OE (BIT(0)) -#define IO_MUX_GPIO30_MCU_OE_M (IO_MUX_GPIO30_MCU_OE_V << IO_MUX_GPIO30_MCU_OE_S) -#define IO_MUX_GPIO30_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO30_MCU_OE_S 0 -/** IO_MUX_GPIO30_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO30_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO30_SLP_SEL_M (IO_MUX_GPIO30_SLP_SEL_V << IO_MUX_GPIO30_SLP_SEL_S) -#define IO_MUX_GPIO30_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO30_SLP_SEL_S 1 -/** IO_MUX_GPIO30_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO30_MCU_WPD_M (IO_MUX_GPIO30_MCU_WPD_V << IO_MUX_GPIO30_MCU_WPD_S) -#define IO_MUX_GPIO30_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO30_MCU_WPD_S 2 -/** IO_MUX_GPIO30_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO30_MCU_WPU_M (IO_MUX_GPIO30_MCU_WPU_V << IO_MUX_GPIO30_MCU_WPU_S) -#define IO_MUX_GPIO30_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO30_MCU_WPU_S 3 -/** IO_MUX_GPIO30_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO30_MCU_IE (BIT(4)) -#define IO_MUX_GPIO30_MCU_IE_M (IO_MUX_GPIO30_MCU_IE_V << IO_MUX_GPIO30_MCU_IE_S) -#define IO_MUX_GPIO30_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO30_MCU_IE_S 4 -/** IO_MUX_GPIO30_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO30_MCU_DRV 0x00000003U -#define IO_MUX_GPIO30_MCU_DRV_M (IO_MUX_GPIO30_MCU_DRV_V << IO_MUX_GPIO30_MCU_DRV_S) -#define IO_MUX_GPIO30_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO30_MCU_DRV_S 5 -/** IO_MUX_GPIO30_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO30_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO30_FUN_WPD_M (IO_MUX_GPIO30_FUN_WPD_V << IO_MUX_GPIO30_FUN_WPD_S) -#define IO_MUX_GPIO30_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO30_FUN_WPD_S 7 -/** IO_MUX_GPIO30_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO30_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO30_FUN_WPU_M (IO_MUX_GPIO30_FUN_WPU_V << IO_MUX_GPIO30_FUN_WPU_S) -#define IO_MUX_GPIO30_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO30_FUN_WPU_S 8 -/** IO_MUX_GPIO30_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO30_FUN_IE (BIT(9)) -#define IO_MUX_GPIO30_FUN_IE_M (IO_MUX_GPIO30_FUN_IE_V << IO_MUX_GPIO30_FUN_IE_S) -#define IO_MUX_GPIO30_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO30_FUN_IE_S 9 -/** IO_MUX_GPIO30_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO30_FUN_DRV 0x00000003U -#define IO_MUX_GPIO30_FUN_DRV_M (IO_MUX_GPIO30_FUN_DRV_V << IO_MUX_GPIO30_FUN_DRV_S) -#define IO_MUX_GPIO30_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO30_FUN_DRV_S 10 -/** IO_MUX_GPIO30_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO30_MCU_SEL 0x00000007U -#define IO_MUX_GPIO30_MCU_SEL_M (IO_MUX_GPIO30_MCU_SEL_V << IO_MUX_GPIO30_MCU_SEL_S) -#define IO_MUX_GPIO30_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO30_MCU_SEL_S 12 -/** IO_MUX_GPIO30_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO30_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO30_FILTER_EN_M (IO_MUX_GPIO30_FILTER_EN_V << IO_MUX_GPIO30_FILTER_EN_S) -#define IO_MUX_GPIO30_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO30_FILTER_EN_S 15 - -/** IO_MUX_gpio31_REG register - * iomux control register for gpio31 - */ -#define IO_MUX_GPIO31_REG (DR_REG_IO_MUX_BASE + 0x80) -/** IO_MUX_GPIO31_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_OE (BIT(0)) -#define IO_MUX_GPIO31_MCU_OE_M (IO_MUX_GPIO31_MCU_OE_V << IO_MUX_GPIO31_MCU_OE_S) -#define IO_MUX_GPIO31_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO31_MCU_OE_S 0 -/** IO_MUX_GPIO31_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO31_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO31_SLP_SEL_M (IO_MUX_GPIO31_SLP_SEL_V << IO_MUX_GPIO31_SLP_SEL_S) -#define IO_MUX_GPIO31_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO31_SLP_SEL_S 1 -/** IO_MUX_GPIO31_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO31_MCU_WPD_M (IO_MUX_GPIO31_MCU_WPD_V << IO_MUX_GPIO31_MCU_WPD_S) -#define IO_MUX_GPIO31_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO31_MCU_WPD_S 2 -/** IO_MUX_GPIO31_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO31_MCU_WPU_M (IO_MUX_GPIO31_MCU_WPU_V << IO_MUX_GPIO31_MCU_WPU_S) -#define IO_MUX_GPIO31_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO31_MCU_WPU_S 3 -/** IO_MUX_GPIO31_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO31_MCU_IE (BIT(4)) -#define IO_MUX_GPIO31_MCU_IE_M (IO_MUX_GPIO31_MCU_IE_V << IO_MUX_GPIO31_MCU_IE_S) -#define IO_MUX_GPIO31_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO31_MCU_IE_S 4 -/** IO_MUX_GPIO31_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO31_MCU_DRV 0x00000003U -#define IO_MUX_GPIO31_MCU_DRV_M (IO_MUX_GPIO31_MCU_DRV_V << IO_MUX_GPIO31_MCU_DRV_S) -#define IO_MUX_GPIO31_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO31_MCU_DRV_S 5 -/** IO_MUX_GPIO31_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO31_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO31_FUN_WPD_M (IO_MUX_GPIO31_FUN_WPD_V << IO_MUX_GPIO31_FUN_WPD_S) -#define IO_MUX_GPIO31_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO31_FUN_WPD_S 7 -/** IO_MUX_GPIO31_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO31_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO31_FUN_WPU_M (IO_MUX_GPIO31_FUN_WPU_V << IO_MUX_GPIO31_FUN_WPU_S) -#define IO_MUX_GPIO31_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO31_FUN_WPU_S 8 -/** IO_MUX_GPIO31_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO31_FUN_IE (BIT(9)) -#define IO_MUX_GPIO31_FUN_IE_M (IO_MUX_GPIO31_FUN_IE_V << IO_MUX_GPIO31_FUN_IE_S) -#define IO_MUX_GPIO31_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO31_FUN_IE_S 9 -/** IO_MUX_GPIO31_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO31_FUN_DRV 0x00000003U -#define IO_MUX_GPIO31_FUN_DRV_M (IO_MUX_GPIO31_FUN_DRV_V << IO_MUX_GPIO31_FUN_DRV_S) -#define IO_MUX_GPIO31_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO31_FUN_DRV_S 10 -/** IO_MUX_GPIO31_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO31_MCU_SEL 0x00000007U -#define IO_MUX_GPIO31_MCU_SEL_M (IO_MUX_GPIO31_MCU_SEL_V << IO_MUX_GPIO31_MCU_SEL_S) -#define IO_MUX_GPIO31_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO31_MCU_SEL_S 12 -/** IO_MUX_GPIO31_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO31_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO31_FILTER_EN_M (IO_MUX_GPIO31_FILTER_EN_V << IO_MUX_GPIO31_FILTER_EN_S) -#define IO_MUX_GPIO31_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO31_FILTER_EN_S 15 - -/** IO_MUX_gpio32_REG register - * iomux control register for gpio32 - */ -#define IO_MUX_GPIO32_REG (DR_REG_IO_MUX_BASE + 0x84) -/** IO_MUX_GPIO32_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_OE (BIT(0)) -#define IO_MUX_GPIO32_MCU_OE_M (IO_MUX_GPIO32_MCU_OE_V << IO_MUX_GPIO32_MCU_OE_S) -#define IO_MUX_GPIO32_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO32_MCU_OE_S 0 -/** IO_MUX_GPIO32_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO32_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO32_SLP_SEL_M (IO_MUX_GPIO32_SLP_SEL_V << IO_MUX_GPIO32_SLP_SEL_S) -#define IO_MUX_GPIO32_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO32_SLP_SEL_S 1 -/** IO_MUX_GPIO32_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO32_MCU_WPD_M (IO_MUX_GPIO32_MCU_WPD_V << IO_MUX_GPIO32_MCU_WPD_S) -#define IO_MUX_GPIO32_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO32_MCU_WPD_S 2 -/** IO_MUX_GPIO32_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO32_MCU_WPU_M (IO_MUX_GPIO32_MCU_WPU_V << IO_MUX_GPIO32_MCU_WPU_S) -#define IO_MUX_GPIO32_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO32_MCU_WPU_S 3 -/** IO_MUX_GPIO32_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO32_MCU_IE (BIT(4)) -#define IO_MUX_GPIO32_MCU_IE_M (IO_MUX_GPIO32_MCU_IE_V << IO_MUX_GPIO32_MCU_IE_S) -#define IO_MUX_GPIO32_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO32_MCU_IE_S 4 -/** IO_MUX_GPIO32_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO32_MCU_DRV 0x00000003U -#define IO_MUX_GPIO32_MCU_DRV_M (IO_MUX_GPIO32_MCU_DRV_V << IO_MUX_GPIO32_MCU_DRV_S) -#define IO_MUX_GPIO32_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO32_MCU_DRV_S 5 -/** IO_MUX_GPIO32_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO32_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO32_FUN_WPD_M (IO_MUX_GPIO32_FUN_WPD_V << IO_MUX_GPIO32_FUN_WPD_S) -#define IO_MUX_GPIO32_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO32_FUN_WPD_S 7 -/** IO_MUX_GPIO32_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO32_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO32_FUN_WPU_M (IO_MUX_GPIO32_FUN_WPU_V << IO_MUX_GPIO32_FUN_WPU_S) -#define IO_MUX_GPIO32_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO32_FUN_WPU_S 8 -/** IO_MUX_GPIO32_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO32_FUN_IE (BIT(9)) -#define IO_MUX_GPIO32_FUN_IE_M (IO_MUX_GPIO32_FUN_IE_V << IO_MUX_GPIO32_FUN_IE_S) -#define IO_MUX_GPIO32_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO32_FUN_IE_S 9 -/** IO_MUX_GPIO32_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO32_FUN_DRV 0x00000003U -#define IO_MUX_GPIO32_FUN_DRV_M (IO_MUX_GPIO32_FUN_DRV_V << IO_MUX_GPIO32_FUN_DRV_S) -#define IO_MUX_GPIO32_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO32_FUN_DRV_S 10 -/** IO_MUX_GPIO32_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO32_MCU_SEL 0x00000007U -#define IO_MUX_GPIO32_MCU_SEL_M (IO_MUX_GPIO32_MCU_SEL_V << IO_MUX_GPIO32_MCU_SEL_S) -#define IO_MUX_GPIO32_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO32_MCU_SEL_S 12 -/** IO_MUX_GPIO32_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO32_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO32_FILTER_EN_M (IO_MUX_GPIO32_FILTER_EN_V << IO_MUX_GPIO32_FILTER_EN_S) -#define IO_MUX_GPIO32_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO32_FILTER_EN_S 15 -/** IO_MUX_GPIO32_RUE_I3C : R/W; bitpos: [16]; default: 0; - * NA - */ -#define IO_MUX_GPIO32_RUE_I3C (BIT(16)) -#define IO_MUX_GPIO32_RUE_I3C_M (IO_MUX_GPIO32_RUE_I3C_V << IO_MUX_GPIO32_RUE_I3C_S) -#define IO_MUX_GPIO32_RUE_I3C_V 0x00000001U -#define IO_MUX_GPIO32_RUE_I3C_S 16 -/** IO_MUX_GPIO32_RU_I3C : R/W; bitpos: [18:17]; default: 0; - * NA - */ -#define IO_MUX_GPIO32_RU_I3C 0x00000003U -#define IO_MUX_GPIO32_RU_I3C_M (IO_MUX_GPIO32_RU_I3C_V << IO_MUX_GPIO32_RU_I3C_S) -#define IO_MUX_GPIO32_RU_I3C_V 0x00000003U -#define IO_MUX_GPIO32_RU_I3C_S 17 -/** IO_MUX_GPIO32_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0; - * NA - */ -#define IO_MUX_GPIO32_RUE_SEL_I3C (BIT(19)) -#define IO_MUX_GPIO32_RUE_SEL_I3C_M (IO_MUX_GPIO32_RUE_SEL_I3C_V << IO_MUX_GPIO32_RUE_SEL_I3C_S) -#define IO_MUX_GPIO32_RUE_SEL_I3C_V 0x00000001U -#define IO_MUX_GPIO32_RUE_SEL_I3C_S 19 - -/** IO_MUX_gpio33_REG register - * iomux control register for gpio33 - */ -#define IO_MUX_GPIO33_REG (DR_REG_IO_MUX_BASE + 0x88) -/** IO_MUX_GPIO33_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_OE (BIT(0)) -#define IO_MUX_GPIO33_MCU_OE_M (IO_MUX_GPIO33_MCU_OE_V << IO_MUX_GPIO33_MCU_OE_S) -#define IO_MUX_GPIO33_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO33_MCU_OE_S 0 -/** IO_MUX_GPIO33_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO33_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO33_SLP_SEL_M (IO_MUX_GPIO33_SLP_SEL_V << IO_MUX_GPIO33_SLP_SEL_S) -#define IO_MUX_GPIO33_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO33_SLP_SEL_S 1 -/** IO_MUX_GPIO33_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO33_MCU_WPD_M (IO_MUX_GPIO33_MCU_WPD_V << IO_MUX_GPIO33_MCU_WPD_S) -#define IO_MUX_GPIO33_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO33_MCU_WPD_S 2 -/** IO_MUX_GPIO33_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO33_MCU_WPU_M (IO_MUX_GPIO33_MCU_WPU_V << IO_MUX_GPIO33_MCU_WPU_S) -#define IO_MUX_GPIO33_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO33_MCU_WPU_S 3 -/** IO_MUX_GPIO33_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO33_MCU_IE (BIT(4)) -#define IO_MUX_GPIO33_MCU_IE_M (IO_MUX_GPIO33_MCU_IE_V << IO_MUX_GPIO33_MCU_IE_S) -#define IO_MUX_GPIO33_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO33_MCU_IE_S 4 -/** IO_MUX_GPIO33_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO33_MCU_DRV 0x00000003U -#define IO_MUX_GPIO33_MCU_DRV_M (IO_MUX_GPIO33_MCU_DRV_V << IO_MUX_GPIO33_MCU_DRV_S) -#define IO_MUX_GPIO33_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO33_MCU_DRV_S 5 -/** IO_MUX_GPIO33_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO33_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO33_FUN_WPD_M (IO_MUX_GPIO33_FUN_WPD_V << IO_MUX_GPIO33_FUN_WPD_S) -#define IO_MUX_GPIO33_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO33_FUN_WPD_S 7 -/** IO_MUX_GPIO33_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO33_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO33_FUN_WPU_M (IO_MUX_GPIO33_FUN_WPU_V << IO_MUX_GPIO33_FUN_WPU_S) -#define IO_MUX_GPIO33_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO33_FUN_WPU_S 8 -/** IO_MUX_GPIO33_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO33_FUN_IE (BIT(9)) -#define IO_MUX_GPIO33_FUN_IE_M (IO_MUX_GPIO33_FUN_IE_V << IO_MUX_GPIO33_FUN_IE_S) -#define IO_MUX_GPIO33_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO33_FUN_IE_S 9 -/** IO_MUX_GPIO33_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO33_FUN_DRV 0x00000003U -#define IO_MUX_GPIO33_FUN_DRV_M (IO_MUX_GPIO33_FUN_DRV_V << IO_MUX_GPIO33_FUN_DRV_S) -#define IO_MUX_GPIO33_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO33_FUN_DRV_S 10 -/** IO_MUX_GPIO33_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO33_MCU_SEL 0x00000007U -#define IO_MUX_GPIO33_MCU_SEL_M (IO_MUX_GPIO33_MCU_SEL_V << IO_MUX_GPIO33_MCU_SEL_S) -#define IO_MUX_GPIO33_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO33_MCU_SEL_S 12 -/** IO_MUX_GPIO33_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO33_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO33_FILTER_EN_M (IO_MUX_GPIO33_FILTER_EN_V << IO_MUX_GPIO33_FILTER_EN_S) -#define IO_MUX_GPIO33_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO33_FILTER_EN_S 15 -/** IO_MUX_GPIO33_RUE_I3C : R/W; bitpos: [16]; default: 0; - * NA - */ -#define IO_MUX_GPIO33_RUE_I3C (BIT(16)) -#define IO_MUX_GPIO33_RUE_I3C_M (IO_MUX_GPIO33_RUE_I3C_V << IO_MUX_GPIO33_RUE_I3C_S) -#define IO_MUX_GPIO33_RUE_I3C_V 0x00000001U -#define IO_MUX_GPIO33_RUE_I3C_S 16 -/** IO_MUX_GPIO33_RU_I3C : R/W; bitpos: [18:17]; default: 0; - * NA - */ -#define IO_MUX_GPIO33_RU_I3C 0x00000003U -#define IO_MUX_GPIO33_RU_I3C_M (IO_MUX_GPIO33_RU_I3C_V << IO_MUX_GPIO33_RU_I3C_S) -#define IO_MUX_GPIO33_RU_I3C_V 0x00000003U -#define IO_MUX_GPIO33_RU_I3C_S 17 -/** IO_MUX_GPIO33_RUE_SEL_I3C : R/W; bitpos: [19]; default: 0; - * NA - */ -#define IO_MUX_GPIO33_RUE_SEL_I3C (BIT(19)) -#define IO_MUX_GPIO33_RUE_SEL_I3C_M (IO_MUX_GPIO33_RUE_SEL_I3C_V << IO_MUX_GPIO33_RUE_SEL_I3C_S) -#define IO_MUX_GPIO33_RUE_SEL_I3C_V 0x00000001U -#define IO_MUX_GPIO33_RUE_SEL_I3C_S 19 - -/** IO_MUX_gpio34_REG register - * iomux control register for gpio34 - */ -#define IO_MUX_GPIO34_REG (DR_REG_IO_MUX_BASE + 0x8c) -/** IO_MUX_GPIO34_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_OE (BIT(0)) -#define IO_MUX_GPIO34_MCU_OE_M (IO_MUX_GPIO34_MCU_OE_V << IO_MUX_GPIO34_MCU_OE_S) -#define IO_MUX_GPIO34_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO34_MCU_OE_S 0 -/** IO_MUX_GPIO34_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO34_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO34_SLP_SEL_M (IO_MUX_GPIO34_SLP_SEL_V << IO_MUX_GPIO34_SLP_SEL_S) -#define IO_MUX_GPIO34_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO34_SLP_SEL_S 1 -/** IO_MUX_GPIO34_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO34_MCU_WPD_M (IO_MUX_GPIO34_MCU_WPD_V << IO_MUX_GPIO34_MCU_WPD_S) -#define IO_MUX_GPIO34_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO34_MCU_WPD_S 2 -/** IO_MUX_GPIO34_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO34_MCU_WPU_M (IO_MUX_GPIO34_MCU_WPU_V << IO_MUX_GPIO34_MCU_WPU_S) -#define IO_MUX_GPIO34_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO34_MCU_WPU_S 3 -/** IO_MUX_GPIO34_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO34_MCU_IE (BIT(4)) -#define IO_MUX_GPIO34_MCU_IE_M (IO_MUX_GPIO34_MCU_IE_V << IO_MUX_GPIO34_MCU_IE_S) -#define IO_MUX_GPIO34_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO34_MCU_IE_S 4 -/** IO_MUX_GPIO34_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO34_MCU_DRV 0x00000003U -#define IO_MUX_GPIO34_MCU_DRV_M (IO_MUX_GPIO34_MCU_DRV_V << IO_MUX_GPIO34_MCU_DRV_S) -#define IO_MUX_GPIO34_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO34_MCU_DRV_S 5 -/** IO_MUX_GPIO34_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO34_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO34_FUN_WPD_M (IO_MUX_GPIO34_FUN_WPD_V << IO_MUX_GPIO34_FUN_WPD_S) -#define IO_MUX_GPIO34_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO34_FUN_WPD_S 7 -/** IO_MUX_GPIO34_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO34_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO34_FUN_WPU_M (IO_MUX_GPIO34_FUN_WPU_V << IO_MUX_GPIO34_FUN_WPU_S) -#define IO_MUX_GPIO34_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO34_FUN_WPU_S 8 -/** IO_MUX_GPIO34_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO34_FUN_IE (BIT(9)) -#define IO_MUX_GPIO34_FUN_IE_M (IO_MUX_GPIO34_FUN_IE_V << IO_MUX_GPIO34_FUN_IE_S) -#define IO_MUX_GPIO34_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO34_FUN_IE_S 9 -/** IO_MUX_GPIO34_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO34_FUN_DRV 0x00000003U -#define IO_MUX_GPIO34_FUN_DRV_M (IO_MUX_GPIO34_FUN_DRV_V << IO_MUX_GPIO34_FUN_DRV_S) -#define IO_MUX_GPIO34_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO34_FUN_DRV_S 10 -/** IO_MUX_GPIO34_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO34_MCU_SEL 0x00000007U -#define IO_MUX_GPIO34_MCU_SEL_M (IO_MUX_GPIO34_MCU_SEL_V << IO_MUX_GPIO34_MCU_SEL_S) -#define IO_MUX_GPIO34_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO34_MCU_SEL_S 12 -/** IO_MUX_GPIO34_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO34_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO34_FILTER_EN_M (IO_MUX_GPIO34_FILTER_EN_V << IO_MUX_GPIO34_FILTER_EN_S) -#define IO_MUX_GPIO34_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO34_FILTER_EN_S 15 - -/** IO_MUX_gpio35_REG register - * iomux control register for gpio35 - */ -#define IO_MUX_GPIO35_REG (DR_REG_IO_MUX_BASE + 0x90) -/** IO_MUX_GPIO35_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_OE (BIT(0)) -#define IO_MUX_GPIO35_MCU_OE_M (IO_MUX_GPIO35_MCU_OE_V << IO_MUX_GPIO35_MCU_OE_S) -#define IO_MUX_GPIO35_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO35_MCU_OE_S 0 -/** IO_MUX_GPIO35_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO35_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO35_SLP_SEL_M (IO_MUX_GPIO35_SLP_SEL_V << IO_MUX_GPIO35_SLP_SEL_S) -#define IO_MUX_GPIO35_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO35_SLP_SEL_S 1 -/** IO_MUX_GPIO35_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO35_MCU_WPD_M (IO_MUX_GPIO35_MCU_WPD_V << IO_MUX_GPIO35_MCU_WPD_S) -#define IO_MUX_GPIO35_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO35_MCU_WPD_S 2 -/** IO_MUX_GPIO35_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO35_MCU_WPU_M (IO_MUX_GPIO35_MCU_WPU_V << IO_MUX_GPIO35_MCU_WPU_S) -#define IO_MUX_GPIO35_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO35_MCU_WPU_S 3 -/** IO_MUX_GPIO35_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO35_MCU_IE (BIT(4)) -#define IO_MUX_GPIO35_MCU_IE_M (IO_MUX_GPIO35_MCU_IE_V << IO_MUX_GPIO35_MCU_IE_S) -#define IO_MUX_GPIO35_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO35_MCU_IE_S 4 -/** IO_MUX_GPIO35_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO35_MCU_DRV 0x00000003U -#define IO_MUX_GPIO35_MCU_DRV_M (IO_MUX_GPIO35_MCU_DRV_V << IO_MUX_GPIO35_MCU_DRV_S) -#define IO_MUX_GPIO35_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO35_MCU_DRV_S 5 -/** IO_MUX_GPIO35_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO35_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO35_FUN_WPD_M (IO_MUX_GPIO35_FUN_WPD_V << IO_MUX_GPIO35_FUN_WPD_S) -#define IO_MUX_GPIO35_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO35_FUN_WPD_S 7 -/** IO_MUX_GPIO35_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO35_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO35_FUN_WPU_M (IO_MUX_GPIO35_FUN_WPU_V << IO_MUX_GPIO35_FUN_WPU_S) -#define IO_MUX_GPIO35_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO35_FUN_WPU_S 8 -/** IO_MUX_GPIO35_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO35_FUN_IE (BIT(9)) -#define IO_MUX_GPIO35_FUN_IE_M (IO_MUX_GPIO35_FUN_IE_V << IO_MUX_GPIO35_FUN_IE_S) -#define IO_MUX_GPIO35_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO35_FUN_IE_S 9 -/** IO_MUX_GPIO35_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO35_FUN_DRV 0x00000003U -#define IO_MUX_GPIO35_FUN_DRV_M (IO_MUX_GPIO35_FUN_DRV_V << IO_MUX_GPIO35_FUN_DRV_S) -#define IO_MUX_GPIO35_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO35_FUN_DRV_S 10 -/** IO_MUX_GPIO35_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO35_MCU_SEL 0x00000007U -#define IO_MUX_GPIO35_MCU_SEL_M (IO_MUX_GPIO35_MCU_SEL_V << IO_MUX_GPIO35_MCU_SEL_S) -#define IO_MUX_GPIO35_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO35_MCU_SEL_S 12 -/** IO_MUX_GPIO35_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO35_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO35_FILTER_EN_M (IO_MUX_GPIO35_FILTER_EN_V << IO_MUX_GPIO35_FILTER_EN_S) -#define IO_MUX_GPIO35_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO35_FILTER_EN_S 15 - -/** IO_MUX_gpio36_REG register - * iomux control register for gpio36 - */ -#define IO_MUX_GPIO36_REG (DR_REG_IO_MUX_BASE + 0x94) -/** IO_MUX_GPIO36_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_OE (BIT(0)) -#define IO_MUX_GPIO36_MCU_OE_M (IO_MUX_GPIO36_MCU_OE_V << IO_MUX_GPIO36_MCU_OE_S) -#define IO_MUX_GPIO36_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO36_MCU_OE_S 0 -/** IO_MUX_GPIO36_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO36_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO36_SLP_SEL_M (IO_MUX_GPIO36_SLP_SEL_V << IO_MUX_GPIO36_SLP_SEL_S) -#define IO_MUX_GPIO36_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO36_SLP_SEL_S 1 -/** IO_MUX_GPIO36_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO36_MCU_WPD_M (IO_MUX_GPIO36_MCU_WPD_V << IO_MUX_GPIO36_MCU_WPD_S) -#define IO_MUX_GPIO36_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO36_MCU_WPD_S 2 -/** IO_MUX_GPIO36_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO36_MCU_WPU_M (IO_MUX_GPIO36_MCU_WPU_V << IO_MUX_GPIO36_MCU_WPU_S) -#define IO_MUX_GPIO36_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO36_MCU_WPU_S 3 -/** IO_MUX_GPIO36_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO36_MCU_IE (BIT(4)) -#define IO_MUX_GPIO36_MCU_IE_M (IO_MUX_GPIO36_MCU_IE_V << IO_MUX_GPIO36_MCU_IE_S) -#define IO_MUX_GPIO36_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO36_MCU_IE_S 4 -/** IO_MUX_GPIO36_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO36_MCU_DRV 0x00000003U -#define IO_MUX_GPIO36_MCU_DRV_M (IO_MUX_GPIO36_MCU_DRV_V << IO_MUX_GPIO36_MCU_DRV_S) -#define IO_MUX_GPIO36_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO36_MCU_DRV_S 5 -/** IO_MUX_GPIO36_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO36_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO36_FUN_WPD_M (IO_MUX_GPIO36_FUN_WPD_V << IO_MUX_GPIO36_FUN_WPD_S) -#define IO_MUX_GPIO36_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO36_FUN_WPD_S 7 -/** IO_MUX_GPIO36_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO36_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO36_FUN_WPU_M (IO_MUX_GPIO36_FUN_WPU_V << IO_MUX_GPIO36_FUN_WPU_S) -#define IO_MUX_GPIO36_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO36_FUN_WPU_S 8 -/** IO_MUX_GPIO36_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO36_FUN_IE (BIT(9)) -#define IO_MUX_GPIO36_FUN_IE_M (IO_MUX_GPIO36_FUN_IE_V << IO_MUX_GPIO36_FUN_IE_S) -#define IO_MUX_GPIO36_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO36_FUN_IE_S 9 -/** IO_MUX_GPIO36_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO36_FUN_DRV 0x00000003U -#define IO_MUX_GPIO36_FUN_DRV_M (IO_MUX_GPIO36_FUN_DRV_V << IO_MUX_GPIO36_FUN_DRV_S) -#define IO_MUX_GPIO36_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO36_FUN_DRV_S 10 -/** IO_MUX_GPIO36_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO36_MCU_SEL 0x00000007U -#define IO_MUX_GPIO36_MCU_SEL_M (IO_MUX_GPIO36_MCU_SEL_V << IO_MUX_GPIO36_MCU_SEL_S) -#define IO_MUX_GPIO36_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO36_MCU_SEL_S 12 -/** IO_MUX_GPIO36_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO36_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO36_FILTER_EN_M (IO_MUX_GPIO36_FILTER_EN_V << IO_MUX_GPIO36_FILTER_EN_S) -#define IO_MUX_GPIO36_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO36_FILTER_EN_S 15 - -/** IO_MUX_gpio37_REG register - * iomux control register for gpio37 - */ -#define IO_MUX_GPIO37_REG (DR_REG_IO_MUX_BASE + 0x98) -/** IO_MUX_GPIO37_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_OE (BIT(0)) -#define IO_MUX_GPIO37_MCU_OE_M (IO_MUX_GPIO37_MCU_OE_V << IO_MUX_GPIO37_MCU_OE_S) -#define IO_MUX_GPIO37_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO37_MCU_OE_S 0 -/** IO_MUX_GPIO37_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO37_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO37_SLP_SEL_M (IO_MUX_GPIO37_SLP_SEL_V << IO_MUX_GPIO37_SLP_SEL_S) -#define IO_MUX_GPIO37_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO37_SLP_SEL_S 1 -/** IO_MUX_GPIO37_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO37_MCU_WPD_M (IO_MUX_GPIO37_MCU_WPD_V << IO_MUX_GPIO37_MCU_WPD_S) -#define IO_MUX_GPIO37_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO37_MCU_WPD_S 2 -/** IO_MUX_GPIO37_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO37_MCU_WPU_M (IO_MUX_GPIO37_MCU_WPU_V << IO_MUX_GPIO37_MCU_WPU_S) -#define IO_MUX_GPIO37_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO37_MCU_WPU_S 3 -/** IO_MUX_GPIO37_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO37_MCU_IE (BIT(4)) -#define IO_MUX_GPIO37_MCU_IE_M (IO_MUX_GPIO37_MCU_IE_V << IO_MUX_GPIO37_MCU_IE_S) -#define IO_MUX_GPIO37_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO37_MCU_IE_S 4 -/** IO_MUX_GPIO37_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO37_MCU_DRV 0x00000003U -#define IO_MUX_GPIO37_MCU_DRV_M (IO_MUX_GPIO37_MCU_DRV_V << IO_MUX_GPIO37_MCU_DRV_S) -#define IO_MUX_GPIO37_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO37_MCU_DRV_S 5 -/** IO_MUX_GPIO37_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO37_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO37_FUN_WPD_M (IO_MUX_GPIO37_FUN_WPD_V << IO_MUX_GPIO37_FUN_WPD_S) -#define IO_MUX_GPIO37_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO37_FUN_WPD_S 7 -/** IO_MUX_GPIO37_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO37_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO37_FUN_WPU_M (IO_MUX_GPIO37_FUN_WPU_V << IO_MUX_GPIO37_FUN_WPU_S) -#define IO_MUX_GPIO37_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO37_FUN_WPU_S 8 -/** IO_MUX_GPIO37_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO37_FUN_IE (BIT(9)) -#define IO_MUX_GPIO37_FUN_IE_M (IO_MUX_GPIO37_FUN_IE_V << IO_MUX_GPIO37_FUN_IE_S) -#define IO_MUX_GPIO37_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO37_FUN_IE_S 9 -/** IO_MUX_GPIO37_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO37_FUN_DRV 0x00000003U -#define IO_MUX_GPIO37_FUN_DRV_M (IO_MUX_GPIO37_FUN_DRV_V << IO_MUX_GPIO37_FUN_DRV_S) -#define IO_MUX_GPIO37_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO37_FUN_DRV_S 10 -/** IO_MUX_GPIO37_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO37_MCU_SEL 0x00000007U -#define IO_MUX_GPIO37_MCU_SEL_M (IO_MUX_GPIO37_MCU_SEL_V << IO_MUX_GPIO37_MCU_SEL_S) -#define IO_MUX_GPIO37_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO37_MCU_SEL_S 12 -/** IO_MUX_GPIO37_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO37_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO37_FILTER_EN_M (IO_MUX_GPIO37_FILTER_EN_V << IO_MUX_GPIO37_FILTER_EN_S) -#define IO_MUX_GPIO37_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO37_FILTER_EN_S 15 - -/** IO_MUX_gpio38_REG register - * iomux control register for gpio38 - */ -#define IO_MUX_GPIO38_REG (DR_REG_IO_MUX_BASE + 0x9c) -/** IO_MUX_GPIO38_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_OE (BIT(0)) -#define IO_MUX_GPIO38_MCU_OE_M (IO_MUX_GPIO38_MCU_OE_V << IO_MUX_GPIO38_MCU_OE_S) -#define IO_MUX_GPIO38_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO38_MCU_OE_S 0 -/** IO_MUX_GPIO38_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO38_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO38_SLP_SEL_M (IO_MUX_GPIO38_SLP_SEL_V << IO_MUX_GPIO38_SLP_SEL_S) -#define IO_MUX_GPIO38_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO38_SLP_SEL_S 1 -/** IO_MUX_GPIO38_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO38_MCU_WPD_M (IO_MUX_GPIO38_MCU_WPD_V << IO_MUX_GPIO38_MCU_WPD_S) -#define IO_MUX_GPIO38_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO38_MCU_WPD_S 2 -/** IO_MUX_GPIO38_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO38_MCU_WPU_M (IO_MUX_GPIO38_MCU_WPU_V << IO_MUX_GPIO38_MCU_WPU_S) -#define IO_MUX_GPIO38_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO38_MCU_WPU_S 3 -/** IO_MUX_GPIO38_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO38_MCU_IE (BIT(4)) -#define IO_MUX_GPIO38_MCU_IE_M (IO_MUX_GPIO38_MCU_IE_V << IO_MUX_GPIO38_MCU_IE_S) -#define IO_MUX_GPIO38_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO38_MCU_IE_S 4 -/** IO_MUX_GPIO38_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO38_MCU_DRV 0x00000003U -#define IO_MUX_GPIO38_MCU_DRV_M (IO_MUX_GPIO38_MCU_DRV_V << IO_MUX_GPIO38_MCU_DRV_S) -#define IO_MUX_GPIO38_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO38_MCU_DRV_S 5 -/** IO_MUX_GPIO38_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO38_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO38_FUN_WPD_M (IO_MUX_GPIO38_FUN_WPD_V << IO_MUX_GPIO38_FUN_WPD_S) -#define IO_MUX_GPIO38_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO38_FUN_WPD_S 7 -/** IO_MUX_GPIO38_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO38_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO38_FUN_WPU_M (IO_MUX_GPIO38_FUN_WPU_V << IO_MUX_GPIO38_FUN_WPU_S) -#define IO_MUX_GPIO38_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO38_FUN_WPU_S 8 -/** IO_MUX_GPIO38_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO38_FUN_IE (BIT(9)) -#define IO_MUX_GPIO38_FUN_IE_M (IO_MUX_GPIO38_FUN_IE_V << IO_MUX_GPIO38_FUN_IE_S) -#define IO_MUX_GPIO38_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO38_FUN_IE_S 9 -/** IO_MUX_GPIO38_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO38_FUN_DRV 0x00000003U -#define IO_MUX_GPIO38_FUN_DRV_M (IO_MUX_GPIO38_FUN_DRV_V << IO_MUX_GPIO38_FUN_DRV_S) -#define IO_MUX_GPIO38_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO38_FUN_DRV_S 10 -/** IO_MUX_GPIO38_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO38_MCU_SEL 0x00000007U -#define IO_MUX_GPIO38_MCU_SEL_M (IO_MUX_GPIO38_MCU_SEL_V << IO_MUX_GPIO38_MCU_SEL_S) -#define IO_MUX_GPIO38_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO38_MCU_SEL_S 12 -/** IO_MUX_GPIO38_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO38_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO38_FILTER_EN_M (IO_MUX_GPIO38_FILTER_EN_V << IO_MUX_GPIO38_FILTER_EN_S) -#define IO_MUX_GPIO38_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO38_FILTER_EN_S 15 - -/** IO_MUX_gpio39_REG register - * iomux control register for gpio39 - */ -#define IO_MUX_GPIO39_REG (DR_REG_IO_MUX_BASE + 0xa0) -/** IO_MUX_GPIO39_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_OE (BIT(0)) -#define IO_MUX_GPIO39_MCU_OE_M (IO_MUX_GPIO39_MCU_OE_V << IO_MUX_GPIO39_MCU_OE_S) -#define IO_MUX_GPIO39_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO39_MCU_OE_S 0 -/** IO_MUX_GPIO39_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO39_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO39_SLP_SEL_M (IO_MUX_GPIO39_SLP_SEL_V << IO_MUX_GPIO39_SLP_SEL_S) -#define IO_MUX_GPIO39_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO39_SLP_SEL_S 1 -/** IO_MUX_GPIO39_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO39_MCU_WPD_M (IO_MUX_GPIO39_MCU_WPD_V << IO_MUX_GPIO39_MCU_WPD_S) -#define IO_MUX_GPIO39_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO39_MCU_WPD_S 2 -/** IO_MUX_GPIO39_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO39_MCU_WPU_M (IO_MUX_GPIO39_MCU_WPU_V << IO_MUX_GPIO39_MCU_WPU_S) -#define IO_MUX_GPIO39_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO39_MCU_WPU_S 3 -/** IO_MUX_GPIO39_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO39_MCU_IE (BIT(4)) -#define IO_MUX_GPIO39_MCU_IE_M (IO_MUX_GPIO39_MCU_IE_V << IO_MUX_GPIO39_MCU_IE_S) -#define IO_MUX_GPIO39_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO39_MCU_IE_S 4 -/** IO_MUX_GPIO39_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO39_MCU_DRV 0x00000003U -#define IO_MUX_GPIO39_MCU_DRV_M (IO_MUX_GPIO39_MCU_DRV_V << IO_MUX_GPIO39_MCU_DRV_S) -#define IO_MUX_GPIO39_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO39_MCU_DRV_S 5 -/** IO_MUX_GPIO39_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO39_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO39_FUN_WPD_M (IO_MUX_GPIO39_FUN_WPD_V << IO_MUX_GPIO39_FUN_WPD_S) -#define IO_MUX_GPIO39_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO39_FUN_WPD_S 7 -/** IO_MUX_GPIO39_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO39_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO39_FUN_WPU_M (IO_MUX_GPIO39_FUN_WPU_V << IO_MUX_GPIO39_FUN_WPU_S) -#define IO_MUX_GPIO39_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO39_FUN_WPU_S 8 -/** IO_MUX_GPIO39_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO39_FUN_IE (BIT(9)) -#define IO_MUX_GPIO39_FUN_IE_M (IO_MUX_GPIO39_FUN_IE_V << IO_MUX_GPIO39_FUN_IE_S) -#define IO_MUX_GPIO39_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO39_FUN_IE_S 9 -/** IO_MUX_GPIO39_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO39_FUN_DRV 0x00000003U -#define IO_MUX_GPIO39_FUN_DRV_M (IO_MUX_GPIO39_FUN_DRV_V << IO_MUX_GPIO39_FUN_DRV_S) -#define IO_MUX_GPIO39_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO39_FUN_DRV_S 10 -/** IO_MUX_GPIO39_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO39_MCU_SEL 0x00000007U -#define IO_MUX_GPIO39_MCU_SEL_M (IO_MUX_GPIO39_MCU_SEL_V << IO_MUX_GPIO39_MCU_SEL_S) -#define IO_MUX_GPIO39_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO39_MCU_SEL_S 12 -/** IO_MUX_GPIO39_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO39_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO39_FILTER_EN_M (IO_MUX_GPIO39_FILTER_EN_V << IO_MUX_GPIO39_FILTER_EN_S) -#define IO_MUX_GPIO39_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO39_FILTER_EN_S 15 - -/** IO_MUX_gpio40_REG register - * iomux control register for gpio40 - */ -#define IO_MUX_GPIO40_REG (DR_REG_IO_MUX_BASE + 0xa4) -/** IO_MUX_GPIO40_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_OE (BIT(0)) -#define IO_MUX_GPIO40_MCU_OE_M (IO_MUX_GPIO40_MCU_OE_V << IO_MUX_GPIO40_MCU_OE_S) -#define IO_MUX_GPIO40_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO40_MCU_OE_S 0 -/** IO_MUX_GPIO40_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO40_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO40_SLP_SEL_M (IO_MUX_GPIO40_SLP_SEL_V << IO_MUX_GPIO40_SLP_SEL_S) -#define IO_MUX_GPIO40_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO40_SLP_SEL_S 1 -/** IO_MUX_GPIO40_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO40_MCU_WPD_M (IO_MUX_GPIO40_MCU_WPD_V << IO_MUX_GPIO40_MCU_WPD_S) -#define IO_MUX_GPIO40_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO40_MCU_WPD_S 2 -/** IO_MUX_GPIO40_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO40_MCU_WPU_M (IO_MUX_GPIO40_MCU_WPU_V << IO_MUX_GPIO40_MCU_WPU_S) -#define IO_MUX_GPIO40_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO40_MCU_WPU_S 3 -/** IO_MUX_GPIO40_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO40_MCU_IE (BIT(4)) -#define IO_MUX_GPIO40_MCU_IE_M (IO_MUX_GPIO40_MCU_IE_V << IO_MUX_GPIO40_MCU_IE_S) -#define IO_MUX_GPIO40_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO40_MCU_IE_S 4 -/** IO_MUX_GPIO40_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO40_MCU_DRV 0x00000003U -#define IO_MUX_GPIO40_MCU_DRV_M (IO_MUX_GPIO40_MCU_DRV_V << IO_MUX_GPIO40_MCU_DRV_S) -#define IO_MUX_GPIO40_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO40_MCU_DRV_S 5 -/** IO_MUX_GPIO40_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO40_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO40_FUN_WPD_M (IO_MUX_GPIO40_FUN_WPD_V << IO_MUX_GPIO40_FUN_WPD_S) -#define IO_MUX_GPIO40_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO40_FUN_WPD_S 7 -/** IO_MUX_GPIO40_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO40_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO40_FUN_WPU_M (IO_MUX_GPIO40_FUN_WPU_V << IO_MUX_GPIO40_FUN_WPU_S) -#define IO_MUX_GPIO40_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO40_FUN_WPU_S 8 -/** IO_MUX_GPIO40_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO40_FUN_IE (BIT(9)) -#define IO_MUX_GPIO40_FUN_IE_M (IO_MUX_GPIO40_FUN_IE_V << IO_MUX_GPIO40_FUN_IE_S) -#define IO_MUX_GPIO40_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO40_FUN_IE_S 9 -/** IO_MUX_GPIO40_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO40_FUN_DRV 0x00000003U -#define IO_MUX_GPIO40_FUN_DRV_M (IO_MUX_GPIO40_FUN_DRV_V << IO_MUX_GPIO40_FUN_DRV_S) -#define IO_MUX_GPIO40_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO40_FUN_DRV_S 10 -/** IO_MUX_GPIO40_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO40_MCU_SEL 0x00000007U -#define IO_MUX_GPIO40_MCU_SEL_M (IO_MUX_GPIO40_MCU_SEL_V << IO_MUX_GPIO40_MCU_SEL_S) -#define IO_MUX_GPIO40_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO40_MCU_SEL_S 12 -/** IO_MUX_GPIO40_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO40_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO40_FILTER_EN_M (IO_MUX_GPIO40_FILTER_EN_V << IO_MUX_GPIO40_FILTER_EN_S) -#define IO_MUX_GPIO40_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO40_FILTER_EN_S 15 - -/** IO_MUX_gpio41_REG register - * iomux control register for gpio41 - */ -#define IO_MUX_GPIO41_REG (DR_REG_IO_MUX_BASE + 0xa8) -/** IO_MUX_GPIO41_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_OE (BIT(0)) -#define IO_MUX_GPIO41_MCU_OE_M (IO_MUX_GPIO41_MCU_OE_V << IO_MUX_GPIO41_MCU_OE_S) -#define IO_MUX_GPIO41_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO41_MCU_OE_S 0 -/** IO_MUX_GPIO41_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO41_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO41_SLP_SEL_M (IO_MUX_GPIO41_SLP_SEL_V << IO_MUX_GPIO41_SLP_SEL_S) -#define IO_MUX_GPIO41_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO41_SLP_SEL_S 1 -/** IO_MUX_GPIO41_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO41_MCU_WPD_M (IO_MUX_GPIO41_MCU_WPD_V << IO_MUX_GPIO41_MCU_WPD_S) -#define IO_MUX_GPIO41_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO41_MCU_WPD_S 2 -/** IO_MUX_GPIO41_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO41_MCU_WPU_M (IO_MUX_GPIO41_MCU_WPU_V << IO_MUX_GPIO41_MCU_WPU_S) -#define IO_MUX_GPIO41_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO41_MCU_WPU_S 3 -/** IO_MUX_GPIO41_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO41_MCU_IE (BIT(4)) -#define IO_MUX_GPIO41_MCU_IE_M (IO_MUX_GPIO41_MCU_IE_V << IO_MUX_GPIO41_MCU_IE_S) -#define IO_MUX_GPIO41_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO41_MCU_IE_S 4 -/** IO_MUX_GPIO41_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO41_MCU_DRV 0x00000003U -#define IO_MUX_GPIO41_MCU_DRV_M (IO_MUX_GPIO41_MCU_DRV_V << IO_MUX_GPIO41_MCU_DRV_S) -#define IO_MUX_GPIO41_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO41_MCU_DRV_S 5 -/** IO_MUX_GPIO41_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO41_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO41_FUN_WPD_M (IO_MUX_GPIO41_FUN_WPD_V << IO_MUX_GPIO41_FUN_WPD_S) -#define IO_MUX_GPIO41_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO41_FUN_WPD_S 7 -/** IO_MUX_GPIO41_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO41_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO41_FUN_WPU_M (IO_MUX_GPIO41_FUN_WPU_V << IO_MUX_GPIO41_FUN_WPU_S) -#define IO_MUX_GPIO41_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO41_FUN_WPU_S 8 -/** IO_MUX_GPIO41_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO41_FUN_IE (BIT(9)) -#define IO_MUX_GPIO41_FUN_IE_M (IO_MUX_GPIO41_FUN_IE_V << IO_MUX_GPIO41_FUN_IE_S) -#define IO_MUX_GPIO41_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO41_FUN_IE_S 9 -/** IO_MUX_GPIO41_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO41_FUN_DRV 0x00000003U -#define IO_MUX_GPIO41_FUN_DRV_M (IO_MUX_GPIO41_FUN_DRV_V << IO_MUX_GPIO41_FUN_DRV_S) -#define IO_MUX_GPIO41_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO41_FUN_DRV_S 10 -/** IO_MUX_GPIO41_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO41_MCU_SEL 0x00000007U -#define IO_MUX_GPIO41_MCU_SEL_M (IO_MUX_GPIO41_MCU_SEL_V << IO_MUX_GPIO41_MCU_SEL_S) -#define IO_MUX_GPIO41_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO41_MCU_SEL_S 12 -/** IO_MUX_GPIO41_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO41_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO41_FILTER_EN_M (IO_MUX_GPIO41_FILTER_EN_V << IO_MUX_GPIO41_FILTER_EN_S) -#define IO_MUX_GPIO41_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO41_FILTER_EN_S 15 - -/** IO_MUX_gpio42_REG register - * iomux control register for gpio42 - */ -#define IO_MUX_GPIO42_REG (DR_REG_IO_MUX_BASE + 0xac) -/** IO_MUX_GPIO42_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_OE (BIT(0)) -#define IO_MUX_GPIO42_MCU_OE_M (IO_MUX_GPIO42_MCU_OE_V << IO_MUX_GPIO42_MCU_OE_S) -#define IO_MUX_GPIO42_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO42_MCU_OE_S 0 -/** IO_MUX_GPIO42_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO42_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO42_SLP_SEL_M (IO_MUX_GPIO42_SLP_SEL_V << IO_MUX_GPIO42_SLP_SEL_S) -#define IO_MUX_GPIO42_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO42_SLP_SEL_S 1 -/** IO_MUX_GPIO42_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO42_MCU_WPD_M (IO_MUX_GPIO42_MCU_WPD_V << IO_MUX_GPIO42_MCU_WPD_S) -#define IO_MUX_GPIO42_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO42_MCU_WPD_S 2 -/** IO_MUX_GPIO42_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO42_MCU_WPU_M (IO_MUX_GPIO42_MCU_WPU_V << IO_MUX_GPIO42_MCU_WPU_S) -#define IO_MUX_GPIO42_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO42_MCU_WPU_S 3 -/** IO_MUX_GPIO42_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO42_MCU_IE (BIT(4)) -#define IO_MUX_GPIO42_MCU_IE_M (IO_MUX_GPIO42_MCU_IE_V << IO_MUX_GPIO42_MCU_IE_S) -#define IO_MUX_GPIO42_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO42_MCU_IE_S 4 -/** IO_MUX_GPIO42_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO42_MCU_DRV 0x00000003U -#define IO_MUX_GPIO42_MCU_DRV_M (IO_MUX_GPIO42_MCU_DRV_V << IO_MUX_GPIO42_MCU_DRV_S) -#define IO_MUX_GPIO42_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO42_MCU_DRV_S 5 -/** IO_MUX_GPIO42_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO42_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO42_FUN_WPD_M (IO_MUX_GPIO42_FUN_WPD_V << IO_MUX_GPIO42_FUN_WPD_S) -#define IO_MUX_GPIO42_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO42_FUN_WPD_S 7 -/** IO_MUX_GPIO42_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO42_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO42_FUN_WPU_M (IO_MUX_GPIO42_FUN_WPU_V << IO_MUX_GPIO42_FUN_WPU_S) -#define IO_MUX_GPIO42_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO42_FUN_WPU_S 8 -/** IO_MUX_GPIO42_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO42_FUN_IE (BIT(9)) -#define IO_MUX_GPIO42_FUN_IE_M (IO_MUX_GPIO42_FUN_IE_V << IO_MUX_GPIO42_FUN_IE_S) -#define IO_MUX_GPIO42_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO42_FUN_IE_S 9 -/** IO_MUX_GPIO42_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO42_FUN_DRV 0x00000003U -#define IO_MUX_GPIO42_FUN_DRV_M (IO_MUX_GPIO42_FUN_DRV_V << IO_MUX_GPIO42_FUN_DRV_S) -#define IO_MUX_GPIO42_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO42_FUN_DRV_S 10 -/** IO_MUX_GPIO42_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO42_MCU_SEL 0x00000007U -#define IO_MUX_GPIO42_MCU_SEL_M (IO_MUX_GPIO42_MCU_SEL_V << IO_MUX_GPIO42_MCU_SEL_S) -#define IO_MUX_GPIO42_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO42_MCU_SEL_S 12 -/** IO_MUX_GPIO42_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO42_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO42_FILTER_EN_M (IO_MUX_GPIO42_FILTER_EN_V << IO_MUX_GPIO42_FILTER_EN_S) -#define IO_MUX_GPIO42_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO42_FILTER_EN_S 15 - -/** IO_MUX_gpio43_REG register - * iomux control register for gpio43 - */ -#define IO_MUX_GPIO43_REG (DR_REG_IO_MUX_BASE + 0xb0) -/** IO_MUX_GPIO43_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_OE (BIT(0)) -#define IO_MUX_GPIO43_MCU_OE_M (IO_MUX_GPIO43_MCU_OE_V << IO_MUX_GPIO43_MCU_OE_S) -#define IO_MUX_GPIO43_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO43_MCU_OE_S 0 -/** IO_MUX_GPIO43_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO43_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO43_SLP_SEL_M (IO_MUX_GPIO43_SLP_SEL_V << IO_MUX_GPIO43_SLP_SEL_S) -#define IO_MUX_GPIO43_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO43_SLP_SEL_S 1 -/** IO_MUX_GPIO43_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO43_MCU_WPD_M (IO_MUX_GPIO43_MCU_WPD_V << IO_MUX_GPIO43_MCU_WPD_S) -#define IO_MUX_GPIO43_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO43_MCU_WPD_S 2 -/** IO_MUX_GPIO43_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO43_MCU_WPU_M (IO_MUX_GPIO43_MCU_WPU_V << IO_MUX_GPIO43_MCU_WPU_S) -#define IO_MUX_GPIO43_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO43_MCU_WPU_S 3 -/** IO_MUX_GPIO43_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO43_MCU_IE (BIT(4)) -#define IO_MUX_GPIO43_MCU_IE_M (IO_MUX_GPIO43_MCU_IE_V << IO_MUX_GPIO43_MCU_IE_S) -#define IO_MUX_GPIO43_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO43_MCU_IE_S 4 -/** IO_MUX_GPIO43_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO43_MCU_DRV 0x00000003U -#define IO_MUX_GPIO43_MCU_DRV_M (IO_MUX_GPIO43_MCU_DRV_V << IO_MUX_GPIO43_MCU_DRV_S) -#define IO_MUX_GPIO43_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO43_MCU_DRV_S 5 -/** IO_MUX_GPIO43_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO43_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO43_FUN_WPD_M (IO_MUX_GPIO43_FUN_WPD_V << IO_MUX_GPIO43_FUN_WPD_S) -#define IO_MUX_GPIO43_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO43_FUN_WPD_S 7 -/** IO_MUX_GPIO43_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO43_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO43_FUN_WPU_M (IO_MUX_GPIO43_FUN_WPU_V << IO_MUX_GPIO43_FUN_WPU_S) -#define IO_MUX_GPIO43_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO43_FUN_WPU_S 8 -/** IO_MUX_GPIO43_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO43_FUN_IE (BIT(9)) -#define IO_MUX_GPIO43_FUN_IE_M (IO_MUX_GPIO43_FUN_IE_V << IO_MUX_GPIO43_FUN_IE_S) -#define IO_MUX_GPIO43_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO43_FUN_IE_S 9 -/** IO_MUX_GPIO43_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO43_FUN_DRV 0x00000003U -#define IO_MUX_GPIO43_FUN_DRV_M (IO_MUX_GPIO43_FUN_DRV_V << IO_MUX_GPIO43_FUN_DRV_S) -#define IO_MUX_GPIO43_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO43_FUN_DRV_S 10 -/** IO_MUX_GPIO43_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO43_MCU_SEL 0x00000007U -#define IO_MUX_GPIO43_MCU_SEL_M (IO_MUX_GPIO43_MCU_SEL_V << IO_MUX_GPIO43_MCU_SEL_S) -#define IO_MUX_GPIO43_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO43_MCU_SEL_S 12 -/** IO_MUX_GPIO43_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO43_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO43_FILTER_EN_M (IO_MUX_GPIO43_FILTER_EN_V << IO_MUX_GPIO43_FILTER_EN_S) -#define IO_MUX_GPIO43_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO43_FILTER_EN_S 15 - -/** IO_MUX_gpio44_REG register - * iomux control register for gpio44 - */ -#define IO_MUX_GPIO44_REG (DR_REG_IO_MUX_BASE + 0xb4) -/** IO_MUX_GPIO44_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_OE (BIT(0)) -#define IO_MUX_GPIO44_MCU_OE_M (IO_MUX_GPIO44_MCU_OE_V << IO_MUX_GPIO44_MCU_OE_S) -#define IO_MUX_GPIO44_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO44_MCU_OE_S 0 -/** IO_MUX_GPIO44_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO44_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO44_SLP_SEL_M (IO_MUX_GPIO44_SLP_SEL_V << IO_MUX_GPIO44_SLP_SEL_S) -#define IO_MUX_GPIO44_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO44_SLP_SEL_S 1 -/** IO_MUX_GPIO44_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO44_MCU_WPD_M (IO_MUX_GPIO44_MCU_WPD_V << IO_MUX_GPIO44_MCU_WPD_S) -#define IO_MUX_GPIO44_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO44_MCU_WPD_S 2 -/** IO_MUX_GPIO44_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO44_MCU_WPU_M (IO_MUX_GPIO44_MCU_WPU_V << IO_MUX_GPIO44_MCU_WPU_S) -#define IO_MUX_GPIO44_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO44_MCU_WPU_S 3 -/** IO_MUX_GPIO44_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO44_MCU_IE (BIT(4)) -#define IO_MUX_GPIO44_MCU_IE_M (IO_MUX_GPIO44_MCU_IE_V << IO_MUX_GPIO44_MCU_IE_S) -#define IO_MUX_GPIO44_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO44_MCU_IE_S 4 -/** IO_MUX_GPIO44_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO44_MCU_DRV 0x00000003U -#define IO_MUX_GPIO44_MCU_DRV_M (IO_MUX_GPIO44_MCU_DRV_V << IO_MUX_GPIO44_MCU_DRV_S) -#define IO_MUX_GPIO44_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO44_MCU_DRV_S 5 -/** IO_MUX_GPIO44_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO44_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO44_FUN_WPD_M (IO_MUX_GPIO44_FUN_WPD_V << IO_MUX_GPIO44_FUN_WPD_S) -#define IO_MUX_GPIO44_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO44_FUN_WPD_S 7 -/** IO_MUX_GPIO44_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO44_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO44_FUN_WPU_M (IO_MUX_GPIO44_FUN_WPU_V << IO_MUX_GPIO44_FUN_WPU_S) -#define IO_MUX_GPIO44_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO44_FUN_WPU_S 8 -/** IO_MUX_GPIO44_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO44_FUN_IE (BIT(9)) -#define IO_MUX_GPIO44_FUN_IE_M (IO_MUX_GPIO44_FUN_IE_V << IO_MUX_GPIO44_FUN_IE_S) -#define IO_MUX_GPIO44_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO44_FUN_IE_S 9 -/** IO_MUX_GPIO44_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO44_FUN_DRV 0x00000003U -#define IO_MUX_GPIO44_FUN_DRV_M (IO_MUX_GPIO44_FUN_DRV_V << IO_MUX_GPIO44_FUN_DRV_S) -#define IO_MUX_GPIO44_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO44_FUN_DRV_S 10 -/** IO_MUX_GPIO44_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO44_MCU_SEL 0x00000007U -#define IO_MUX_GPIO44_MCU_SEL_M (IO_MUX_GPIO44_MCU_SEL_V << IO_MUX_GPIO44_MCU_SEL_S) -#define IO_MUX_GPIO44_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO44_MCU_SEL_S 12 -/** IO_MUX_GPIO44_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO44_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO44_FILTER_EN_M (IO_MUX_GPIO44_FILTER_EN_V << IO_MUX_GPIO44_FILTER_EN_S) -#define IO_MUX_GPIO44_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO44_FILTER_EN_S 15 - -/** IO_MUX_gpio45_REG register - * iomux control register for gpio45 - */ -#define IO_MUX_GPIO45_REG (DR_REG_IO_MUX_BASE + 0xb8) -/** IO_MUX_GPIO45_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_OE (BIT(0)) -#define IO_MUX_GPIO45_MCU_OE_M (IO_MUX_GPIO45_MCU_OE_V << IO_MUX_GPIO45_MCU_OE_S) -#define IO_MUX_GPIO45_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO45_MCU_OE_S 0 -/** IO_MUX_GPIO45_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO45_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO45_SLP_SEL_M (IO_MUX_GPIO45_SLP_SEL_V << IO_MUX_GPIO45_SLP_SEL_S) -#define IO_MUX_GPIO45_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO45_SLP_SEL_S 1 -/** IO_MUX_GPIO45_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO45_MCU_WPD_M (IO_MUX_GPIO45_MCU_WPD_V << IO_MUX_GPIO45_MCU_WPD_S) -#define IO_MUX_GPIO45_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO45_MCU_WPD_S 2 -/** IO_MUX_GPIO45_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO45_MCU_WPU_M (IO_MUX_GPIO45_MCU_WPU_V << IO_MUX_GPIO45_MCU_WPU_S) -#define IO_MUX_GPIO45_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO45_MCU_WPU_S 3 -/** IO_MUX_GPIO45_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO45_MCU_IE (BIT(4)) -#define IO_MUX_GPIO45_MCU_IE_M (IO_MUX_GPIO45_MCU_IE_V << IO_MUX_GPIO45_MCU_IE_S) -#define IO_MUX_GPIO45_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO45_MCU_IE_S 4 -/** IO_MUX_GPIO45_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO45_MCU_DRV 0x00000003U -#define IO_MUX_GPIO45_MCU_DRV_M (IO_MUX_GPIO45_MCU_DRV_V << IO_MUX_GPIO45_MCU_DRV_S) -#define IO_MUX_GPIO45_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO45_MCU_DRV_S 5 -/** IO_MUX_GPIO45_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO45_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO45_FUN_WPD_M (IO_MUX_GPIO45_FUN_WPD_V << IO_MUX_GPIO45_FUN_WPD_S) -#define IO_MUX_GPIO45_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO45_FUN_WPD_S 7 -/** IO_MUX_GPIO45_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO45_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO45_FUN_WPU_M (IO_MUX_GPIO45_FUN_WPU_V << IO_MUX_GPIO45_FUN_WPU_S) -#define IO_MUX_GPIO45_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO45_FUN_WPU_S 8 -/** IO_MUX_GPIO45_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO45_FUN_IE (BIT(9)) -#define IO_MUX_GPIO45_FUN_IE_M (IO_MUX_GPIO45_FUN_IE_V << IO_MUX_GPIO45_FUN_IE_S) -#define IO_MUX_GPIO45_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO45_FUN_IE_S 9 -/** IO_MUX_GPIO45_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO45_FUN_DRV 0x00000003U -#define IO_MUX_GPIO45_FUN_DRV_M (IO_MUX_GPIO45_FUN_DRV_V << IO_MUX_GPIO45_FUN_DRV_S) -#define IO_MUX_GPIO45_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO45_FUN_DRV_S 10 -/** IO_MUX_GPIO45_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO45_MCU_SEL 0x00000007U -#define IO_MUX_GPIO45_MCU_SEL_M (IO_MUX_GPIO45_MCU_SEL_V << IO_MUX_GPIO45_MCU_SEL_S) -#define IO_MUX_GPIO45_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO45_MCU_SEL_S 12 -/** IO_MUX_GPIO45_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO45_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO45_FILTER_EN_M (IO_MUX_GPIO45_FILTER_EN_V << IO_MUX_GPIO45_FILTER_EN_S) -#define IO_MUX_GPIO45_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO45_FILTER_EN_S 15 - -/** IO_MUX_gpio46_REG register - * iomux control register for gpio46 - */ -#define IO_MUX_GPIO46_REG (DR_REG_IO_MUX_BASE + 0xbc) -/** IO_MUX_GPIO46_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_OE (BIT(0)) -#define IO_MUX_GPIO46_MCU_OE_M (IO_MUX_GPIO46_MCU_OE_V << IO_MUX_GPIO46_MCU_OE_S) -#define IO_MUX_GPIO46_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO46_MCU_OE_S 0 -/** IO_MUX_GPIO46_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO46_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO46_SLP_SEL_M (IO_MUX_GPIO46_SLP_SEL_V << IO_MUX_GPIO46_SLP_SEL_S) -#define IO_MUX_GPIO46_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO46_SLP_SEL_S 1 -/** IO_MUX_GPIO46_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO46_MCU_WPD_M (IO_MUX_GPIO46_MCU_WPD_V << IO_MUX_GPIO46_MCU_WPD_S) -#define IO_MUX_GPIO46_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO46_MCU_WPD_S 2 -/** IO_MUX_GPIO46_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO46_MCU_WPU_M (IO_MUX_GPIO46_MCU_WPU_V << IO_MUX_GPIO46_MCU_WPU_S) -#define IO_MUX_GPIO46_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO46_MCU_WPU_S 3 -/** IO_MUX_GPIO46_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO46_MCU_IE (BIT(4)) -#define IO_MUX_GPIO46_MCU_IE_M (IO_MUX_GPIO46_MCU_IE_V << IO_MUX_GPIO46_MCU_IE_S) -#define IO_MUX_GPIO46_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO46_MCU_IE_S 4 -/** IO_MUX_GPIO46_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO46_MCU_DRV 0x00000003U -#define IO_MUX_GPIO46_MCU_DRV_M (IO_MUX_GPIO46_MCU_DRV_V << IO_MUX_GPIO46_MCU_DRV_S) -#define IO_MUX_GPIO46_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO46_MCU_DRV_S 5 -/** IO_MUX_GPIO46_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO46_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO46_FUN_WPD_M (IO_MUX_GPIO46_FUN_WPD_V << IO_MUX_GPIO46_FUN_WPD_S) -#define IO_MUX_GPIO46_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO46_FUN_WPD_S 7 -/** IO_MUX_GPIO46_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO46_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO46_FUN_WPU_M (IO_MUX_GPIO46_FUN_WPU_V << IO_MUX_GPIO46_FUN_WPU_S) -#define IO_MUX_GPIO46_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO46_FUN_WPU_S 8 -/** IO_MUX_GPIO46_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO46_FUN_IE (BIT(9)) -#define IO_MUX_GPIO46_FUN_IE_M (IO_MUX_GPIO46_FUN_IE_V << IO_MUX_GPIO46_FUN_IE_S) -#define IO_MUX_GPIO46_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO46_FUN_IE_S 9 -/** IO_MUX_GPIO46_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO46_FUN_DRV 0x00000003U -#define IO_MUX_GPIO46_FUN_DRV_M (IO_MUX_GPIO46_FUN_DRV_V << IO_MUX_GPIO46_FUN_DRV_S) -#define IO_MUX_GPIO46_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO46_FUN_DRV_S 10 -/** IO_MUX_GPIO46_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO46_MCU_SEL 0x00000007U -#define IO_MUX_GPIO46_MCU_SEL_M (IO_MUX_GPIO46_MCU_SEL_V << IO_MUX_GPIO46_MCU_SEL_S) -#define IO_MUX_GPIO46_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO46_MCU_SEL_S 12 -/** IO_MUX_GPIO46_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO46_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO46_FILTER_EN_M (IO_MUX_GPIO46_FILTER_EN_V << IO_MUX_GPIO46_FILTER_EN_S) -#define IO_MUX_GPIO46_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO46_FILTER_EN_S 15 - -/** IO_MUX_gpio47_REG register - * iomux control register for gpio47 - */ -#define IO_MUX_GPIO47_REG (DR_REG_IO_MUX_BASE + 0xc0) -/** IO_MUX_GPIO47_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_OE (BIT(0)) -#define IO_MUX_GPIO47_MCU_OE_M (IO_MUX_GPIO47_MCU_OE_V << IO_MUX_GPIO47_MCU_OE_S) -#define IO_MUX_GPIO47_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO47_MCU_OE_S 0 -/** IO_MUX_GPIO47_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO47_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO47_SLP_SEL_M (IO_MUX_GPIO47_SLP_SEL_V << IO_MUX_GPIO47_SLP_SEL_S) -#define IO_MUX_GPIO47_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO47_SLP_SEL_S 1 -/** IO_MUX_GPIO47_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO47_MCU_WPD_M (IO_MUX_GPIO47_MCU_WPD_V << IO_MUX_GPIO47_MCU_WPD_S) -#define IO_MUX_GPIO47_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO47_MCU_WPD_S 2 -/** IO_MUX_GPIO47_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO47_MCU_WPU_M (IO_MUX_GPIO47_MCU_WPU_V << IO_MUX_GPIO47_MCU_WPU_S) -#define IO_MUX_GPIO47_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO47_MCU_WPU_S 3 -/** IO_MUX_GPIO47_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO47_MCU_IE (BIT(4)) -#define IO_MUX_GPIO47_MCU_IE_M (IO_MUX_GPIO47_MCU_IE_V << IO_MUX_GPIO47_MCU_IE_S) -#define IO_MUX_GPIO47_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO47_MCU_IE_S 4 -/** IO_MUX_GPIO47_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO47_MCU_DRV 0x00000003U -#define IO_MUX_GPIO47_MCU_DRV_M (IO_MUX_GPIO47_MCU_DRV_V << IO_MUX_GPIO47_MCU_DRV_S) -#define IO_MUX_GPIO47_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO47_MCU_DRV_S 5 -/** IO_MUX_GPIO47_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO47_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO47_FUN_WPD_M (IO_MUX_GPIO47_FUN_WPD_V << IO_MUX_GPIO47_FUN_WPD_S) -#define IO_MUX_GPIO47_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO47_FUN_WPD_S 7 -/** IO_MUX_GPIO47_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO47_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO47_FUN_WPU_M (IO_MUX_GPIO47_FUN_WPU_V << IO_MUX_GPIO47_FUN_WPU_S) -#define IO_MUX_GPIO47_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO47_FUN_WPU_S 8 -/** IO_MUX_GPIO47_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO47_FUN_IE (BIT(9)) -#define IO_MUX_GPIO47_FUN_IE_M (IO_MUX_GPIO47_FUN_IE_V << IO_MUX_GPIO47_FUN_IE_S) -#define IO_MUX_GPIO47_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO47_FUN_IE_S 9 -/** IO_MUX_GPIO47_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO47_FUN_DRV 0x00000003U -#define IO_MUX_GPIO47_FUN_DRV_M (IO_MUX_GPIO47_FUN_DRV_V << IO_MUX_GPIO47_FUN_DRV_S) -#define IO_MUX_GPIO47_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO47_FUN_DRV_S 10 -/** IO_MUX_GPIO47_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO47_MCU_SEL 0x00000007U -#define IO_MUX_GPIO47_MCU_SEL_M (IO_MUX_GPIO47_MCU_SEL_V << IO_MUX_GPIO47_MCU_SEL_S) -#define IO_MUX_GPIO47_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO47_MCU_SEL_S 12 -/** IO_MUX_GPIO47_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO47_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO47_FILTER_EN_M (IO_MUX_GPIO47_FILTER_EN_V << IO_MUX_GPIO47_FILTER_EN_S) -#define IO_MUX_GPIO47_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO47_FILTER_EN_S 15 - -/** IO_MUX_gpio48_REG register - * iomux control register for gpio48 - */ -#define IO_MUX_GPIO48_REG (DR_REG_IO_MUX_BASE + 0xc4) -/** IO_MUX_GPIO48_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_OE (BIT(0)) -#define IO_MUX_GPIO48_MCU_OE_M (IO_MUX_GPIO48_MCU_OE_V << IO_MUX_GPIO48_MCU_OE_S) -#define IO_MUX_GPIO48_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO48_MCU_OE_S 0 -/** IO_MUX_GPIO48_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO48_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO48_SLP_SEL_M (IO_MUX_GPIO48_SLP_SEL_V << IO_MUX_GPIO48_SLP_SEL_S) -#define IO_MUX_GPIO48_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO48_SLP_SEL_S 1 -/** IO_MUX_GPIO48_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO48_MCU_WPD_M (IO_MUX_GPIO48_MCU_WPD_V << IO_MUX_GPIO48_MCU_WPD_S) -#define IO_MUX_GPIO48_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO48_MCU_WPD_S 2 -/** IO_MUX_GPIO48_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO48_MCU_WPU_M (IO_MUX_GPIO48_MCU_WPU_V << IO_MUX_GPIO48_MCU_WPU_S) -#define IO_MUX_GPIO48_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO48_MCU_WPU_S 3 -/** IO_MUX_GPIO48_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO48_MCU_IE (BIT(4)) -#define IO_MUX_GPIO48_MCU_IE_M (IO_MUX_GPIO48_MCU_IE_V << IO_MUX_GPIO48_MCU_IE_S) -#define IO_MUX_GPIO48_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO48_MCU_IE_S 4 -/** IO_MUX_GPIO48_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO48_MCU_DRV 0x00000003U -#define IO_MUX_GPIO48_MCU_DRV_M (IO_MUX_GPIO48_MCU_DRV_V << IO_MUX_GPIO48_MCU_DRV_S) -#define IO_MUX_GPIO48_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO48_MCU_DRV_S 5 -/** IO_MUX_GPIO48_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO48_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO48_FUN_WPD_M (IO_MUX_GPIO48_FUN_WPD_V << IO_MUX_GPIO48_FUN_WPD_S) -#define IO_MUX_GPIO48_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO48_FUN_WPD_S 7 -/** IO_MUX_GPIO48_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO48_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO48_FUN_WPU_M (IO_MUX_GPIO48_FUN_WPU_V << IO_MUX_GPIO48_FUN_WPU_S) -#define IO_MUX_GPIO48_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO48_FUN_WPU_S 8 -/** IO_MUX_GPIO48_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO48_FUN_IE (BIT(9)) -#define IO_MUX_GPIO48_FUN_IE_M (IO_MUX_GPIO48_FUN_IE_V << IO_MUX_GPIO48_FUN_IE_S) -#define IO_MUX_GPIO48_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO48_FUN_IE_S 9 -/** IO_MUX_GPIO48_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO48_FUN_DRV 0x00000003U -#define IO_MUX_GPIO48_FUN_DRV_M (IO_MUX_GPIO48_FUN_DRV_V << IO_MUX_GPIO48_FUN_DRV_S) -#define IO_MUX_GPIO48_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO48_FUN_DRV_S 10 -/** IO_MUX_GPIO48_MCU_SEL : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO48_MCU_SEL 0x00000007U -#define IO_MUX_GPIO48_MCU_SEL_M (IO_MUX_GPIO48_MCU_SEL_V << IO_MUX_GPIO48_MCU_SEL_S) -#define IO_MUX_GPIO48_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO48_MCU_SEL_S 12 -/** IO_MUX_GPIO48_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO48_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO48_FILTER_EN_M (IO_MUX_GPIO48_FILTER_EN_V << IO_MUX_GPIO48_FILTER_EN_S) -#define IO_MUX_GPIO48_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO48_FILTER_EN_S 15 - -/** IO_MUX_gpio49_REG register - * iomux control register for gpio49 - */ -#define IO_MUX_GPIO49_REG (DR_REG_IO_MUX_BASE + 0xc8) -/** IO_MUX_GPIO49_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_OE (BIT(0)) -#define IO_MUX_GPIO49_MCU_OE_M (IO_MUX_GPIO49_MCU_OE_V << IO_MUX_GPIO49_MCU_OE_S) -#define IO_MUX_GPIO49_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO49_MCU_OE_S 0 -/** IO_MUX_GPIO49_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO49_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO49_SLP_SEL_M (IO_MUX_GPIO49_SLP_SEL_V << IO_MUX_GPIO49_SLP_SEL_S) -#define IO_MUX_GPIO49_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO49_SLP_SEL_S 1 -/** IO_MUX_GPIO49_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO49_MCU_WPD_M (IO_MUX_GPIO49_MCU_WPD_V << IO_MUX_GPIO49_MCU_WPD_S) -#define IO_MUX_GPIO49_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO49_MCU_WPD_S 2 -/** IO_MUX_GPIO49_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO49_MCU_WPU_M (IO_MUX_GPIO49_MCU_WPU_V << IO_MUX_GPIO49_MCU_WPU_S) -#define IO_MUX_GPIO49_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO49_MCU_WPU_S 3 -/** IO_MUX_GPIO49_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO49_MCU_IE (BIT(4)) -#define IO_MUX_GPIO49_MCU_IE_M (IO_MUX_GPIO49_MCU_IE_V << IO_MUX_GPIO49_MCU_IE_S) -#define IO_MUX_GPIO49_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO49_MCU_IE_S 4 -/** IO_MUX_GPIO49_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO49_MCU_DRV 0x00000003U -#define IO_MUX_GPIO49_MCU_DRV_M (IO_MUX_GPIO49_MCU_DRV_V << IO_MUX_GPIO49_MCU_DRV_S) -#define IO_MUX_GPIO49_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO49_MCU_DRV_S 5 -/** IO_MUX_GPIO49_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO49_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO49_FUN_WPD_M (IO_MUX_GPIO49_FUN_WPD_V << IO_MUX_GPIO49_FUN_WPD_S) -#define IO_MUX_GPIO49_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO49_FUN_WPD_S 7 -/** IO_MUX_GPIO49_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO49_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO49_FUN_WPU_M (IO_MUX_GPIO49_FUN_WPU_V << IO_MUX_GPIO49_FUN_WPU_S) -#define IO_MUX_GPIO49_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO49_FUN_WPU_S 8 -/** IO_MUX_GPIO49_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO49_FUN_IE (BIT(9)) -#define IO_MUX_GPIO49_FUN_IE_M (IO_MUX_GPIO49_FUN_IE_V << IO_MUX_GPIO49_FUN_IE_S) -#define IO_MUX_GPIO49_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO49_FUN_IE_S 9 -/** IO_MUX_GPIO49_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO49_FUN_DRV 0x00000003U -#define IO_MUX_GPIO49_FUN_DRV_M (IO_MUX_GPIO49_FUN_DRV_V << IO_MUX_GPIO49_FUN_DRV_S) -#define IO_MUX_GPIO49_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO49_FUN_DRV_S 10 -/** IO_MUX_GPIO49_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO49_MCU_SEL 0x00000007U -#define IO_MUX_GPIO49_MCU_SEL_M (IO_MUX_GPIO49_MCU_SEL_V << IO_MUX_GPIO49_MCU_SEL_S) -#define IO_MUX_GPIO49_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO49_MCU_SEL_S 12 -/** IO_MUX_GPIO49_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO49_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO49_FILTER_EN_M (IO_MUX_GPIO49_FILTER_EN_V << IO_MUX_GPIO49_FILTER_EN_S) -#define IO_MUX_GPIO49_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO49_FILTER_EN_S 15 - -/** IO_MUX_gpio50_REG register - * iomux control register for gpio50 - */ -#define IO_MUX_GPIO50_REG (DR_REG_IO_MUX_BASE + 0xcc) -/** IO_MUX_GPIO50_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_OE (BIT(0)) -#define IO_MUX_GPIO50_MCU_OE_M (IO_MUX_GPIO50_MCU_OE_V << IO_MUX_GPIO50_MCU_OE_S) -#define IO_MUX_GPIO50_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO50_MCU_OE_S 0 -/** IO_MUX_GPIO50_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO50_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO50_SLP_SEL_M (IO_MUX_GPIO50_SLP_SEL_V << IO_MUX_GPIO50_SLP_SEL_S) -#define IO_MUX_GPIO50_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO50_SLP_SEL_S 1 -/** IO_MUX_GPIO50_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO50_MCU_WPD_M (IO_MUX_GPIO50_MCU_WPD_V << IO_MUX_GPIO50_MCU_WPD_S) -#define IO_MUX_GPIO50_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO50_MCU_WPD_S 2 -/** IO_MUX_GPIO50_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO50_MCU_WPU_M (IO_MUX_GPIO50_MCU_WPU_V << IO_MUX_GPIO50_MCU_WPU_S) -#define IO_MUX_GPIO50_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO50_MCU_WPU_S 3 -/** IO_MUX_GPIO50_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO50_MCU_IE (BIT(4)) -#define IO_MUX_GPIO50_MCU_IE_M (IO_MUX_GPIO50_MCU_IE_V << IO_MUX_GPIO50_MCU_IE_S) -#define IO_MUX_GPIO50_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO50_MCU_IE_S 4 -/** IO_MUX_GPIO50_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO50_MCU_DRV 0x00000003U -#define IO_MUX_GPIO50_MCU_DRV_M (IO_MUX_GPIO50_MCU_DRV_V << IO_MUX_GPIO50_MCU_DRV_S) -#define IO_MUX_GPIO50_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO50_MCU_DRV_S 5 -/** IO_MUX_GPIO50_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO50_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO50_FUN_WPD_M (IO_MUX_GPIO50_FUN_WPD_V << IO_MUX_GPIO50_FUN_WPD_S) -#define IO_MUX_GPIO50_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO50_FUN_WPD_S 7 -/** IO_MUX_GPIO50_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO50_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO50_FUN_WPU_M (IO_MUX_GPIO50_FUN_WPU_V << IO_MUX_GPIO50_FUN_WPU_S) -#define IO_MUX_GPIO50_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO50_FUN_WPU_S 8 -/** IO_MUX_GPIO50_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO50_FUN_IE (BIT(9)) -#define IO_MUX_GPIO50_FUN_IE_M (IO_MUX_GPIO50_FUN_IE_V << IO_MUX_GPIO50_FUN_IE_S) -#define IO_MUX_GPIO50_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO50_FUN_IE_S 9 -/** IO_MUX_GPIO50_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO50_FUN_DRV 0x00000003U -#define IO_MUX_GPIO50_FUN_DRV_M (IO_MUX_GPIO50_FUN_DRV_V << IO_MUX_GPIO50_FUN_DRV_S) -#define IO_MUX_GPIO50_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO50_FUN_DRV_S 10 -/** IO_MUX_GPIO50_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO50_MCU_SEL 0x00000007U -#define IO_MUX_GPIO50_MCU_SEL_M (IO_MUX_GPIO50_MCU_SEL_V << IO_MUX_GPIO50_MCU_SEL_S) -#define IO_MUX_GPIO50_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO50_MCU_SEL_S 12 -/** IO_MUX_GPIO50_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO50_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO50_FILTER_EN_M (IO_MUX_GPIO50_FILTER_EN_V << IO_MUX_GPIO50_FILTER_EN_S) -#define IO_MUX_GPIO50_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO50_FILTER_EN_S 15 - -/** IO_MUX_gpio51_REG register - * iomux control register for gpio51 - */ -#define IO_MUX_GPIO51_REG (DR_REG_IO_MUX_BASE + 0xd0) -/** IO_MUX_GPIO51_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_OE (BIT(0)) -#define IO_MUX_GPIO51_MCU_OE_M (IO_MUX_GPIO51_MCU_OE_V << IO_MUX_GPIO51_MCU_OE_S) -#define IO_MUX_GPIO51_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO51_MCU_OE_S 0 -/** IO_MUX_GPIO51_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO51_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO51_SLP_SEL_M (IO_MUX_GPIO51_SLP_SEL_V << IO_MUX_GPIO51_SLP_SEL_S) -#define IO_MUX_GPIO51_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO51_SLP_SEL_S 1 -/** IO_MUX_GPIO51_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO51_MCU_WPD_M (IO_MUX_GPIO51_MCU_WPD_V << IO_MUX_GPIO51_MCU_WPD_S) -#define IO_MUX_GPIO51_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO51_MCU_WPD_S 2 -/** IO_MUX_GPIO51_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO51_MCU_WPU_M (IO_MUX_GPIO51_MCU_WPU_V << IO_MUX_GPIO51_MCU_WPU_S) -#define IO_MUX_GPIO51_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO51_MCU_WPU_S 3 -/** IO_MUX_GPIO51_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO51_MCU_IE (BIT(4)) -#define IO_MUX_GPIO51_MCU_IE_M (IO_MUX_GPIO51_MCU_IE_V << IO_MUX_GPIO51_MCU_IE_S) -#define IO_MUX_GPIO51_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO51_MCU_IE_S 4 -/** IO_MUX_GPIO51_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO51_MCU_DRV 0x00000003U -#define IO_MUX_GPIO51_MCU_DRV_M (IO_MUX_GPIO51_MCU_DRV_V << IO_MUX_GPIO51_MCU_DRV_S) -#define IO_MUX_GPIO51_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO51_MCU_DRV_S 5 -/** IO_MUX_GPIO51_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO51_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO51_FUN_WPD_M (IO_MUX_GPIO51_FUN_WPD_V << IO_MUX_GPIO51_FUN_WPD_S) -#define IO_MUX_GPIO51_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO51_FUN_WPD_S 7 -/** IO_MUX_GPIO51_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO51_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO51_FUN_WPU_M (IO_MUX_GPIO51_FUN_WPU_V << IO_MUX_GPIO51_FUN_WPU_S) -#define IO_MUX_GPIO51_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO51_FUN_WPU_S 8 -/** IO_MUX_GPIO51_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO51_FUN_IE (BIT(9)) -#define IO_MUX_GPIO51_FUN_IE_M (IO_MUX_GPIO51_FUN_IE_V << IO_MUX_GPIO51_FUN_IE_S) -#define IO_MUX_GPIO51_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO51_FUN_IE_S 9 -/** IO_MUX_GPIO51_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO51_FUN_DRV 0x00000003U -#define IO_MUX_GPIO51_FUN_DRV_M (IO_MUX_GPIO51_FUN_DRV_V << IO_MUX_GPIO51_FUN_DRV_S) -#define IO_MUX_GPIO51_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO51_FUN_DRV_S 10 -/** IO_MUX_GPIO51_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO51_MCU_SEL 0x00000007U -#define IO_MUX_GPIO51_MCU_SEL_M (IO_MUX_GPIO51_MCU_SEL_V << IO_MUX_GPIO51_MCU_SEL_S) -#define IO_MUX_GPIO51_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO51_MCU_SEL_S 12 -/** IO_MUX_GPIO51_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO51_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO51_FILTER_EN_M (IO_MUX_GPIO51_FILTER_EN_V << IO_MUX_GPIO51_FILTER_EN_S) -#define IO_MUX_GPIO51_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO51_FILTER_EN_S 15 - -/** IO_MUX_gpio52_REG register - * iomux control register for gpio52 - */ -#define IO_MUX_GPIO52_REG (DR_REG_IO_MUX_BASE + 0xd4) -/** IO_MUX_GPIO52_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_OE (BIT(0)) -#define IO_MUX_GPIO52_MCU_OE_M (IO_MUX_GPIO52_MCU_OE_V << IO_MUX_GPIO52_MCU_OE_S) -#define IO_MUX_GPIO52_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO52_MCU_OE_S 0 -/** IO_MUX_GPIO52_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO52_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO52_SLP_SEL_M (IO_MUX_GPIO52_SLP_SEL_V << IO_MUX_GPIO52_SLP_SEL_S) -#define IO_MUX_GPIO52_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO52_SLP_SEL_S 1 -/** IO_MUX_GPIO52_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO52_MCU_WPD_M (IO_MUX_GPIO52_MCU_WPD_V << IO_MUX_GPIO52_MCU_WPD_S) -#define IO_MUX_GPIO52_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO52_MCU_WPD_S 2 -/** IO_MUX_GPIO52_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO52_MCU_WPU_M (IO_MUX_GPIO52_MCU_WPU_V << IO_MUX_GPIO52_MCU_WPU_S) -#define IO_MUX_GPIO52_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO52_MCU_WPU_S 3 -/** IO_MUX_GPIO52_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO52_MCU_IE (BIT(4)) -#define IO_MUX_GPIO52_MCU_IE_M (IO_MUX_GPIO52_MCU_IE_V << IO_MUX_GPIO52_MCU_IE_S) -#define IO_MUX_GPIO52_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO52_MCU_IE_S 4 -/** IO_MUX_GPIO52_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO52_MCU_DRV 0x00000003U -#define IO_MUX_GPIO52_MCU_DRV_M (IO_MUX_GPIO52_MCU_DRV_V << IO_MUX_GPIO52_MCU_DRV_S) -#define IO_MUX_GPIO52_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO52_MCU_DRV_S 5 -/** IO_MUX_GPIO52_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO52_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO52_FUN_WPD_M (IO_MUX_GPIO52_FUN_WPD_V << IO_MUX_GPIO52_FUN_WPD_S) -#define IO_MUX_GPIO52_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO52_FUN_WPD_S 7 -/** IO_MUX_GPIO52_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO52_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO52_FUN_WPU_M (IO_MUX_GPIO52_FUN_WPU_V << IO_MUX_GPIO52_FUN_WPU_S) -#define IO_MUX_GPIO52_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO52_FUN_WPU_S 8 -/** IO_MUX_GPIO52_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO52_FUN_IE (BIT(9)) -#define IO_MUX_GPIO52_FUN_IE_M (IO_MUX_GPIO52_FUN_IE_V << IO_MUX_GPIO52_FUN_IE_S) -#define IO_MUX_GPIO52_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO52_FUN_IE_S 9 -/** IO_MUX_GPIO52_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO52_FUN_DRV 0x00000003U -#define IO_MUX_GPIO52_FUN_DRV_M (IO_MUX_GPIO52_FUN_DRV_V << IO_MUX_GPIO52_FUN_DRV_S) -#define IO_MUX_GPIO52_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO52_FUN_DRV_S 10 -/** IO_MUX_GPIO52_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO52_MCU_SEL 0x00000007U -#define IO_MUX_GPIO52_MCU_SEL_M (IO_MUX_GPIO52_MCU_SEL_V << IO_MUX_GPIO52_MCU_SEL_S) -#define IO_MUX_GPIO52_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO52_MCU_SEL_S 12 -/** IO_MUX_GPIO52_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO52_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO52_FILTER_EN_M (IO_MUX_GPIO52_FILTER_EN_V << IO_MUX_GPIO52_FILTER_EN_S) -#define IO_MUX_GPIO52_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO52_FILTER_EN_S 15 - -/** IO_MUX_gpio53_REG register - * iomux control register for gpio53 - */ -#define IO_MUX_GPIO53_REG (DR_REG_IO_MUX_BASE + 0xd8) -/** IO_MUX_GPIO53_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_OE (BIT(0)) -#define IO_MUX_GPIO53_MCU_OE_M (IO_MUX_GPIO53_MCU_OE_V << IO_MUX_GPIO53_MCU_OE_S) -#define IO_MUX_GPIO53_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO53_MCU_OE_S 0 -/** IO_MUX_GPIO53_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO53_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO53_SLP_SEL_M (IO_MUX_GPIO53_SLP_SEL_V << IO_MUX_GPIO53_SLP_SEL_S) -#define IO_MUX_GPIO53_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO53_SLP_SEL_S 1 -/** IO_MUX_GPIO53_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO53_MCU_WPD_M (IO_MUX_GPIO53_MCU_WPD_V << IO_MUX_GPIO53_MCU_WPD_S) -#define IO_MUX_GPIO53_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO53_MCU_WPD_S 2 -/** IO_MUX_GPIO53_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO53_MCU_WPU_M (IO_MUX_GPIO53_MCU_WPU_V << IO_MUX_GPIO53_MCU_WPU_S) -#define IO_MUX_GPIO53_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO53_MCU_WPU_S 3 -/** IO_MUX_GPIO53_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO53_MCU_IE (BIT(4)) -#define IO_MUX_GPIO53_MCU_IE_M (IO_MUX_GPIO53_MCU_IE_V << IO_MUX_GPIO53_MCU_IE_S) -#define IO_MUX_GPIO53_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO53_MCU_IE_S 4 -/** IO_MUX_GPIO53_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO53_MCU_DRV 0x00000003U -#define IO_MUX_GPIO53_MCU_DRV_M (IO_MUX_GPIO53_MCU_DRV_V << IO_MUX_GPIO53_MCU_DRV_S) -#define IO_MUX_GPIO53_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO53_MCU_DRV_S 5 -/** IO_MUX_GPIO53_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO53_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO53_FUN_WPD_M (IO_MUX_GPIO53_FUN_WPD_V << IO_MUX_GPIO53_FUN_WPD_S) -#define IO_MUX_GPIO53_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO53_FUN_WPD_S 7 -/** IO_MUX_GPIO53_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO53_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO53_FUN_WPU_M (IO_MUX_GPIO53_FUN_WPU_V << IO_MUX_GPIO53_FUN_WPU_S) -#define IO_MUX_GPIO53_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO53_FUN_WPU_S 8 -/** IO_MUX_GPIO53_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO53_FUN_IE (BIT(9)) -#define IO_MUX_GPIO53_FUN_IE_M (IO_MUX_GPIO53_FUN_IE_V << IO_MUX_GPIO53_FUN_IE_S) -#define IO_MUX_GPIO53_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO53_FUN_IE_S 9 -/** IO_MUX_GPIO53_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO53_FUN_DRV 0x00000003U -#define IO_MUX_GPIO53_FUN_DRV_M (IO_MUX_GPIO53_FUN_DRV_V << IO_MUX_GPIO53_FUN_DRV_S) -#define IO_MUX_GPIO53_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO53_FUN_DRV_S 10 -/** IO_MUX_GPIO53_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO53_MCU_SEL 0x00000007U -#define IO_MUX_GPIO53_MCU_SEL_M (IO_MUX_GPIO53_MCU_SEL_V << IO_MUX_GPIO53_MCU_SEL_S) -#define IO_MUX_GPIO53_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO53_MCU_SEL_S 12 -/** IO_MUX_GPIO53_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO53_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO53_FILTER_EN_M (IO_MUX_GPIO53_FILTER_EN_V << IO_MUX_GPIO53_FILTER_EN_S) -#define IO_MUX_GPIO53_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO53_FILTER_EN_S 15 - -/** IO_MUX_gpio54_REG register - * iomux control register for gpio54 - */ -#define IO_MUX_GPIO54_REG (DR_REG_IO_MUX_BASE + 0xdc) -/** IO_MUX_GPIO54_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_OE (BIT(0)) -#define IO_MUX_GPIO54_MCU_OE_M (IO_MUX_GPIO54_MCU_OE_V << IO_MUX_GPIO54_MCU_OE_S) -#define IO_MUX_GPIO54_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO54_MCU_OE_S 0 -/** IO_MUX_GPIO54_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO54_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO54_SLP_SEL_M (IO_MUX_GPIO54_SLP_SEL_V << IO_MUX_GPIO54_SLP_SEL_S) -#define IO_MUX_GPIO54_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO54_SLP_SEL_S 1 -/** IO_MUX_GPIO54_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO54_MCU_WPD_M (IO_MUX_GPIO54_MCU_WPD_V << IO_MUX_GPIO54_MCU_WPD_S) -#define IO_MUX_GPIO54_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO54_MCU_WPD_S 2 -/** IO_MUX_GPIO54_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO54_MCU_WPU_M (IO_MUX_GPIO54_MCU_WPU_V << IO_MUX_GPIO54_MCU_WPU_S) -#define IO_MUX_GPIO54_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO54_MCU_WPU_S 3 -/** IO_MUX_GPIO54_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO54_MCU_IE (BIT(4)) -#define IO_MUX_GPIO54_MCU_IE_M (IO_MUX_GPIO54_MCU_IE_V << IO_MUX_GPIO54_MCU_IE_S) -#define IO_MUX_GPIO54_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO54_MCU_IE_S 4 -/** IO_MUX_GPIO54_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO54_MCU_DRV 0x00000003U -#define IO_MUX_GPIO54_MCU_DRV_M (IO_MUX_GPIO54_MCU_DRV_V << IO_MUX_GPIO54_MCU_DRV_S) -#define IO_MUX_GPIO54_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO54_MCU_DRV_S 5 -/** IO_MUX_GPIO54_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO54_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO54_FUN_WPD_M (IO_MUX_GPIO54_FUN_WPD_V << IO_MUX_GPIO54_FUN_WPD_S) -#define IO_MUX_GPIO54_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO54_FUN_WPD_S 7 -/** IO_MUX_GPIO54_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO54_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO54_FUN_WPU_M (IO_MUX_GPIO54_FUN_WPU_V << IO_MUX_GPIO54_FUN_WPU_S) -#define IO_MUX_GPIO54_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO54_FUN_WPU_S 8 -/** IO_MUX_GPIO54_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO54_FUN_IE (BIT(9)) -#define IO_MUX_GPIO54_FUN_IE_M (IO_MUX_GPIO54_FUN_IE_V << IO_MUX_GPIO54_FUN_IE_S) -#define IO_MUX_GPIO54_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO54_FUN_IE_S 9 -/** IO_MUX_GPIO54_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO54_FUN_DRV 0x00000003U -#define IO_MUX_GPIO54_FUN_DRV_M (IO_MUX_GPIO54_FUN_DRV_V << IO_MUX_GPIO54_FUN_DRV_S) -#define IO_MUX_GPIO54_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO54_FUN_DRV_S 10 -/** IO_MUX_GPIO54_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO54_MCU_SEL 0x00000007U -#define IO_MUX_GPIO54_MCU_SEL_M (IO_MUX_GPIO54_MCU_SEL_V << IO_MUX_GPIO54_MCU_SEL_S) -#define IO_MUX_GPIO54_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO54_MCU_SEL_S 12 -/** IO_MUX_GPIO54_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO54_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO54_FILTER_EN_M (IO_MUX_GPIO54_FILTER_EN_V << IO_MUX_GPIO54_FILTER_EN_S) -#define IO_MUX_GPIO54_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO54_FILTER_EN_S 15 - -/** IO_MUX_gpio55_REG register - * iomux control register for gpio55 - */ -#define IO_MUX_GPIO55_REG (DR_REG_IO_MUX_BASE + 0xe0) -/** IO_MUX_GPIO55_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_OE (BIT(0)) -#define IO_MUX_GPIO55_MCU_OE_M (IO_MUX_GPIO55_MCU_OE_V << IO_MUX_GPIO55_MCU_OE_S) -#define IO_MUX_GPIO55_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO55_MCU_OE_S 0 -/** IO_MUX_GPIO55_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO55_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO55_SLP_SEL_M (IO_MUX_GPIO55_SLP_SEL_V << IO_MUX_GPIO55_SLP_SEL_S) -#define IO_MUX_GPIO55_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO55_SLP_SEL_S 1 -/** IO_MUX_GPIO55_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO55_MCU_WPD_M (IO_MUX_GPIO55_MCU_WPD_V << IO_MUX_GPIO55_MCU_WPD_S) -#define IO_MUX_GPIO55_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO55_MCU_WPD_S 2 -/** IO_MUX_GPIO55_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO55_MCU_WPU_M (IO_MUX_GPIO55_MCU_WPU_V << IO_MUX_GPIO55_MCU_WPU_S) -#define IO_MUX_GPIO55_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO55_MCU_WPU_S 3 -/** IO_MUX_GPIO55_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO55_MCU_IE (BIT(4)) -#define IO_MUX_GPIO55_MCU_IE_M (IO_MUX_GPIO55_MCU_IE_V << IO_MUX_GPIO55_MCU_IE_S) -#define IO_MUX_GPIO55_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO55_MCU_IE_S 4 -/** IO_MUX_GPIO55_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO55_MCU_DRV 0x00000003U -#define IO_MUX_GPIO55_MCU_DRV_M (IO_MUX_GPIO55_MCU_DRV_V << IO_MUX_GPIO55_MCU_DRV_S) -#define IO_MUX_GPIO55_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO55_MCU_DRV_S 5 -/** IO_MUX_GPIO55_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO55_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO55_FUN_WPD_M (IO_MUX_GPIO55_FUN_WPD_V << IO_MUX_GPIO55_FUN_WPD_S) -#define IO_MUX_GPIO55_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO55_FUN_WPD_S 7 -/** IO_MUX_GPIO55_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO55_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO55_FUN_WPU_M (IO_MUX_GPIO55_FUN_WPU_V << IO_MUX_GPIO55_FUN_WPU_S) -#define IO_MUX_GPIO55_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO55_FUN_WPU_S 8 -/** IO_MUX_GPIO55_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO55_FUN_IE (BIT(9)) -#define IO_MUX_GPIO55_FUN_IE_M (IO_MUX_GPIO55_FUN_IE_V << IO_MUX_GPIO55_FUN_IE_S) -#define IO_MUX_GPIO55_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO55_FUN_IE_S 9 -/** IO_MUX_GPIO55_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO55_FUN_DRV 0x00000003U -#define IO_MUX_GPIO55_FUN_DRV_M (IO_MUX_GPIO55_FUN_DRV_V << IO_MUX_GPIO55_FUN_DRV_S) -#define IO_MUX_GPIO55_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO55_FUN_DRV_S 10 -/** IO_MUX_GPIO55_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO55_MCU_SEL 0x00000007U -#define IO_MUX_GPIO55_MCU_SEL_M (IO_MUX_GPIO55_MCU_SEL_V << IO_MUX_GPIO55_MCU_SEL_S) -#define IO_MUX_GPIO55_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO55_MCU_SEL_S 12 -/** IO_MUX_GPIO55_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO55_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO55_FILTER_EN_M (IO_MUX_GPIO55_FILTER_EN_V << IO_MUX_GPIO55_FILTER_EN_S) -#define IO_MUX_GPIO55_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO55_FILTER_EN_S 15 - -/** IO_MUX_gpio56_REG register - * iomux control register for gpio56 - */ -#define IO_MUX_GPIO56_REG (DR_REG_IO_MUX_BASE + 0xe4) -/** IO_MUX_GPIO56_MCU_OE : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_OE (BIT(0)) -#define IO_MUX_GPIO56_MCU_OE_M (IO_MUX_GPIO56_MCU_OE_V << IO_MUX_GPIO56_MCU_OE_S) -#define IO_MUX_GPIO56_MCU_OE_V 0x00000001U -#define IO_MUX_GPIO56_MCU_OE_S 0 -/** IO_MUX_GPIO56_SLP_SEL : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ -#define IO_MUX_GPIO56_SLP_SEL (BIT(1)) -#define IO_MUX_GPIO56_SLP_SEL_M (IO_MUX_GPIO56_SLP_SEL_V << IO_MUX_GPIO56_SLP_SEL_S) -#define IO_MUX_GPIO56_SLP_SEL_V 0x00000001U -#define IO_MUX_GPIO56_SLP_SEL_S 1 -/** IO_MUX_GPIO56_MCU_WPD : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_WPD (BIT(2)) -#define IO_MUX_GPIO56_MCU_WPD_M (IO_MUX_GPIO56_MCU_WPD_V << IO_MUX_GPIO56_MCU_WPD_S) -#define IO_MUX_GPIO56_MCU_WPD_V 0x00000001U -#define IO_MUX_GPIO56_MCU_WPD_S 2 -/** IO_MUX_GPIO56_MCU_WPU : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_WPU (BIT(3)) -#define IO_MUX_GPIO56_MCU_WPU_M (IO_MUX_GPIO56_MCU_WPU_V << IO_MUX_GPIO56_MCU_WPU_S) -#define IO_MUX_GPIO56_MCU_WPU_V 0x00000001U -#define IO_MUX_GPIO56_MCU_WPU_S 3 -/** IO_MUX_GPIO56_MCU_IE : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ -#define IO_MUX_GPIO56_MCU_IE (BIT(4)) -#define IO_MUX_GPIO56_MCU_IE_M (IO_MUX_GPIO56_MCU_IE_V << IO_MUX_GPIO56_MCU_IE_S) -#define IO_MUX_GPIO56_MCU_IE_V 0x00000001U -#define IO_MUX_GPIO56_MCU_IE_S 4 -/** IO_MUX_GPIO56_MCU_DRV : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ -#define IO_MUX_GPIO56_MCU_DRV 0x00000003U -#define IO_MUX_GPIO56_MCU_DRV_M (IO_MUX_GPIO56_MCU_DRV_V << IO_MUX_GPIO56_MCU_DRV_S) -#define IO_MUX_GPIO56_MCU_DRV_V 0x00000003U -#define IO_MUX_GPIO56_MCU_DRV_S 5 -/** IO_MUX_GPIO56_FUN_WPD : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ -#define IO_MUX_GPIO56_FUN_WPD (BIT(7)) -#define IO_MUX_GPIO56_FUN_WPD_M (IO_MUX_GPIO56_FUN_WPD_V << IO_MUX_GPIO56_FUN_WPD_S) -#define IO_MUX_GPIO56_FUN_WPD_V 0x00000001U -#define IO_MUX_GPIO56_FUN_WPD_S 7 -/** IO_MUX_GPIO56_FUN_WPU : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ -#define IO_MUX_GPIO56_FUN_WPU (BIT(8)) -#define IO_MUX_GPIO56_FUN_WPU_M (IO_MUX_GPIO56_FUN_WPU_V << IO_MUX_GPIO56_FUN_WPU_S) -#define IO_MUX_GPIO56_FUN_WPU_V 0x00000001U -#define IO_MUX_GPIO56_FUN_WPU_S 8 -/** IO_MUX_GPIO56_FUN_IE : R/W; bitpos: [9]; default: 0; - * input enable - */ -#define IO_MUX_GPIO56_FUN_IE (BIT(9)) -#define IO_MUX_GPIO56_FUN_IE_M (IO_MUX_GPIO56_FUN_IE_V << IO_MUX_GPIO56_FUN_IE_S) -#define IO_MUX_GPIO56_FUN_IE_V 0x00000001U -#define IO_MUX_GPIO56_FUN_IE_S 9 -/** IO_MUX_GPIO56_FUN_DRV : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ -#define IO_MUX_GPIO56_FUN_DRV 0x00000003U -#define IO_MUX_GPIO56_FUN_DRV_M (IO_MUX_GPIO56_FUN_DRV_V << IO_MUX_GPIO56_FUN_DRV_S) -#define IO_MUX_GPIO56_FUN_DRV_V 0x00000003U -#define IO_MUX_GPIO56_FUN_DRV_S 10 -/** IO_MUX_GPIO56_MCU_SEL : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ -#define IO_MUX_GPIO56_MCU_SEL 0x00000007U -#define IO_MUX_GPIO56_MCU_SEL_M (IO_MUX_GPIO56_MCU_SEL_V << IO_MUX_GPIO56_MCU_SEL_S) -#define IO_MUX_GPIO56_MCU_SEL_V 0x00000007U -#define IO_MUX_GPIO56_MCU_SEL_S 12 -/** IO_MUX_GPIO56_FILTER_EN : R/W; bitpos: [15]; default: 0; - * input filter enable - */ -#define IO_MUX_GPIO56_FILTER_EN (BIT(15)) -#define IO_MUX_GPIO56_FILTER_EN_M (IO_MUX_GPIO56_FILTER_EN_V << IO_MUX_GPIO56_FILTER_EN_S) -#define IO_MUX_GPIO56_FILTER_EN_V 0x00000001U -#define IO_MUX_GPIO56_FILTER_EN_S 15 - -/** IO_MUX_DATE_REG register - * iomux version - */ -#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x104) -/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 2101794; - * csv date - */ -#define IO_MUX_DATE 0x0FFFFFFFU -#define IO_MUX_DATE_M (IO_MUX_DATE_V << IO_MUX_DATE_S) -#define IO_MUX_DATE_V 0x0FFFFFFFU -#define IO_MUX_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h deleted file mode 100644 index 0ebee78c34..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_eco5_struct.h +++ /dev/null @@ -1,3430 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: IOMUX Register */ -/** Type of gpio0 register - * iomux control register for gpio0 - */ -typedef union { - struct { - /** gpio0_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio0_mcu_oe:1; - /** gpio0_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio0_slp_sel:1; - /** gpio0_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio0_mcu_wpd:1; - /** gpio0_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio0_mcu_wpu:1; - /** gpio0_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio0_mcu_ie:1; - /** gpio0_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio0_mcu_drv:2; - /** gpio0_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio0_fun_wpd:1; - /** gpio0_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio0_fun_wpu:1; - /** gpio0_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio0_fun_ie:1; - /** gpio0_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio0_fun_drv:2; - /** gpio0_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio0_mcu_sel:3; - /** gpio0_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio0_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio0_reg_t; - -/** Type of gpio1 register - * iomux control register for gpio1 - */ -typedef union { - struct { - /** gpio1_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio1_mcu_oe:1; - /** gpio1_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio1_slp_sel:1; - /** gpio1_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio1_mcu_wpd:1; - /** gpio1_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio1_mcu_wpu:1; - /** gpio1_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio1_mcu_ie:1; - /** gpio1_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio1_mcu_drv:2; - /** gpio1_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio1_fun_wpd:1; - /** gpio1_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio1_fun_wpu:1; - /** gpio1_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio1_fun_ie:1; - /** gpio1_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio1_fun_drv:2; - /** gpio1_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio1_mcu_sel:3; - /** gpio1_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio1_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio1_reg_t; - -/** Type of gpio2 register - * iomux control register for gpio2 - */ -typedef union { - struct { - /** gpio2_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio2_mcu_oe:1; - /** gpio2_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio2_slp_sel:1; - /** gpio2_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio2_mcu_wpd:1; - /** gpio2_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio2_mcu_wpu:1; - /** gpio2_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio2_mcu_ie:1; - /** gpio2_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio2_mcu_drv:2; - /** gpio2_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio2_fun_wpd:1; - /** gpio2_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio2_fun_wpu:1; - /** gpio2_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio2_fun_ie:1; - /** gpio2_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio2_fun_drv:2; - /** gpio2_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio2_mcu_sel:3; - /** gpio2_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio2_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio2_reg_t; - -/** Type of gpio3 register - * iomux control register for gpio3 - */ -typedef union { - struct { - /** gpio3_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio3_mcu_oe:1; - /** gpio3_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio3_slp_sel:1; - /** gpio3_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio3_mcu_wpd:1; - /** gpio3_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio3_mcu_wpu:1; - /** gpio3_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio3_mcu_ie:1; - /** gpio3_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio3_mcu_drv:2; - /** gpio3_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio3_fun_wpd:1; - /** gpio3_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio3_fun_wpu:1; - /** gpio3_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio3_fun_ie:1; - /** gpio3_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio3_fun_drv:2; - /** gpio3_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio3_mcu_sel:3; - /** gpio3_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio3_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio3_reg_t; - -/** Type of gpio4 register - * iomux control register for gpio4 - */ -typedef union { - struct { - /** gpio4_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio4_mcu_oe:1; - /** gpio4_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio4_slp_sel:1; - /** gpio4_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio4_mcu_wpd:1; - /** gpio4_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio4_mcu_wpu:1; - /** gpio4_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio4_mcu_ie:1; - /** gpio4_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio4_mcu_drv:2; - /** gpio4_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio4_fun_wpd:1; - /** gpio4_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio4_fun_wpu:1; - /** gpio4_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio4_fun_ie:1; - /** gpio4_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio4_fun_drv:2; - /** gpio4_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio4_mcu_sel:3; - /** gpio4_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio4_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio4_reg_t; - -/** Type of gpio5 register - * iomux control register for gpio5 - */ -typedef union { - struct { - /** gpio5_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio5_mcu_oe:1; - /** gpio5_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio5_slp_sel:1; - /** gpio5_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio5_mcu_wpd:1; - /** gpio5_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio5_mcu_wpu:1; - /** gpio5_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio5_mcu_ie:1; - /** gpio5_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio5_mcu_drv:2; - /** gpio5_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio5_fun_wpd:1; - /** gpio5_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio5_fun_wpu:1; - /** gpio5_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio5_fun_ie:1; - /** gpio5_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio5_fun_drv:2; - /** gpio5_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio5_mcu_sel:3; - /** gpio5_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio5_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio5_reg_t; - -/** Type of gpio6 register - * iomux control register for gpio6 - */ -typedef union { - struct { - /** gpio6_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio6_mcu_oe:1; - /** gpio6_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio6_slp_sel:1; - /** gpio6_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio6_mcu_wpd:1; - /** gpio6_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio6_mcu_wpu:1; - /** gpio6_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio6_mcu_ie:1; - /** gpio6_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio6_mcu_drv:2; - /** gpio6_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio6_fun_wpd:1; - /** gpio6_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio6_fun_wpu:1; - /** gpio6_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio6_fun_ie:1; - /** gpio6_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio6_fun_drv:2; - /** gpio6_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio6_mcu_sel:3; - /** gpio6_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio6_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio6_reg_t; - -/** Type of gpio7 register - * iomux control register for gpio7 - */ -typedef union { - struct { - /** gpio7_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio7_mcu_oe:1; - /** gpio7_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio7_slp_sel:1; - /** gpio7_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio7_mcu_wpd:1; - /** gpio7_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio7_mcu_wpu:1; - /** gpio7_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio7_mcu_ie:1; - /** gpio7_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio7_mcu_drv:2; - /** gpio7_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio7_fun_wpd:1; - /** gpio7_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio7_fun_wpu:1; - /** gpio7_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio7_fun_ie:1; - /** gpio7_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio7_fun_drv:2; - /** gpio7_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio7_mcu_sel:3; - /** gpio7_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio7_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio7_reg_t; - -/** Type of gpio8 register - * iomux control register for gpio8 - */ -typedef union { - struct { - /** gpio8_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio8_mcu_oe:1; - /** gpio8_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio8_slp_sel:1; - /** gpio8_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio8_mcu_wpd:1; - /** gpio8_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio8_mcu_wpu:1; - /** gpio8_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio8_mcu_ie:1; - /** gpio8_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio8_mcu_drv:2; - /** gpio8_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio8_fun_wpd:1; - /** gpio8_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio8_fun_wpu:1; - /** gpio8_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio8_fun_ie:1; - /** gpio8_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio8_fun_drv:2; - /** gpio8_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio8_mcu_sel:3; - /** gpio8_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio8_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio8_reg_t; - -/** Type of gpio9 register - * iomux control register for gpio9 - */ -typedef union { - struct { - /** gpio9_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio9_mcu_oe:1; - /** gpio9_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio9_slp_sel:1; - /** gpio9_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio9_mcu_wpd:1; - /** gpio9_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio9_mcu_wpu:1; - /** gpio9_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio9_mcu_ie:1; - /** gpio9_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio9_mcu_drv:2; - /** gpio9_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio9_fun_wpd:1; - /** gpio9_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio9_fun_wpu:1; - /** gpio9_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio9_fun_ie:1; - /** gpio9_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio9_fun_drv:2; - /** gpio9_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio9_mcu_sel:3; - /** gpio9_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio9_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio9_reg_t; - -/** Type of gpio10 register - * iomux control register for gpio10 - */ -typedef union { - struct { - /** gpio10_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio10_mcu_oe:1; - /** gpio10_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio10_slp_sel:1; - /** gpio10_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio10_mcu_wpd:1; - /** gpio10_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio10_mcu_wpu:1; - /** gpio10_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio10_mcu_ie:1; - /** gpio10_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio10_mcu_drv:2; - /** gpio10_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio10_fun_wpd:1; - /** gpio10_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio10_fun_wpu:1; - /** gpio10_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio10_fun_ie:1; - /** gpio10_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio10_fun_drv:2; - /** gpio10_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio10_mcu_sel:3; - /** gpio10_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio10_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio10_reg_t; - -/** Type of gpio11 register - * iomux control register for gpio11 - */ -typedef union { - struct { - /** gpio11_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio11_mcu_oe:1; - /** gpio11_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio11_slp_sel:1; - /** gpio11_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio11_mcu_wpd:1; - /** gpio11_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio11_mcu_wpu:1; - /** gpio11_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio11_mcu_ie:1; - /** gpio11_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio11_mcu_drv:2; - /** gpio11_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio11_fun_wpd:1; - /** gpio11_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio11_fun_wpu:1; - /** gpio11_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio11_fun_ie:1; - /** gpio11_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio11_fun_drv:2; - /** gpio11_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio11_mcu_sel:3; - /** gpio11_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio11_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio11_reg_t; - -/** Type of gpio12 register - * iomux control register for gpio12 - */ -typedef union { - struct { - /** gpio12_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio12_mcu_oe:1; - /** gpio12_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio12_slp_sel:1; - /** gpio12_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio12_mcu_wpd:1; - /** gpio12_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio12_mcu_wpu:1; - /** gpio12_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio12_mcu_ie:1; - /** gpio12_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio12_mcu_drv:2; - /** gpio12_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio12_fun_wpd:1; - /** gpio12_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio12_fun_wpu:1; - /** gpio12_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio12_fun_ie:1; - /** gpio12_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio12_fun_drv:2; - /** gpio12_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio12_mcu_sel:3; - /** gpio12_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio12_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio12_reg_t; - -/** Type of gpio13 register - * iomux control register for gpio13 - */ -typedef union { - struct { - /** gpio13_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio13_mcu_oe:1; - /** gpio13_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio13_slp_sel:1; - /** gpio13_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio13_mcu_wpd:1; - /** gpio13_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio13_mcu_wpu:1; - /** gpio13_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio13_mcu_ie:1; - /** gpio13_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio13_mcu_drv:2; - /** gpio13_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio13_fun_wpd:1; - /** gpio13_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio13_fun_wpu:1; - /** gpio13_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio13_fun_ie:1; - /** gpio13_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio13_fun_drv:2; - /** gpio13_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio13_mcu_sel:3; - /** gpio13_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio13_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio13_reg_t; - -/** Type of gpio14 register - * iomux control register for gpio14 - */ -typedef union { - struct { - /** gpio14_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio14_mcu_oe:1; - /** gpio14_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio14_slp_sel:1; - /** gpio14_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio14_mcu_wpd:1; - /** gpio14_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio14_mcu_wpu:1; - /** gpio14_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio14_mcu_ie:1; - /** gpio14_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio14_mcu_drv:2; - /** gpio14_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio14_fun_wpd:1; - /** gpio14_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio14_fun_wpu:1; - /** gpio14_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio14_fun_ie:1; - /** gpio14_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio14_fun_drv:2; - /** gpio14_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio14_mcu_sel:3; - /** gpio14_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio14_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio14_reg_t; - -/** Type of gpio15 register - * iomux control register for gpio15 - */ -typedef union { - struct { - /** gpio15_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio15_mcu_oe:1; - /** gpio15_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio15_slp_sel:1; - /** gpio15_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio15_mcu_wpd:1; - /** gpio15_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio15_mcu_wpu:1; - /** gpio15_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio15_mcu_ie:1; - /** gpio15_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio15_mcu_drv:2; - /** gpio15_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio15_fun_wpd:1; - /** gpio15_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio15_fun_wpu:1; - /** gpio15_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio15_fun_ie:1; - /** gpio15_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio15_fun_drv:2; - /** gpio15_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio15_mcu_sel:3; - /** gpio15_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio15_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio15_reg_t; - -/** Type of gpio16 register - * iomux control register for gpio16 - */ -typedef union { - struct { - /** gpio16_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio16_mcu_oe:1; - /** gpio16_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio16_slp_sel:1; - /** gpio16_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio16_mcu_wpd:1; - /** gpio16_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio16_mcu_wpu:1; - /** gpio16_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio16_mcu_ie:1; - /** gpio16_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio16_mcu_drv:2; - /** gpio16_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio16_fun_wpd:1; - /** gpio16_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio16_fun_wpu:1; - /** gpio16_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio16_fun_ie:1; - /** gpio16_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio16_fun_drv:2; - /** gpio16_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio16_mcu_sel:3; - /** gpio16_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio16_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio16_reg_t; - -/** Type of gpio17 register - * iomux control register for gpio17 - */ -typedef union { - struct { - /** gpio17_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio17_mcu_oe:1; - /** gpio17_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio17_slp_sel:1; - /** gpio17_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio17_mcu_wpd:1; - /** gpio17_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio17_mcu_wpu:1; - /** gpio17_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio17_mcu_ie:1; - /** gpio17_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio17_mcu_drv:2; - /** gpio17_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio17_fun_wpd:1; - /** gpio17_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio17_fun_wpu:1; - /** gpio17_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio17_fun_ie:1; - /** gpio17_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio17_fun_drv:2; - /** gpio17_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio17_mcu_sel:3; - /** gpio17_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio17_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio17_reg_t; - -/** Type of gpio18 register - * iomux control register for gpio18 - */ -typedef union { - struct { - /** gpio18_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio18_mcu_oe:1; - /** gpio18_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio18_slp_sel:1; - /** gpio18_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio18_mcu_wpd:1; - /** gpio18_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio18_mcu_wpu:1; - /** gpio18_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio18_mcu_ie:1; - /** gpio18_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio18_mcu_drv:2; - /** gpio18_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio18_fun_wpd:1; - /** gpio18_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio18_fun_wpu:1; - /** gpio18_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio18_fun_ie:1; - /** gpio18_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio18_fun_drv:2; - /** gpio18_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio18_mcu_sel:3; - /** gpio18_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio18_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio18_reg_t; - -/** Type of gpio19 register - * iomux control register for gpio19 - */ -typedef union { - struct { - /** gpio19_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio19_mcu_oe:1; - /** gpio19_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio19_slp_sel:1; - /** gpio19_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio19_mcu_wpd:1; - /** gpio19_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio19_mcu_wpu:1; - /** gpio19_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio19_mcu_ie:1; - /** gpio19_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio19_mcu_drv:2; - /** gpio19_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio19_fun_wpd:1; - /** gpio19_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio19_fun_wpu:1; - /** gpio19_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio19_fun_ie:1; - /** gpio19_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio19_fun_drv:2; - /** gpio19_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio19_mcu_sel:3; - /** gpio19_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio19_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio19_reg_t; - -/** Type of gpio20 register - * iomux control register for gpio20 - */ -typedef union { - struct { - /** gpio20_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio20_mcu_oe:1; - /** gpio20_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio20_slp_sel:1; - /** gpio20_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio20_mcu_wpd:1; - /** gpio20_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio20_mcu_wpu:1; - /** gpio20_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio20_mcu_ie:1; - /** gpio20_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio20_mcu_drv:2; - /** gpio20_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio20_fun_wpd:1; - /** gpio20_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio20_fun_wpu:1; - /** gpio20_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio20_fun_ie:1; - /** gpio20_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio20_fun_drv:2; - /** gpio20_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio20_mcu_sel:3; - /** gpio20_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio20_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio20_reg_t; - -/** Type of gpio21 register - * iomux control register for gpio21 - */ -typedef union { - struct { - /** gpio21_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio21_mcu_oe:1; - /** gpio21_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio21_slp_sel:1; - /** gpio21_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio21_mcu_wpd:1; - /** gpio21_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio21_mcu_wpu:1; - /** gpio21_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio21_mcu_ie:1; - /** gpio21_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio21_mcu_drv:2; - /** gpio21_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio21_fun_wpd:1; - /** gpio21_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio21_fun_wpu:1; - /** gpio21_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio21_fun_ie:1; - /** gpio21_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio21_fun_drv:2; - /** gpio21_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio21_mcu_sel:3; - /** gpio21_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio21_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio21_reg_t; - -/** Type of gpio22 register - * iomux control register for gpio22 - */ -typedef union { - struct { - /** gpio22_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio22_mcu_oe:1; - /** gpio22_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio22_slp_sel:1; - /** gpio22_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio22_mcu_wpd:1; - /** gpio22_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio22_mcu_wpu:1; - /** gpio22_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio22_mcu_ie:1; - /** gpio22_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio22_mcu_drv:2; - /** gpio22_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio22_fun_wpd:1; - /** gpio22_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio22_fun_wpu:1; - /** gpio22_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio22_fun_ie:1; - /** gpio22_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio22_fun_drv:2; - /** gpio22_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio22_mcu_sel:3; - /** gpio22_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio22_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio22_reg_t; - -/** Type of gpio23 register - * iomux control register for gpio23 - */ -typedef union { - struct { - /** gpio23_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio23_mcu_oe:1; - /** gpio23_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio23_slp_sel:1; - /** gpio23_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio23_mcu_wpd:1; - /** gpio23_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio23_mcu_wpu:1; - /** gpio23_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio23_mcu_ie:1; - /** gpio23_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio23_mcu_drv:2; - /** gpio23_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio23_fun_wpd:1; - /** gpio23_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio23_fun_wpu:1; - /** gpio23_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio23_fun_ie:1; - /** gpio23_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio23_fun_drv:2; - /** gpio23_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio23_mcu_sel:3; - /** gpio23_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio23_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio23_reg_t; - -/** Type of gpio24 register - * iomux control register for gpio24 - */ -typedef union { - struct { - /** gpio24_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio24_mcu_oe:1; - /** gpio24_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio24_slp_sel:1; - /** gpio24_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio24_mcu_wpd:1; - /** gpio24_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio24_mcu_wpu:1; - /** gpio24_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio24_mcu_ie:1; - /** gpio24_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio24_mcu_drv:2; - /** gpio24_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio24_fun_wpd:1; - /** gpio24_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio24_fun_wpu:1; - /** gpio24_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio24_fun_ie:1; - /** gpio24_fun_drv : R/W; bitpos: [11:10]; default: 3; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio24_fun_drv:2; - /** gpio24_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio24_mcu_sel:3; - /** gpio24_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio24_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio24_reg_t; - -/** Type of gpio25 register - * iomux control register for gpio25 - */ -typedef union { - struct { - /** gpio25_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio25_mcu_oe:1; - /** gpio25_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio25_slp_sel:1; - /** gpio25_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio25_mcu_wpd:1; - /** gpio25_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio25_mcu_wpu:1; - /** gpio25_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio25_mcu_ie:1; - /** gpio25_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio25_mcu_drv:2; - /** gpio25_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio25_fun_wpd:1; - /** gpio25_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio25_fun_wpu:1; - /** gpio25_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio25_fun_ie:1; - /** gpio25_fun_drv : R/W; bitpos: [11:10]; default: 3; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio25_fun_drv:2; - /** gpio25_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio25_mcu_sel:3; - /** gpio25_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio25_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio25_reg_t; - -/** Type of gpio26 register - * iomux control register for gpio26 - */ -typedef union { - struct { - /** gpio26_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio26_mcu_oe:1; - /** gpio26_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio26_slp_sel:1; - /** gpio26_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio26_mcu_wpd:1; - /** gpio26_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio26_mcu_wpu:1; - /** gpio26_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio26_mcu_ie:1; - /** gpio26_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio26_mcu_drv:2; - /** gpio26_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio26_fun_wpd:1; - /** gpio26_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio26_fun_wpu:1; - /** gpio26_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio26_fun_ie:1; - /** gpio26_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio26_fun_drv:2; - /** gpio26_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio26_mcu_sel:3; - /** gpio26_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio26_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio26_reg_t; - -/** Type of gpio27 register - * iomux control register for gpio27 - */ -typedef union { - struct { - /** gpio27_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio27_mcu_oe:1; - /** gpio27_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio27_slp_sel:1; - /** gpio27_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio27_mcu_wpd:1; - /** gpio27_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio27_mcu_wpu:1; - /** gpio27_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio27_mcu_ie:1; - /** gpio27_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio27_mcu_drv:2; - /** gpio27_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio27_fun_wpd:1; - /** gpio27_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio27_fun_wpu:1; - /** gpio27_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio27_fun_ie:1; - /** gpio27_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio27_fun_drv:2; - /** gpio27_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio27_mcu_sel:3; - /** gpio27_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio27_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio27_reg_t; - -/** Type of gpio28 register - * iomux control register for gpio28 - */ -typedef union { - struct { - /** gpio28_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio28_mcu_oe:1; - /** gpio28_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio28_slp_sel:1; - /** gpio28_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio28_mcu_wpd:1; - /** gpio28_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio28_mcu_wpu:1; - /** gpio28_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio28_mcu_ie:1; - /** gpio28_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio28_mcu_drv:2; - /** gpio28_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio28_fun_wpd:1; - /** gpio28_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio28_fun_wpu:1; - /** gpio28_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio28_fun_ie:1; - /** gpio28_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio28_fun_drv:2; - /** gpio28_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio28_mcu_sel:3; - /** gpio28_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio28_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio28_reg_t; - -/** Type of gpio29 register - * iomux control register for gpio29 - */ -typedef union { - struct { - /** gpio29_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio29_mcu_oe:1; - /** gpio29_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio29_slp_sel:1; - /** gpio29_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio29_mcu_wpd:1; - /** gpio29_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio29_mcu_wpu:1; - /** gpio29_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio29_mcu_ie:1; - /** gpio29_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio29_mcu_drv:2; - /** gpio29_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio29_fun_wpd:1; - /** gpio29_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio29_fun_wpu:1; - /** gpio29_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio29_fun_ie:1; - /** gpio29_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio29_fun_drv:2; - /** gpio29_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio29_mcu_sel:3; - /** gpio29_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio29_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio29_reg_t; - -/** Type of gpio30 register - * iomux control register for gpio30 - */ -typedef union { - struct { - /** gpio30_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio30_mcu_oe:1; - /** gpio30_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio30_slp_sel:1; - /** gpio30_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio30_mcu_wpd:1; - /** gpio30_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio30_mcu_wpu:1; - /** gpio30_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio30_mcu_ie:1; - /** gpio30_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio30_mcu_drv:2; - /** gpio30_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio30_fun_wpd:1; - /** gpio30_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio30_fun_wpu:1; - /** gpio30_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio30_fun_ie:1; - /** gpio30_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio30_fun_drv:2; - /** gpio30_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio30_mcu_sel:3; - /** gpio30_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio30_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio30_reg_t; - -/** Type of gpio31 register - * iomux control register for gpio31 - */ -typedef union { - struct { - /** gpio31_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio31_mcu_oe:1; - /** gpio31_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio31_slp_sel:1; - /** gpio31_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio31_mcu_wpd:1; - /** gpio31_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio31_mcu_wpu:1; - /** gpio31_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio31_mcu_ie:1; - /** gpio31_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio31_mcu_drv:2; - /** gpio31_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio31_fun_wpd:1; - /** gpio31_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio31_fun_wpu:1; - /** gpio31_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio31_fun_ie:1; - /** gpio31_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio31_fun_drv:2; - /** gpio31_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio31_mcu_sel:3; - /** gpio31_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio31_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio31_reg_t; - -/** Type of gpio32 register - * iomux control register for gpio32 - */ -typedef union { - struct { - /** gpio32_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio32_mcu_oe:1; - /** gpio32_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio32_slp_sel:1; - /** gpio32_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio32_mcu_wpd:1; - /** gpio32_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio32_mcu_wpu:1; - /** gpio32_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio32_mcu_ie:1; - /** gpio32_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio32_mcu_drv:2; - /** gpio32_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio32_fun_wpd:1; - /** gpio32_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio32_fun_wpu:1; - /** gpio32_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio32_fun_ie:1; - /** gpio32_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio32_fun_drv:2; - /** gpio32_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio32_mcu_sel:3; - /** gpio32_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio32_filter_en:1; - /** gpio32_rue_i3c : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t gpio32_rue_i3c:1; - /** gpio32_ru_i3c : R/W; bitpos: [18:17]; default: 0; - * NA - */ - uint32_t gpio32_ru_i3c:2; - /** gpio32_rue_sel_i3c : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t gpio32_rue_sel_i3c:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} io_mux_gpio32_reg_t; - -/** Type of gpio33 register - * iomux control register for gpio33 - */ -typedef union { - struct { - /** gpio33_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio33_mcu_oe:1; - /** gpio33_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio33_slp_sel:1; - /** gpio33_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio33_mcu_wpd:1; - /** gpio33_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio33_mcu_wpu:1; - /** gpio33_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio33_mcu_ie:1; - /** gpio33_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio33_mcu_drv:2; - /** gpio33_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio33_fun_wpd:1; - /** gpio33_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio33_fun_wpu:1; - /** gpio33_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio33_fun_ie:1; - /** gpio33_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio33_fun_drv:2; - /** gpio33_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio33_mcu_sel:3; - /** gpio33_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio33_filter_en:1; - /** gpio33_rue_i3c : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t gpio33_rue_i3c:1; - /** gpio33_ru_i3c : R/W; bitpos: [18:17]; default: 0; - * NA - */ - uint32_t gpio33_ru_i3c:2; - /** gpio33_rue_sel_i3c : R/W; bitpos: [19]; default: 0; - * NA - */ - uint32_t gpio33_rue_sel_i3c:1; - uint32_t reserved_20:12; - }; - uint32_t val; -} io_mux_gpio33_reg_t; - -/** Type of gpio34 register - * iomux control register for gpio34 - */ -typedef union { - struct { - /** gpio34_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio34_mcu_oe:1; - /** gpio34_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio34_slp_sel:1; - /** gpio34_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio34_mcu_wpd:1; - /** gpio34_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio34_mcu_wpu:1; - /** gpio34_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio34_mcu_ie:1; - /** gpio34_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio34_mcu_drv:2; - /** gpio34_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio34_fun_wpd:1; - /** gpio34_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio34_fun_wpu:1; - /** gpio34_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio34_fun_ie:1; - /** gpio34_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio34_fun_drv:2; - /** gpio34_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio34_mcu_sel:3; - /** gpio34_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio34_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio34_reg_t; - -/** Type of gpio35 register - * iomux control register for gpio35 - */ -typedef union { - struct { - /** gpio35_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio35_mcu_oe:1; - /** gpio35_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio35_slp_sel:1; - /** gpio35_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio35_mcu_wpd:1; - /** gpio35_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio35_mcu_wpu:1; - /** gpio35_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio35_mcu_ie:1; - /** gpio35_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio35_mcu_drv:2; - /** gpio35_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio35_fun_wpd:1; - /** gpio35_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio35_fun_wpu:1; - /** gpio35_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio35_fun_ie:1; - /** gpio35_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio35_fun_drv:2; - /** gpio35_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio35_mcu_sel:3; - /** gpio35_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio35_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio35_reg_t; - -/** Type of gpio36 register - * iomux control register for gpio36 - */ -typedef union { - struct { - /** gpio36_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio36_mcu_oe:1; - /** gpio36_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio36_slp_sel:1; - /** gpio36_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio36_mcu_wpd:1; - /** gpio36_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio36_mcu_wpu:1; - /** gpio36_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio36_mcu_ie:1; - /** gpio36_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio36_mcu_drv:2; - /** gpio36_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio36_fun_wpd:1; - /** gpio36_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio36_fun_wpu:1; - /** gpio36_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio36_fun_ie:1; - /** gpio36_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio36_fun_drv:2; - /** gpio36_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio36_mcu_sel:3; - /** gpio36_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio36_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio36_reg_t; - -/** Type of gpio37 register - * iomux control register for gpio37 - */ -typedef union { - struct { - /** gpio37_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio37_mcu_oe:1; - /** gpio37_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio37_slp_sel:1; - /** gpio37_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio37_mcu_wpd:1; - /** gpio37_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio37_mcu_wpu:1; - /** gpio37_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio37_mcu_ie:1; - /** gpio37_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio37_mcu_drv:2; - /** gpio37_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio37_fun_wpd:1; - /** gpio37_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio37_fun_wpu:1; - /** gpio37_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio37_fun_ie:1; - /** gpio37_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio37_fun_drv:2; - /** gpio37_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio37_mcu_sel:3; - /** gpio37_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio37_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio37_reg_t; - -/** Type of gpio38 register - * iomux control register for gpio38 - */ -typedef union { - struct { - /** gpio38_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio38_mcu_oe:1; - /** gpio38_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio38_slp_sel:1; - /** gpio38_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio38_mcu_wpd:1; - /** gpio38_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio38_mcu_wpu:1; - /** gpio38_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio38_mcu_ie:1; - /** gpio38_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio38_mcu_drv:2; - /** gpio38_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio38_fun_wpd:1; - /** gpio38_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio38_fun_wpu:1; - /** gpio38_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio38_fun_ie:1; - /** gpio38_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio38_fun_drv:2; - /** gpio38_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio38_mcu_sel:3; - /** gpio38_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio38_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio38_reg_t; - -/** Type of gpio39 register - * iomux control register for gpio39 - */ -typedef union { - struct { - /** gpio39_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio39_mcu_oe:1; - /** gpio39_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio39_slp_sel:1; - /** gpio39_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio39_mcu_wpd:1; - /** gpio39_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio39_mcu_wpu:1; - /** gpio39_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio39_mcu_ie:1; - /** gpio39_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio39_mcu_drv:2; - /** gpio39_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio39_fun_wpd:1; - /** gpio39_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio39_fun_wpu:1; - /** gpio39_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio39_fun_ie:1; - /** gpio39_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio39_fun_drv:2; - /** gpio39_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio39_mcu_sel:3; - /** gpio39_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio39_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio39_reg_t; - -/** Type of gpio40 register - * iomux control register for gpio40 - */ -typedef union { - struct { - /** gpio40_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio40_mcu_oe:1; - /** gpio40_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio40_slp_sel:1; - /** gpio40_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio40_mcu_wpd:1; - /** gpio40_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio40_mcu_wpu:1; - /** gpio40_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio40_mcu_ie:1; - /** gpio40_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio40_mcu_drv:2; - /** gpio40_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio40_fun_wpd:1; - /** gpio40_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio40_fun_wpu:1; - /** gpio40_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio40_fun_ie:1; - /** gpio40_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio40_fun_drv:2; - /** gpio40_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio40_mcu_sel:3; - /** gpio40_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio40_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio40_reg_t; - -/** Type of gpio41 register - * iomux control register for gpio41 - */ -typedef union { - struct { - /** gpio41_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio41_mcu_oe:1; - /** gpio41_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio41_slp_sel:1; - /** gpio41_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio41_mcu_wpd:1; - /** gpio41_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio41_mcu_wpu:1; - /** gpio41_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio41_mcu_ie:1; - /** gpio41_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio41_mcu_drv:2; - /** gpio41_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio41_fun_wpd:1; - /** gpio41_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio41_fun_wpu:1; - /** gpio41_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio41_fun_ie:1; - /** gpio41_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio41_fun_drv:2; - /** gpio41_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio41_mcu_sel:3; - /** gpio41_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio41_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio41_reg_t; - -/** Type of gpio42 register - * iomux control register for gpio42 - */ -typedef union { - struct { - /** gpio42_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio42_mcu_oe:1; - /** gpio42_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio42_slp_sel:1; - /** gpio42_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio42_mcu_wpd:1; - /** gpio42_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio42_mcu_wpu:1; - /** gpio42_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio42_mcu_ie:1; - /** gpio42_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio42_mcu_drv:2; - /** gpio42_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio42_fun_wpd:1; - /** gpio42_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio42_fun_wpu:1; - /** gpio42_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio42_fun_ie:1; - /** gpio42_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio42_fun_drv:2; - /** gpio42_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio42_mcu_sel:3; - /** gpio42_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio42_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio42_reg_t; - -/** Type of gpio43 register - * iomux control register for gpio43 - */ -typedef union { - struct { - /** gpio43_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio43_mcu_oe:1; - /** gpio43_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio43_slp_sel:1; - /** gpio43_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio43_mcu_wpd:1; - /** gpio43_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio43_mcu_wpu:1; - /** gpio43_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio43_mcu_ie:1; - /** gpio43_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio43_mcu_drv:2; - /** gpio43_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio43_fun_wpd:1; - /** gpio43_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio43_fun_wpu:1; - /** gpio43_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio43_fun_ie:1; - /** gpio43_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio43_fun_drv:2; - /** gpio43_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio43_mcu_sel:3; - /** gpio43_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio43_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio43_reg_t; - -/** Type of gpio44 register - * iomux control register for gpio44 - */ -typedef union { - struct { - /** gpio44_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio44_mcu_oe:1; - /** gpio44_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio44_slp_sel:1; - /** gpio44_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio44_mcu_wpd:1; - /** gpio44_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio44_mcu_wpu:1; - /** gpio44_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio44_mcu_ie:1; - /** gpio44_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio44_mcu_drv:2; - /** gpio44_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio44_fun_wpd:1; - /** gpio44_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio44_fun_wpu:1; - /** gpio44_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio44_fun_ie:1; - /** gpio44_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio44_fun_drv:2; - /** gpio44_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio44_mcu_sel:3; - /** gpio44_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio44_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio44_reg_t; - -/** Type of gpio45 register - * iomux control register for gpio45 - */ -typedef union { - struct { - /** gpio45_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio45_mcu_oe:1; - /** gpio45_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio45_slp_sel:1; - /** gpio45_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio45_mcu_wpd:1; - /** gpio45_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio45_mcu_wpu:1; - /** gpio45_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio45_mcu_ie:1; - /** gpio45_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio45_mcu_drv:2; - /** gpio45_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio45_fun_wpd:1; - /** gpio45_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio45_fun_wpu:1; - /** gpio45_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio45_fun_ie:1; - /** gpio45_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio45_fun_drv:2; - /** gpio45_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio45_mcu_sel:3; - /** gpio45_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio45_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio45_reg_t; - -/** Type of gpio46 register - * iomux control register for gpio46 - */ -typedef union { - struct { - /** gpio46_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio46_mcu_oe:1; - /** gpio46_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio46_slp_sel:1; - /** gpio46_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio46_mcu_wpd:1; - /** gpio46_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio46_mcu_wpu:1; - /** gpio46_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio46_mcu_ie:1; - /** gpio46_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio46_mcu_drv:2; - /** gpio46_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio46_fun_wpd:1; - /** gpio46_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio46_fun_wpu:1; - /** gpio46_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio46_fun_ie:1; - /** gpio46_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio46_fun_drv:2; - /** gpio46_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio46_mcu_sel:3; - /** gpio46_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio46_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio46_reg_t; - -/** Type of gpio47 register - * iomux control register for gpio47 - */ -typedef union { - struct { - /** gpio47_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio47_mcu_oe:1; - /** gpio47_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio47_slp_sel:1; - /** gpio47_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio47_mcu_wpd:1; - /** gpio47_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio47_mcu_wpu:1; - /** gpio47_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio47_mcu_ie:1; - /** gpio47_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio47_mcu_drv:2; - /** gpio47_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio47_fun_wpd:1; - /** gpio47_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio47_fun_wpu:1; - /** gpio47_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio47_fun_ie:1; - /** gpio47_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio47_fun_drv:2; - /** gpio47_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio47_mcu_sel:3; - /** gpio47_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio47_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio47_reg_t; - -/** Type of gpio48 register - * iomux control register for gpio48 - */ -typedef union { - struct { - /** gpio48_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio48_mcu_oe:1; - /** gpio48_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio48_slp_sel:1; - /** gpio48_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio48_mcu_wpd:1; - /** gpio48_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio48_mcu_wpu:1; - /** gpio48_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio48_mcu_ie:1; - /** gpio48_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio48_mcu_drv:2; - /** gpio48_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio48_fun_wpd:1; - /** gpio48_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio48_fun_wpu:1; - /** gpio48_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio48_fun_ie:1; - /** gpio48_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio48_fun_drv:2; - /** gpio48_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio48_mcu_sel:3; - /** gpio48_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio48_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio48_reg_t; - -/** Type of gpio49 register - * iomux control register for gpio49 - */ -typedef union { - struct { - /** gpio49_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio49_mcu_oe:1; - /** gpio49_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio49_slp_sel:1; - /** gpio49_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio49_mcu_wpd:1; - /** gpio49_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio49_mcu_wpu:1; - /** gpio49_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio49_mcu_ie:1; - /** gpio49_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio49_mcu_drv:2; - /** gpio49_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio49_fun_wpd:1; - /** gpio49_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio49_fun_wpu:1; - /** gpio49_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio49_fun_ie:1; - /** gpio49_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio49_fun_drv:2; - /** gpio49_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio49_mcu_sel:3; - /** gpio49_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio49_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio49_reg_t; - -/** Type of gpio50 register - * iomux control register for gpio50 - */ -typedef union { - struct { - /** gpio50_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio50_mcu_oe:1; - /** gpio50_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio50_slp_sel:1; - /** gpio50_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio50_mcu_wpd:1; - /** gpio50_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio50_mcu_wpu:1; - /** gpio50_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio50_mcu_ie:1; - /** gpio50_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio50_mcu_drv:2; - /** gpio50_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio50_fun_wpd:1; - /** gpio50_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio50_fun_wpu:1; - /** gpio50_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio50_fun_ie:1; - /** gpio50_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio50_fun_drv:2; - /** gpio50_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio50_mcu_sel:3; - /** gpio50_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio50_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio50_reg_t; - -/** Type of gpio51 register - * iomux control register for gpio51 - */ -typedef union { - struct { - /** gpio51_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio51_mcu_oe:1; - /** gpio51_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio51_slp_sel:1; - /** gpio51_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio51_mcu_wpd:1; - /** gpio51_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio51_mcu_wpu:1; - /** gpio51_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio51_mcu_ie:1; - /** gpio51_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio51_mcu_drv:2; - /** gpio51_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio51_fun_wpd:1; - /** gpio51_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio51_fun_wpu:1; - /** gpio51_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio51_fun_ie:1; - /** gpio51_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio51_fun_drv:2; - /** gpio51_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio51_mcu_sel:3; - /** gpio51_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio51_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio51_reg_t; - -/** Type of gpio52 register - * iomux control register for gpio52 - */ -typedef union { - struct { - /** gpio52_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio52_mcu_oe:1; - /** gpio52_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio52_slp_sel:1; - /** gpio52_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio52_mcu_wpd:1; - /** gpio52_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio52_mcu_wpu:1; - /** gpio52_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio52_mcu_ie:1; - /** gpio52_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio52_mcu_drv:2; - /** gpio52_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio52_fun_wpd:1; - /** gpio52_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio52_fun_wpu:1; - /** gpio52_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio52_fun_ie:1; - /** gpio52_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio52_fun_drv:2; - /** gpio52_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio52_mcu_sel:3; - /** gpio52_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio52_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio52_reg_t; - -/** Type of gpio53 register - * iomux control register for gpio53 - */ -typedef union { - struct { - /** gpio53_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio53_mcu_oe:1; - /** gpio53_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio53_slp_sel:1; - /** gpio53_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio53_mcu_wpd:1; - /** gpio53_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio53_mcu_wpu:1; - /** gpio53_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio53_mcu_ie:1; - /** gpio53_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio53_mcu_drv:2; - /** gpio53_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio53_fun_wpd:1; - /** gpio53_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio53_fun_wpu:1; - /** gpio53_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio53_fun_ie:1; - /** gpio53_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio53_fun_drv:2; - /** gpio53_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio53_mcu_sel:3; - /** gpio53_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio53_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio53_reg_t; - -/** Type of gpio54 register - * iomux control register for gpio54 - */ -typedef union { - struct { - /** gpio54_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio54_mcu_oe:1; - /** gpio54_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio54_slp_sel:1; - /** gpio54_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio54_mcu_wpd:1; - /** gpio54_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio54_mcu_wpu:1; - /** gpio54_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio54_mcu_ie:1; - /** gpio54_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio54_mcu_drv:2; - /** gpio54_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio54_fun_wpd:1; - /** gpio54_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio54_fun_wpu:1; - /** gpio54_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio54_fun_ie:1; - /** gpio54_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio54_fun_drv:2; - /** gpio54_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio54_mcu_sel:3; - /** gpio54_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio54_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio54_reg_t; - -/** Type of gpio55 register - * iomux control register for gpio55 - */ -typedef union { - struct { - /** gpio55_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio55_mcu_oe:1; - /** gpio55_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio55_slp_sel:1; - /** gpio55_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio55_mcu_wpd:1; - /** gpio55_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio55_mcu_wpu:1; - /** gpio55_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio55_mcu_ie:1; - /** gpio55_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio55_mcu_drv:2; - /** gpio55_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio55_fun_wpd:1; - /** gpio55_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio55_fun_wpu:1; - /** gpio55_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio55_fun_ie:1; - /** gpio55_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio55_fun_drv:2; - /** gpio55_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio55_mcu_sel:3; - /** gpio55_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio55_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio55_reg_t; - -/** Type of gpio56 register - * iomux control register for gpio56 - */ -typedef union { - struct { - /** gpio56_mcu_oe : R/W; bitpos: [0]; default: 0; - * output enable on sleep mode - */ - uint32_t gpio56_mcu_oe:1; - /** gpio56_slp_sel : R/W; bitpos: [1]; default: 0; - * io sleep mode enable. set 1 to enable sleep mode. - */ - uint32_t gpio56_slp_sel:1; - /** gpio56_mcu_wpd : R/W; bitpos: [2]; default: 0; - * pull-down enable on sleep mode - */ - uint32_t gpio56_mcu_wpd:1; - /** gpio56_mcu_wpu : R/W; bitpos: [3]; default: 0; - * pull-up enable on sleep mode - */ - uint32_t gpio56_mcu_wpu:1; - /** gpio56_mcu_ie : R/W; bitpos: [4]; default: 0; - * input enable on sleep mode - */ - uint32_t gpio56_mcu_ie:1; - /** gpio56_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * select drive strength on sleep mode - */ - uint32_t gpio56_mcu_drv:2; - /** gpio56_fun_wpd : R/W; bitpos: [7]; default: 0; - * pull-down enable - */ - uint32_t gpio56_fun_wpd:1; - /** gpio56_fun_wpu : R/W; bitpos: [8]; default: 0; - * pull-up enable - */ - uint32_t gpio56_fun_wpu:1; - /** gpio56_fun_ie : R/W; bitpos: [9]; default: 0; - * input enable - */ - uint32_t gpio56_fun_ie:1; - /** gpio56_fun_drv : R/W; bitpos: [11:10]; default: 2; - * select drive strength, 0:5mA, 1:10mA, 2:20mA, 3:40mA - */ - uint32_t gpio56_fun_drv:2; - /** gpio56_mcu_sel : R/W; bitpos: [14:12]; default: 0; - * 0:select function0, 1:select function1 ... - */ - uint32_t gpio56_mcu_sel:3; - /** gpio56_filter_en : R/W; bitpos: [15]; default: 0; - * input filter enable - */ - uint32_t gpio56_filter_en:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} io_mux_gpio56_reg_t; - -/** Type of date register - * iomux version - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 2101794; - * csv date - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} io_mux_date_reg_t; - - -typedef struct { - uint32_t reserved_000; - volatile io_mux_gpio0_reg_t gpio0; - volatile io_mux_gpio1_reg_t gpio1; - volatile io_mux_gpio2_reg_t gpio2; - volatile io_mux_gpio3_reg_t gpio3; - volatile io_mux_gpio4_reg_t gpio4; - volatile io_mux_gpio5_reg_t gpio5; - volatile io_mux_gpio6_reg_t gpio6; - volatile io_mux_gpio7_reg_t gpio7; - volatile io_mux_gpio8_reg_t gpio8; - volatile io_mux_gpio9_reg_t gpio9; - volatile io_mux_gpio10_reg_t gpio10; - volatile io_mux_gpio11_reg_t gpio11; - volatile io_mux_gpio12_reg_t gpio12; - volatile io_mux_gpio13_reg_t gpio13; - volatile io_mux_gpio14_reg_t gpio14; - volatile io_mux_gpio15_reg_t gpio15; - volatile io_mux_gpio16_reg_t gpio16; - volatile io_mux_gpio17_reg_t gpio17; - volatile io_mux_gpio18_reg_t gpio18; - volatile io_mux_gpio19_reg_t gpio19; - volatile io_mux_gpio20_reg_t gpio20; - volatile io_mux_gpio21_reg_t gpio21; - volatile io_mux_gpio22_reg_t gpio22; - volatile io_mux_gpio23_reg_t gpio23; - volatile io_mux_gpio24_reg_t gpio24; - volatile io_mux_gpio25_reg_t gpio25; - volatile io_mux_gpio26_reg_t gpio26; - volatile io_mux_gpio27_reg_t gpio27; - volatile io_mux_gpio28_reg_t gpio28; - volatile io_mux_gpio29_reg_t gpio29; - volatile io_mux_gpio30_reg_t gpio30; - volatile io_mux_gpio31_reg_t gpio31; - volatile io_mux_gpio32_reg_t gpio32; - volatile io_mux_gpio33_reg_t gpio33; - volatile io_mux_gpio34_reg_t gpio34; - volatile io_mux_gpio35_reg_t gpio35; - volatile io_mux_gpio36_reg_t gpio36; - volatile io_mux_gpio37_reg_t gpio37; - volatile io_mux_gpio38_reg_t gpio38; - volatile io_mux_gpio39_reg_t gpio39; - volatile io_mux_gpio40_reg_t gpio40; - volatile io_mux_gpio41_reg_t gpio41; - volatile io_mux_gpio42_reg_t gpio42; - volatile io_mux_gpio43_reg_t gpio43; - volatile io_mux_gpio44_reg_t gpio44; - volatile io_mux_gpio45_reg_t gpio45; - volatile io_mux_gpio46_reg_t gpio46; - volatile io_mux_gpio47_reg_t gpio47; - volatile io_mux_gpio48_reg_t gpio48; - volatile io_mux_gpio49_reg_t gpio49; - volatile io_mux_gpio50_reg_t gpio50; - volatile io_mux_gpio51_reg_t gpio51; - volatile io_mux_gpio52_reg_t gpio52; - volatile io_mux_gpio53_reg_t gpio53; - volatile io_mux_gpio54_reg_t gpio54; - volatile io_mux_gpio55_reg_t gpio55; - volatile io_mux_gpio56_reg_t gpio56; - uint32_t reserved_0e8[7]; - volatile io_mux_date_reg_t date; -} io_mux_dev_t; - -extern io_mux_dev_t IO_MUX; - -#ifndef __cplusplus -_Static_assert(sizeof(io_mux_dev_t) == 0x108, "Invalid size of io_mux_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h index b8eac91be1..4671c68ae9 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h @@ -7,8 +7,6 @@ #pragma once #include "soc/soc.h" -//TODO: IDF-13419 - /* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ /* Output enable in sleep mode */ #define SLP_OE (BIT(0)) @@ -155,23 +153,6 @@ #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -// TODO: IDF-7499, IDF-7495 -// SPI pins defined here are all wrong. On P4, these pins are individual pins, don't use normal GPIO pins anymore. -// Please check iomux_mspi_pin_struct/reg.h -#include "soc/gpio_num.h" -#define SPI_CS1_GPIO_NUM GPIO_NUM_MAX -#define SPI_HD_GPIO_NUM GPIO_NUM_MAX -#define SPI_WP_GPIO_NUM GPIO_NUM_MAX -#define SPI_CS0_GPIO_NUM GPIO_NUM_MAX -#define SPI_CLK_GPIO_NUM GPIO_NUM_MAX -#define SPI_Q_GPIO_NUM GPIO_NUM_MAX -#define SPI_D_GPIO_NUM GPIO_NUM_MAX -#define SPI_D4_GPIO_NUM GPIO_NUM_MAX -#define SPI_D5_GPIO_NUM GPIO_NUM_MAX -#define SPI_D6_GPIO_NUM GPIO_NUM_MAX -#define SPI_D7_GPIO_NUM GPIO_NUM_MAX -#define SPI_DQS_GPIO_NUM GPIO_NUM_MAX - #define SD_CLK_GPIO_NUM 43 #define SD_CMD_GPIO_NUM 44 #define SD_DATA0_GPIO_NUM 39 @@ -357,6 +338,7 @@ #define FUNC_GPIO31_GPIO31 1 #define FUNC_GPIO31_GPIO31_0 0 +// Strapping: Diag Group Sel1 #define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x84) #define FUNC_GPIO32_DBG_PSRAM_DQ4_PAD 4 #define FUNC_GPIO32_EMAC_RMII_CLK_PAD 3 @@ -364,6 +346,7 @@ #define FUNC_GPIO32_GPIO32 1 #define FUNC_GPIO32_GPIO32_0 0 +// Strapping: Diag Group Sel0 #define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x88) #define FUNC_GPIO33_DBG_PSRAM_DQ5_PAD 4 #define FUNC_GPIO33_EMAC_PHY_TXEN_PAD 3 @@ -371,6 +354,7 @@ #define FUNC_GPIO33_GPIO33 1 #define FUNC_GPIO33_GPIO33_0 0 +// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag #define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x8C) #define FUNC_GPIO34_DBG_PSRAM_DQ6_PAD 4 #define FUNC_GPIO34_EMAC_PHY_TXD0_PAD 3 @@ -378,6 +362,7 @@ #define FUNC_GPIO34_GPIO34 1 #define FUNC_GPIO34_GPIO34_0 0 +// Strapping: Boot Mode select 3 #define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x90) #define FUNC_GPIO35_DBG_PSRAM_DQ7_PAD 4 #define FUNC_GPIO35_EMAC_PHY_TXD1_PAD 3 @@ -385,6 +370,7 @@ #define FUNC_GPIO35_GPIO35 1 #define FUNC_GPIO35_GPIO35_0 0 +// Strapping: Boot Mode select 2 #define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x94) #define FUNC_GPIO36_DBG_PSRAM_DQS_0_PAD 4 #define FUNC_GPIO36_EMAC_PHY_TXER_PAD 3 @@ -392,11 +378,13 @@ #define FUNC_GPIO36_GPIO36 1 #define FUNC_GPIO36_GPIO36_0 0 +// Strapping: Boot Mode select 1 #define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x98) #define FUNC_GPIO37_SPI2_IO7_PAD 2 #define FUNC_GPIO37_GPIO37 1 #define FUNC_GPIO37_UART0_TXD_PAD 0 +// Strapping: Boot Mode select 0 #define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x9C) #define FUNC_GPIO38_SPI2_DQS_PAD 2 #define FUNC_GPIO38_GPIO38 1 diff --git a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h index b2b0e66306..e187ba7459 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/io_mux_struct.h @@ -10,7 +10,6 @@ extern "C" { #endif -//TODO: IDF-13419 /** Type of GPIO register * IO MUX gpio configuration register */ diff --git a/components/soc/esp32s2/register/soc/io_mux_reg.h b/components/soc/esp32s2/register/soc/io_mux_reg.h index 86f19ce8eb..949be5e5d7 100644 --- a/components/soc/esp32s2/register/soc/io_mux_reg.h +++ b/components/soc/esp32s2/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -143,19 +143,6 @@ #define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -#define SPI_CS1_GPIO_NUM 26 -#define SPI_HD_GPIO_NUM 27 -#define SPI_WP_GPIO_NUM 28 -#define SPI_CS0_GPIO_NUM 29 -#define SPI_CLK_GPIO_NUM 30 -#define SPI_Q_GPIO_NUM 31 -#define SPI_D_GPIO_NUM 32 -#define SPI_D4_GPIO_NUM 33 -#define SPI_D5_GPIO_NUM 34 -#define SPI_D6_GPIO_NUM 35 -#define SPI_D7_GPIO_NUM 36 -#define SPI_DQS_GPIO_NUM 37 - #define MAX_RTC_GPIO_NUM 21 #define MAX_PAD_GPIO_NUM 46 #define MAX_GPIO_NUM 53 diff --git a/components/soc/esp32s3/register/soc/io_mux_reg.h b/components/soc/esp32s3/register/soc/io_mux_reg.h index fa72d36306..e44cfc80e3 100644 --- a/components/soc/esp32s3/register/soc/io_mux_reg.h +++ b/components/soc/esp32s3/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -143,18 +143,6 @@ #define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) #define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) -#define SPI_CS1_GPIO_NUM 26 -#define SPI_HD_GPIO_NUM 27 -#define SPI_WP_GPIO_NUM 28 -#define SPI_CS0_GPIO_NUM 29 -#define SPI_CLK_GPIO_NUM 30 -#define SPI_Q_GPIO_NUM 31 -#define SPI_D_GPIO_NUM 32 -#define SPI_D4_GPIO_NUM 33 -#define SPI_D5_GPIO_NUM 34 -#define SPI_D6_GPIO_NUM 35 -#define SPI_D7_GPIO_NUM 36 -#define SPI_DQS_GPIO_NUM 37 #define SD_CLK_GPIO_NUM 12 #define SD_CMD_GPIO_NUM 11 #define SD_DATA0_GPIO_NUM 13 From dde8fac6b8b76165a720afb65ccce10f07cd6283 Mon Sep 17 00:00:00 2001 From: Chen Jichang Date: Fri, 26 Sep 2025 16:58:27 +0800 Subject: [PATCH 2/2] feat(parlio_tx): support cs signal on esp32p4 eco5 --- .../test_apps/parlio/main/test_board.h | 10 +- .../test_apps/parlio/main/test_parlio_tx.c | 39 +++++--- .../hal/esp32p4/include/hal/parlio_ll.h | 95 +++++++++++++------ .../soc/esp32p4/include/soc/gpio_sig_map.h | 2 +- components/soc/esp32p4/parlio_periph.c | 2 +- 5 files changed, 102 insertions(+), 46 deletions(-) diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_board.h b/components/esp_driver_parlio/test_apps/parlio/main/test_board.h index 067529d382..dc8251b599 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_board.h +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_board.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -68,6 +68,14 @@ extern "C" { #define TEST_DATA5_GPIO 29 #define TEST_DATA6_GPIO 30 #define TEST_DATA7_GPIO 31 +#define TEST_DATA8_GPIO 35 +#define TEST_DATA9_GPIO 36 +#define TEST_DATA10_GPIO 39 +#define TEST_DATA11_GPIO 40 +#define TEST_DATA12_GPIO 41 +#define TEST_DATA13_GPIO 42 +#define TEST_DATA14_GPIO 43 +#define TEST_DATA15_GPIO 44 #else #error "Unsupported target" #endif diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c index 942e037608..4d161f4195 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c @@ -294,18 +294,10 @@ TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]") #if !PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG TEST_CASE("parallel_tx_clock_gating_and_msb_coexist", "[paralio_tx]") { - printf("init a gpio to read parlio_tx clk output\r\n"); - gpio_config_t test_gpio_conf = { - .mode = GPIO_MODE_INPUT, - .pin_bit_mask = BIT64(TEST_CLK_GPIO) | BIT64(TEST_DATA7_GPIO), - }; - TEST_ESP_OK(gpio_config(&test_gpio_conf)); - - printf("install parlio tx unit\r\n"); parlio_tx_unit_handle_t tx_unit = NULL; parlio_tx_unit_config_t config = { .clk_src = PARLIO_CLK_SRC_DEFAULT, - .data_width = 8, + .data_width = PARLIO_TX_UNIT_MAX_DATA_WIDTH, .clk_in_gpio_num = -1, // use internal clock source .valid_gpio_num = TEST_VALID_GPIO, // generate the valid signal .clk_out_gpio_num = TEST_CLK_GPIO, @@ -318,6 +310,16 @@ TEST_CASE("parallel_tx_clock_gating_and_msb_coexist", "[paralio_tx]") TEST_DATA5_GPIO, TEST_DATA6_GPIO, TEST_DATA7_GPIO, +#if PARLIO_TX_UNIT_MAX_DATA_WIDTH > 8 + TEST_DATA8_GPIO, + TEST_DATA9_GPIO, + TEST_DATA10_GPIO, + TEST_DATA11_GPIO, + TEST_DATA12_GPIO, + TEST_DATA13_GPIO, + TEST_DATA14_GPIO, + TEST_DATA15_GPIO, +#endif }, .output_clk_freq_hz = 1 * 1000 * 1000, .trans_queue_depth = 4, @@ -328,13 +330,23 @@ TEST_CASE("parallel_tx_clock_gating_and_msb_coexist", "[paralio_tx]") .valid_stop_delay = 5, .flags.clk_gate_en = true, // enable clock gating, controlled by the CS signal }; + + printf("init a gpio to read parlio_tx clk output\r\n"); + gpio_num_t msb_gpio_num = config.data_gpio_nums[PARLIO_TX_UNIT_MAX_DATA_WIDTH - 1]; + gpio_config_t test_gpio_conf = { + .mode = GPIO_MODE_INPUT, + .pin_bit_mask = BIT64(TEST_CLK_GPIO) | BIT64(msb_gpio_num), + }; + TEST_ESP_OK(gpio_config(&test_gpio_conf)); + + printf("install parlio tx unit\r\n"); TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); printf("send packets and see if the clock is gated when there's no transaction on line\r\n"); parlio_transmit_config_t transmit_config = { - // set the idle value to 0x80, so that the MSB is high when there's no transaction - .idle_value = 0x80, + // set the idle value to 1 << (PARLIO_TX_UNIT_MAX_DATA_WIDTH - 1), so that the MSB is high when there's no transaction + .idle_value = 1 << (PARLIO_TX_UNIT_MAX_DATA_WIDTH - 1), }; uint32_t size = 256; __attribute__((aligned(64))) uint8_t payload[size]; @@ -345,16 +357,17 @@ TEST_CASE("parallel_tx_clock_gating_and_msb_coexist", "[paralio_tx]") TEST_ESP_OK(parlio_tx_unit_wait_all_done(tx_unit, -1)); // check if the level on the clock line is low TEST_ASSERT_EQUAL(0, gpio_get_level(TEST_CLK_GPIO)); - TEST_ASSERT_EQUAL(1, gpio_get_level(TEST_DATA7_GPIO)); + TEST_ASSERT_EQUAL(1, gpio_get_level(msb_gpio_num)); TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload, size * sizeof(uint8_t) * 8, &transmit_config)); TEST_ESP_OK(parlio_tx_unit_wait_all_done(tx_unit, -1)); TEST_ASSERT_EQUAL(0, gpio_get_level(TEST_CLK_GPIO)); TEST_ASSERT_EQUAL(0, gpio_get_level(TEST_CLK_GPIO)); - TEST_ASSERT_EQUAL(1, gpio_get_level(TEST_DATA7_GPIO)); + TEST_ASSERT_EQUAL(1, gpio_get_level(msb_gpio_num)); TEST_ESP_OK(parlio_tx_unit_disable(tx_unit)); TEST_ESP_OK(parlio_del_tx_unit(tx_unit)); TEST_ESP_OK(gpio_reset_pin(TEST_CLK_GPIO)); + TEST_ESP_OK(gpio_reset_pin(msb_gpio_num)); } #endif // !PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG #endif // SOC_PARLIO_TX_CLK_SUPPORT_GATING diff --git a/components/hal/esp32p4/include/hal/parlio_ll.h b/components/hal/esp32p4/include/hal/parlio_ll.h index 2e6327394f..be352a4ce0 100644 --- a/components/hal/esp32p4/include/hal/parlio_ll.h +++ b/components/hal/esp32p4/include/hal/parlio_ll.h @@ -14,6 +14,7 @@ #include "hal/misc.h" #include "hal/parlio_types.h" #include "hal/hal_utils.h" +#include "hal/config.h" #include "soc/hp_sys_clkrst_struct.h" #include "soc/lp_clkrst_struct.h" #include "soc/parl_io_struct.h" @@ -33,9 +34,17 @@ #define PARLIO_LL_EVENT_TX_MASK (PARLIO_LL_EVENT_TX_FIFO_EMPTY | PARLIO_LL_EVENT_TX_EOF) #define PARLIO_LL_EVENT_RX_MASK (PARLIO_LL_EVENT_RX_FIFO_FULL) + +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) < 300 #define PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG 15 // TXD[15] can be used a valid signal +#endif + #define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 15 // TXD[15] can be used as clock gate signal +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +#define PARLIO_LL_TX_VALID_MAX_DELAY 32767 +#endif + #ifdef __cplusplus extern "C" { #endif @@ -553,23 +562,6 @@ static inline void parlio_ll_tx_set_trans_bit_len(parl_io_dev_t *dev, uint32_t b dev->tx_data_cfg.tx_bitlen = bitlen; } -/** - * @brief Set TX valid signal delay - * - * @param dev Parallel IO register base address - * @param start_delay Number of clock cycles to delay - * @param stop_delay Number of clock cycles to delay - * @return true: success, false: valid delay is not supported - */ -static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t start_delay, uint32_t stop_delay) -{ - (void)dev; - if (start_delay == 0 && stop_delay == 0) { - return true; - } - return false; -} - /** * @brief Check if tx size can be determined by DMA * @@ -621,19 +613,6 @@ static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en) dev->tx_start_cfg.tx_start = en; } -/** - * @brief Whether to treat the MSB of TXD as the valid signal - * - * @note If enabled, TXD[15] will work as valid signal, which stay high during data transmission. - * - * @param dev Parallel IO register base address - * @param en True to enable, False to disable - */ -static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en) -{ - dev->tx_genrl_cfg.tx_valid_output_en = en; -} - /** * @brief Set the sample clock edge * @@ -794,6 +773,62 @@ static inline volatile void *parlio_ll_get_interrupt_status_reg(parl_io_dev_t *d return &dev->int_st; } +/**********************************************************************************************************************/ +/************************ The following functions behave differently based on the chip revision ***********************/ +/**********************************************************************************************************************/ + +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +/** + * @brief Set the clock gating from the valid signal + * + * @param dev Parallel IO register base address + * @param en If set to true, the clock is gated by the valid signal, otherwise it is gated by the MSB of the data line. + */ +static inline void parlio_ll_tx_clock_gating_from_valid(parl_io_dev_t *dev, bool en) +{ + dev->tx_genrl_cfg.tx_valid_output_en = en; +} +#else +/** + * @brief Whether to treat the MSB of TXD as the valid signal + * + * @note If enabled, TXD[15] will work as valid signal, which stay high during data transmission. + * + * @param dev Parallel IO register base address + * @param en True to enable, False to disable + */ +static inline void parlio_ll_tx_treat_msb_as_valid(parl_io_dev_t *dev, bool en) +{ + dev->tx_genrl_cfg.tx_valid_output_en = en; +} +#endif + +/** + * @brief Set TX valid signal delay + * + * @param dev Parallel IO register base address + * @param start_delay Number of clock cycles to delay + * @param stop_delay Number of clock cycles to delay + * @return true: success, false: valid delay is not supported + */ +static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t start_delay, uint32_t stop_delay) +{ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 + if (start_delay > PARLIO_LL_TX_VALID_MAX_DELAY || stop_delay > PARLIO_LL_TX_VALID_MAX_DELAY) { + return false; + } + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cs_cfg, tx_cs_start_delay, start_delay); + HAL_FORCE_MODIFY_U32_REG_FIELD(dev->tx_cs_cfg, tx_cs_stop_delay, stop_delay); + return true; +#else + (void)dev; + if (start_delay == 0 && stop_delay == 0) { + return true; + } + return false; +#endif +} + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32p4/include/soc/gpio_sig_map.h b/components/soc/esp32p4/include/soc/gpio_sig_map.h index 756baafe93..e1979fb566 100644 --- a/components/soc/esp32p4/include/soc/gpio_sig_map.h +++ b/components/soc/esp32p4/include/soc/gpio_sig_map.h @@ -451,7 +451,7 @@ #define CORE_GPIO_IN_PAD_IN27_IDX 241 #define CORE_GPIO_OUT_PAD_OUT27_IDX 241 #define CORE_GPIO_IN_PAD_IN28_IDX 242 -#define PARLIO_TX_CS_PAD_OUT_IDX 242 +#define PARLIO_TX_CS_PAD_OUT_IDX 242 // only exists on ESP32P4 Rev. 3.0 and later #define CORE_GPIO_IN_PAD_IN29_IDX 243 #define EMAC_PTP_PPS_PAD_OUT_IDX 243 #define CORE_GPIO_IN_PAD_IN30_IDX 244 diff --git a/components/soc/esp32p4/parlio_periph.c b/components/soc/esp32p4/parlio_periph.c index f5fc910c58..5a7d4ce791 100644 --- a/components/soc/esp32p4/parlio_periph.c +++ b/components/soc/esp32p4/parlio_periph.c @@ -35,7 +35,7 @@ const parlio_signal_conn_t parlio_periph_signals = { }, .clk_out_sig = PARLIO_TX_CLK_PAD_OUT_IDX, .clk_in_sig = PARLIO_TX_CLK_PAD_IN_IDX, - .cs_sig = -1, + .cs_sig = PARLIO_TX_CS_PAD_OUT_IDX, } }, .rx_units = {