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https://github.com/espressif/esp-idf.git
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async memcpy: support async memcopy on esp32s2/s3
Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA
This commit is contained in:
morris
313
components/esp_system/esp_async_memcpy.c
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313
components/esp_system/esp_async_memcpy.c
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "hal/dma_types.h"
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#include "esp_compiler.h"
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#include "esp_heap_caps.h"
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#include "esp_log.h"
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#include "esp_async_memcpy.h"
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#include "esp_async_memcpy_impl.h"
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static const char *TAG = "async_memcpy";
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#define ASMCP_CHECK(a, msg, tag, ret, ...) \
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do \
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{ \
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if (unlikely(!(a))) \
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{ \
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ESP_LOGE(TAG, "%s(%d): " msg, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
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ret_code = ret; \
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goto tag; \
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} \
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} while (0)
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/**
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* @brief Type of async mcp stream
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* mcp stream inherits DMA descriptor, besides that, it has a callback function member
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*/
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typedef struct {
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dma_descriptor_t desc;
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async_memcpy_isr_cb_t cb;
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void *cb_args;
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} async_memcpy_stream_t;
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/**
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* @brief Type of async mcp driver context
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*/
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typedef struct async_memcpy_context_t {
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async_memcpy_impl_t mcp_impl; // implementation layer
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intr_handle_t intr_hdl; // interrupt handle
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uint32_t flags; // extra driver flags
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dma_descriptor_t *tx_desc; // pointer to the next free TX descriptor
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dma_descriptor_t *rx_desc; // pointer to the next free RX descriptor
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dma_descriptor_t *next_rx_desc_to_check; // pointer to the next RX descriptor to recycle
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uint32_t max_stream_num; // maximum number of streams
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async_memcpy_stream_t *out_streams; // pointer to the first TX stream
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async_memcpy_stream_t *in_streams; // pointer to the first RX stream
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async_memcpy_stream_t streams_pool[0]; // stream pool (TX + RX), the size is configured during driver installation
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} async_memcpy_context_t;
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esp_err_t esp_async_memcpy_install(const async_memcpy_config_t *config, async_memcpy_t *asmcp)
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{
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esp_err_t ret_code = ESP_OK;
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async_memcpy_context_t *mcp_hdl = NULL;
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ASMCP_CHECK(config, "configuration can't be null", err, ESP_ERR_INVALID_ARG);
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ASMCP_CHECK(asmcp, "can't assign mcp handle to null", err, ESP_ERR_INVALID_ARG);
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// context memory size + stream pool size
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size_t total_malloc_size = sizeof(async_memcpy_context_t) + sizeof(async_memcpy_stream_t) * config->backlog * 2;
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// to work when cache is disabled, the driver handle should located in SRAM
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mcp_hdl = heap_caps_calloc(1, total_malloc_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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ASMCP_CHECK(mcp_hdl, "allocate context memory failed", err, ESP_ERR_NO_MEM);
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int int_flags = ESP_INTR_FLAG_IRAM; // interrupt can still work when cache is disabled
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// allocate interrupt handle, it's target dependent
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ret_code = async_memcpy_impl_allocate_intr(&mcp_hdl->mcp_impl, int_flags, &mcp_hdl->intr_hdl);
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ASMCP_CHECK(ret_code == ESP_OK, "allocate interrupt handle failed", err, ret_code);
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mcp_hdl->flags = config->flags;
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mcp_hdl->out_streams = mcp_hdl->streams_pool;
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mcp_hdl->in_streams = mcp_hdl->streams_pool + config->backlog;
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mcp_hdl->max_stream_num = config->backlog;
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// circle TX/RX descriptors
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for (int i = 0; i < mcp_hdl->max_stream_num; i++) {
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mcp_hdl->out_streams[i].desc.dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU;
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mcp_hdl->out_streams[i].desc.next = &mcp_hdl->out_streams[i + 1].desc;
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mcp_hdl->in_streams[i].desc.dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU;
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mcp_hdl->in_streams[i].desc.next = &mcp_hdl->in_streams[i + 1].desc;
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}
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mcp_hdl->out_streams[mcp_hdl->max_stream_num - 1].desc.next = &mcp_hdl->out_streams[0].desc;
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mcp_hdl->in_streams[mcp_hdl->max_stream_num - 1].desc.next = &mcp_hdl->in_streams[0].desc;
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mcp_hdl->tx_desc = &mcp_hdl->out_streams[0].desc;
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mcp_hdl->rx_desc = &mcp_hdl->in_streams[0].desc;
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mcp_hdl->next_rx_desc_to_check = &mcp_hdl->in_streams[0].desc;
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// initialize implementation layer
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async_memcpy_impl_init(&mcp_hdl->mcp_impl, &mcp_hdl->out_streams[0].desc, &mcp_hdl->in_streams[0].desc);
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*asmcp = mcp_hdl;
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async_memcpy_impl_start(&mcp_hdl->mcp_impl);
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return ESP_OK;
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err:
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if (mcp_hdl) {
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if (mcp_hdl->intr_hdl) {
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esp_intr_free(mcp_hdl->intr_hdl);
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}
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free(mcp_hdl);
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}
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if (asmcp) {
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*asmcp = NULL;
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}
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return ret_code;
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}
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esp_err_t esp_async_memcpy_uninstall(async_memcpy_t asmcp)
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{
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esp_err_t ret_code = ESP_OK;
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ASMCP_CHECK(asmcp, "mcp handle can't be null", err, ESP_ERR_INVALID_ARG);
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esp_intr_free(asmcp->intr_hdl);
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async_memcpy_impl_stop(&asmcp->mcp_impl);
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async_memcpy_impl_deinit(&asmcp->mcp_impl);
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free(asmcp);
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return ESP_OK;
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err:
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return ret_code;
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}
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static int async_memcpy_prepare_receive(async_memcpy_t asmcp, void *buffer, size_t size, dma_descriptor_t **start_desc, dma_descriptor_t **end_desc)
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{
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uint32_t prepared_length = 0;
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uint8_t *buf = (uint8_t *)buffer;
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dma_descriptor_t *desc = asmcp->rx_desc; // descriptor iterator
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dma_descriptor_t *start = desc;
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dma_descriptor_t *end = desc;
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while (size > DMA_DESCRIPTOR_BUFFER_MAX_SIZE) {
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if (desc->dw0.owner != DMA_DESCRIPTOR_BUFFER_OWNER_DMA) {
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desc->dw0.size = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
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desc->buffer = &buf[prepared_length];
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desc = desc->next; // move to next descriptor
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prepared_length += DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
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size -= DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
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} else {
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// out of RX descriptors
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goto _exit;
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}
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}
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if (size) {
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if (desc->dw0.owner != DMA_DESCRIPTOR_BUFFER_OWNER_DMA) {
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end = desc; // the last descriptor used
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desc->dw0.size = size;
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desc->buffer = &buf[prepared_length];
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desc = desc->next; // move to next descriptor
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prepared_length += size;
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} else {
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// out of RX descriptors
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goto _exit;
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}
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}
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_exit:
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*start_desc = start;
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*end_desc = end;
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return prepared_length;
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}
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static int async_memcpy_prepare_transmit(async_memcpy_t asmcp, void *buffer, size_t len, dma_descriptor_t **start_desc, dma_descriptor_t **end_desc)
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{
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uint32_t prepared_length = 0;
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uint8_t *buf = (uint8_t *)buffer;
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dma_descriptor_t *desc = asmcp->tx_desc; // descriptor iterator
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dma_descriptor_t *start = desc;
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dma_descriptor_t *end = desc;
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while (len > DMA_DESCRIPTOR_BUFFER_MAX_SIZE) {
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if (desc->dw0.owner != DMA_DESCRIPTOR_BUFFER_OWNER_DMA) {
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desc->dw0.suc_eof = 0; // not the end of the transaction
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desc->dw0.size = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
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desc->dw0.length = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
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desc->buffer = &buf[prepared_length];
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desc = desc->next; // move to next descriptor
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prepared_length += DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
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len -= DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
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} else {
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// out of TX descriptors
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goto _exit;
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}
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}
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if (len) {
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if (desc->dw0.owner != DMA_DESCRIPTOR_BUFFER_OWNER_DMA) {
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end = desc; // the last descriptor used
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desc->dw0.suc_eof = 1; // end of the transaction
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desc->dw0.size = len;
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desc->dw0.length = len;
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desc->buffer = &buf[prepared_length];
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desc = desc->next; // move to next descriptor
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prepared_length += len;
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} else {
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// out of TX descriptors
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goto _exit;
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}
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}
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*start_desc = start;
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*end_desc = end;
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_exit:
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return prepared_length;
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}
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static bool async_memcpy_get_next_rx_descriptor(async_memcpy_t asmcp, dma_descriptor_t *eof_desc, dma_descriptor_t **next_desc)
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{
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dma_descriptor_t *next = asmcp->next_rx_desc_to_check;
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// additional check, to avoid potential interrupt got triggered by mistake
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if (next->dw0.owner == DMA_DESCRIPTOR_BUFFER_OWNER_CPU) {
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asmcp->next_rx_desc_to_check = asmcp->next_rx_desc_to_check->next;
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*next_desc = next;
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// return if we need to continue
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return eof_desc == next ? false : true;
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}
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*next_desc = NULL;
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return false;
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}
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esp_err_t esp_async_memcpy(async_memcpy_t asmcp, void *dst, void *src, size_t n, async_memcpy_isr_cb_t cb_isr, void *cb_args)
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{
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esp_err_t ret_code = ESP_OK;
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dma_descriptor_t *rx_start_desc = NULL;
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dma_descriptor_t *rx_end_desc = NULL;
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dma_descriptor_t *tx_start_desc = NULL;
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dma_descriptor_t *tx_end_desc = NULL;
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int rx_prepared_size = 0;
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int tx_prepared_size = 0;
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ASMCP_CHECK(asmcp, "mcp handle can't be null", err, ESP_ERR_INVALID_ARG);
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ASMCP_CHECK(async_memcpy_impl_is_buffer_address_valid(&asmcp->mcp_impl, src, dst), "buffer address not valid", err, ESP_ERR_INVALID_ARG);
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ASMCP_CHECK(n <= DMA_DESCRIPTOR_BUFFER_MAX_SIZE * asmcp->max_stream_num, "buffer size too large", err, ESP_ERR_INVALID_ARG);
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// Prepare TX and RX descriptor
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portENTER_CRITICAL_SAFE(&asmcp->mcp_impl.hal_lock);
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rx_prepared_size = async_memcpy_prepare_receive(asmcp, dst, n, &rx_start_desc, &rx_end_desc);
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tx_prepared_size = async_memcpy_prepare_transmit(asmcp, src, n, &tx_start_desc, &tx_end_desc);
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if ((rx_prepared_size == n) && (tx_prepared_size == n)) {
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// register user callback to the last descriptor
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async_memcpy_stream_t *mcp_stream = __containerof(rx_end_desc, async_memcpy_stream_t, desc);
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mcp_stream->cb = cb_isr;
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mcp_stream->cb_args = cb_args;
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// restart RX firstly
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dma_descriptor_t *desc = rx_start_desc;
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while (desc != rx_end_desc) {
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desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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desc = desc->next;
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}
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desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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asmcp->rx_desc = desc->next;
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// restart TX secondly
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desc = tx_start_desc;
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while (desc != tx_end_desc) {
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desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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desc = desc->next;
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}
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desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
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asmcp->tx_desc = desc->next;
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async_memcpy_impl_restart(&asmcp->mcp_impl);
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}
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portEXIT_CRITICAL_SAFE(&asmcp->mcp_impl.hal_lock);
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// It's unlikely that we have space for rx descriptor but no space for tx descriptor
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// Both tx and rx descriptor should move in the same pace
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ASMCP_CHECK(rx_prepared_size == n, "out of rx descriptor", err, ESP_FAIL);
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ASMCP_CHECK(tx_prepared_size == n, "out of tx descriptor", err, ESP_FAIL);
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return ESP_OK;
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err:
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return ret_code;
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}
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IRAM_ATTR void async_memcpy_isr_on_rx_done_event(async_memcpy_impl_t *impl)
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{
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bool to_continue = false;
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async_memcpy_stream_t *in_stream = NULL;
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dma_descriptor_t *next_desc = NULL;
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async_memcpy_context_t *asmcp = __containerof(impl, async_memcpy_context_t, mcp_impl);
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// get the RX eof descriptor address
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dma_descriptor_t *eof = async_memcpy_impl_get_rx_suc_eof_descriptor(impl);
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// traversal all unchecked descriptors
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do {
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portENTER_CRITICAL_ISR(&impl->hal_lock);
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// There is an assumption that the usage of rx descriptors are in the same pace as tx descriptors (this is determined by M2M DMA working mechanism)
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// And once the rx descriptor is recycled, the corresponding tx desc is guaranteed to be returned by DMA
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to_continue = async_memcpy_get_next_rx_descriptor(asmcp, eof, &next_desc);
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portEXIT_CRITICAL_ISR(&impl->hal_lock);
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if (next_desc) {
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in_stream = __containerof(next_desc, async_memcpy_stream_t, desc);
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// invoke user registered callback if available
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if (in_stream->cb) {
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async_memcpy_event_t e = {0};
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if (in_stream->cb(asmcp, &e, in_stream->cb_args)) {
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impl->isr_need_yield = true;
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}
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in_stream->cb = NULL;
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in_stream->cb_args = NULL;
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}
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}
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} while (to_continue);
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}
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