mirror of
https://github.com/espressif/esp-idf.git
synced 2025-12-15 19:34:03 +00:00
async memcpy: support async memcopy on esp32s2/s3
Added async memory copy API: on esp32-s2, the implementation is based on CP_DMA on esp32-s3, the implementation is based on GDMA
This commit is contained in:
morris
@@ -74,10 +74,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
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return SYSTEM_SPI3_CLK_EN;
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case PERIPH_VSPI_MODULE:
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return SYSTEM_SPI4_CLK_EN;
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case PERIPH_SPI2_DMA_MODULE:
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return SYSTEM_SPI2_DMA_CLK_EN;
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case PERIPH_SPI3_DMA_MODULE:
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return SYSTEM_SPI3_DMA_CLK_EN;
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case PERIPH_SDMMC_MODULE:
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return SYSTEM_SDIO_HOST_CLK_EN;
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case PERIPH_TWAI_MODULE:
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@@ -94,6 +90,10 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
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return SYSTEM_BT_BASEBAND_EN;
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case PERIPH_BT_LC_MODULE:
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return SYSTEM_BT_LC_EN;
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case PERIPH_SYSTIMER_MODULE:
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return SYSTEM_SYSTIMER_CLK_EN;
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case PERIPH_GDMA_MODULE:
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return SYSTEM_DMA_CLK_EN;
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default:
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return 0;
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}
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@@ -151,14 +151,14 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
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return SYSTEM_SPI3_RST;
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case PERIPH_VSPI_MODULE:
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return SYSTEM_SPI4_RST;
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case PERIPH_SPI2_DMA_MODULE:
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return SYSTEM_SPI2_DMA_RST;
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case PERIPH_SPI3_DMA_MODULE:
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return SYSTEM_SPI3_DMA_RST;
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case PERIPH_SDMMC_MODULE:
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return SYSTEM_SDIO_HOST_RST;
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case PERIPH_TWAI_MODULE:
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return SYSTEM_TWAI_RST;
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case PERIPH_SYSTIMER_MODULE:
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return SYSTEM_SYSTIMER_RST;
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case PERIPH_GDMA_MODULE:
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return SYSTEM_DMA_RST;
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default:
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return 0;
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}
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@@ -176,7 +176,7 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
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return SYSTEM_WIFI_CLK_EN_REG ;
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case PERIPH_UART2_MODULE:
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case PERIPH_SDMMC_MODULE:
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case PERIPH_SPI_SHARED_DMA_MODULE:
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case PERIPH_GDMA_MODULE:
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return SYSTEM_PERIP_CLK_EN1_REG;
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default:
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return SYSTEM_PERIP_CLK_EN0_REG;
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@@ -195,7 +195,7 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
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return SYSTEM_CORE_RST_EN_REG;
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case PERIPH_UART2_MODULE:
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case PERIPH_SDMMC_MODULE:
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case PERIPH_SPI_SHARED_DMA_MODULE:
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case PERIPH_GDMA_MODULE:
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return SYSTEM_PERIP_RST_EN1_REG;
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default:
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return SYSTEM_PERIP_RST_EN0_REG;
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@@ -228,4 +228,3 @@ static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
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#ifdef __cplusplus
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}
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#endif
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495
components/hal/esp32s3/include/hal/gdma_ll.h
Normal file
495
components/hal/esp32s3/include/hal/gdma_ll.h
Normal file
@@ -0,0 +1,495 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/gdma_struct.h"
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#include "soc/gdma_reg.h"
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#include "soc/gdma_caps.h"
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#define GDMA_LL_EVENT_TX_L3_FIFO_UDF (1<<17)
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#define GDMA_LL_EVENT_TX_L3_FIFO_OVF (1<<16)
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#define GDMA_LL_EVENT_TX_L1_FIFO_UDF (1<<15)
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#define GDMA_LL_EVENT_TX_L1_FIFO_OVF (1<<14)
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#define GDMA_LL_EVENT_RX_L3_FIFO_UDF (1<<13)
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#define GDMA_LL_EVENT_RX_L3_FIFO_OVF (1<<12)
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#define GDMA_LL_EVENT_RX_L1_FIFO_UDF (1<<11)
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#define GDMA_LL_EVENT_RX_L1_FIFO_OVF (1<<10)
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#define GDMA_LL_EVENT_RX_WATER_MARK (1<<9)
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#define GDMA_LL_EVENT_TX_TOTAL_EOF (1<<8)
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#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<7)
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#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<6)
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#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<5)
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#define GDMA_LL_EVENT_TX_EOF (1<<4)
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#define GDMA_LL_EVENT_TX_DONE (1<<3)
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#define GDMA_LL_EVENT_RX_ERR_EOF (1<<2)
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#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
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#define GDMA_LL_EVENT_RX_DONE (1<<0)
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#define GDMA_LL_TRIG_SRC_SPI2 (0)
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#define GDMA_LL_TRIG_SRC_SPI3 (1)
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#define GDMA_LL_TRIG_SRC_UART (2)
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#define GDMA_LL_TRIG_SRC_I2S0 (3)
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#define GDMA_LL_TRIG_SRC_I2S1 (4)
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#define GDMA_LL_TRIG_SRC_LCD_CAM (5)
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#define GDMA_LL_TRIG_SRC_AES (6)
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#define GDMA_LL_TRIG_SRC_SHA (7)
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#define GDMA_LL_TRIG_SRC_ADC_DAC (8)
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///////////////////////////////////// Common /////////////////////////////////////////
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/**
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* @brief Enable DMA channel M2M mode (TX channel n forward data to RX channel n), disabled by default
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*/
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static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf0[channel].mem_trans_en = enable;
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if (!enable) {
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dev->peri_sel[channel].peri_in_sel = 0;
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dev->peri_sel[channel].peri_out_sel = 0;
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}
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}
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/**
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* @brief Enable DMA to check the owner bit in the descriptor, disabled by default
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*/
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static inline void gdma_ll_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf1[channel].check_owner = enable;
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}
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/**
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* @brief Get DMA interrupt status word
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*/
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static inline uint32_t gdma_ll_get_interrupt_status(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->int_st[channel].val;
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}
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/**
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* @brief Enable DMA interrupt
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*/
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static inline void gdma_ll_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
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{
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if (enable) {
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dev->int_ena[channel].val |= mask;
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} else {
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dev->int_ena[channel].val &= ~mask;
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}
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}
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/**
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* @brief Clear DMA interrupt
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*/
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static inline void gdma_ll_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
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{
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dev->int_clr[channel].val = mask;
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}
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/**
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* @brief Enable DMA clock gating
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*/
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static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable)
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{
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dev->misc_conf.clk_en = enable;
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}
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///////////////////////////////////// RX /////////////////////////////////////////
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/**
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* @brief Enable DMA RX channel burst reading data, disabled by default
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*/
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static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf0[channel].in_data_burst_en = enable;
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}
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/**
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* @brief Enable DMA RX channel burst reading descriptor link, disabled by default
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*/
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static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf0[channel].indscr_burst_en = enable;
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}
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/**
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* @brief Reset DMA RX channel FSM and FIFO pointer
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*/
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static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
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{
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dev->conf0[channel].in_rst = 1;
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dev->conf0[channel].in_rst = 0;
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}
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/**
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* @brief Set DMA RX channel memory block size
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* @param size_index Supported value: GDMA_IN_EXT_MEM_BK_SIZE_16B, GDMA_IN_EXT_MEM_BK_SIZE_32B
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*/
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static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
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{
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dev->conf1[channel].in_ext_mem_bk_size = size_index;
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}
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/**
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* @brief Set the water mark for RX channel, default value is 12
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*/
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static inline void gdma_ll_rx_set_water_mark(gdma_dev_t *dev, uint32_t channel, uint32_t water_mark)
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{
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dev->conf1[channel].infifo_full_thrs = water_mark;
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}
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/**
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* @brief Check if DMA RX FIFO is full
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* @param fifo_level (1,2,3) <=> (L1, L2, L3)
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*/
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static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->infifo_status[channel].val & (1 << 2 * (fifo_level - 1));
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}
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/**
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* @brief Check if DMA RX FIFO is empty
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* @param fifo_level (1,2,3) <=> (L1, L2, L3)
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*/
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static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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return dev->infifo_status[channel].val & (1 << (2 * (fifo_level - 1) + 1));
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}
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/**
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* @brief Get number of bytes in RX FIFO (L1, L2, L3)
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* @param fifo_level (1,2,3) <=> (L1, L2, L3)
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*/
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static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
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{
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switch (fifo_level) {
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case 1:
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return dev->infifo_status[channel].infifo_cnt_l1;
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case 2:
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return dev->infifo_status[channel].infifo_cnt_l2;
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case 3:
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return dev->infifo_status[channel].infifo_cnt_l3;
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}
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}
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/**
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* @brief Pop data from DMA RX FIFO
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*/
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static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
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{
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dev->in_pop[channel].infifo_pop = 1;
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return dev->in_pop[channel].infifo_rdata;
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}
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/**
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* @brief Set the descriptor link base address for RX channel
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*/
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static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
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{
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dev->in_link[channel].addr = addr;
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}
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/**
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* @brief Start dealing with RX descriptors
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*/
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static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
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{
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dev->in_link[channel].start = 1;
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}
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/**
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* @brief Stop dealing with RX descriptors
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*/
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static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
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{
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dev->in_link[channel].stop = 1;
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}
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/**
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* @brief Restart a new inlink right after the last descriptor
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*/
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static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
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{
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dev->in_link[channel].restart = 1;
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}
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/**
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* @brief Enable DMA RX to return the address of current descriptor when receives error
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*/
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static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->in_link[channel].auto_ret = enable;
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}
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/**
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* @brief Check if DMA RX FSM is in IDLE state
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*/
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static inline bool gdma_ll_rx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->in_link[channel].park;
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}
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/**
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* @brief Get RX success EOF descriptor's address
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*/
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static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->in_suc_eof_des_addr[channel];
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}
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/**
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* @brief Get RX error EOF descriptor's address
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*/
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static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->in_err_eof_des_addr[channel];
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}
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/**
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* @brief Get current RX descriptor's address
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*/
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static inline uint32_t gdma_ll_rx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
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{
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return dev->in_dscr[channel];
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}
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/**
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* @brief Set weight for DMA RX channel
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*/
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static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight)
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{
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dev->wight[channel].rx_weight = weight;
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}
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/**
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* @brief Set priority for DMA RX channel
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*/
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static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
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{
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dev->pri[channel].rx_pri = prio;
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}
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/**
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* @brief Connect DMA RX channel to a given peripheral
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*/
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static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, uint32_t periph_id)
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{
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dev->peri_sel[channel].peri_in_sel = periph_id;
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}
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/**
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* @brief Extend the L2 FIFO size for RX channel
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* @note By default, the L2 FIFO size is SOC_GDMA_L2_FIFO_BASE_SIZE Bytes. Suggest to extend it to twice the block size when accessing PSRAM.
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* @note `size_in_bytes` should aligned to 8 and larger than SOC_GDMA_L2_FIFO_BASE_SIZE
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*/
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static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
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{
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if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
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dev->sram_size[channel].in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
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}
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}
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///////////////////////////////////// TX /////////////////////////////////////////
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/**
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* @brief Enable DMA TX channel burst sending data, disabled by default
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*/
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static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf0[channel].out_data_burst_en = enable;
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}
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/**
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* @brief Enable DMA TX channel burst reading descriptor link, disabled by default
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*/
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static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf0[channel].outdscr_burst_en = enable;
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}
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/**
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* @brief Set TX channel EOF mode
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*/
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static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
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{
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dev->conf0[channel].out_eof_mode = mode;
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}
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/**
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* @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
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*/
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static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->conf0[channel].out_auto_wrback = enable;
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}
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/**
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* @brief Reset DMA TX channel FSM and FIFO pointer
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*/
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static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
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{
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dev->conf0[channel].out_rst = 1;
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dev->conf0[channel].out_rst = 0;
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}
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/**
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* @brief Set DMA TX channel memory block size
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* @param size_index Supported value: GDMA_OUT_EXT_MEM_BK_SIZE_16B, GDMA_OUT_EXT_MEM_BK_SIZE_32B
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*/
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static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
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{
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dev->conf1[channel].out_ext_mem_bk_size = size_index;
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}
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/**
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* @brief Check if DMA TX FIFO is full
|
||||
* @param fifo_level (1,2,3) <=> (L1, L2, L3)
|
||||
*/
|
||||
static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
|
||||
{
|
||||
return dev->outfifo_status[channel].val & (1 << 2 * (fifo_level - 1));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA TX FIFO is empty
|
||||
* @param fifo_level (1,2,3) <=> (L1, L2, L3)
|
||||
*/
|
||||
static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
|
||||
{
|
||||
return dev->outfifo_status[channel].val & (1 << (2 * (fifo_level - 1) + 1));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get number of bytes in TX FIFO (L1, L2, L3)
|
||||
* @param fifo_level (1,2,3) <=> (L1, L2, L3)
|
||||
*/
|
||||
static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
|
||||
{
|
||||
switch (fifo_level) {
|
||||
case 1:
|
||||
return dev->outfifo_status[channel].outfifo_cnt_l1;
|
||||
case 2:
|
||||
return dev->outfifo_status[channel].outfifo_cnt_l2;
|
||||
case 3:
|
||||
return dev->outfifo_status[channel].outfifo_cnt_l3;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Push data into DMA TX FIFO
|
||||
*/
|
||||
static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
|
||||
{
|
||||
dev->out_push[channel].outfifo_wdata = data;
|
||||
dev->out_push[channel].outfifo_push = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the descriptor link base address for TX channel
|
||||
*/
|
||||
static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
|
||||
{
|
||||
dev->out_link[channel].addr = addr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start dealing with TX descriptors
|
||||
*/
|
||||
static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out_link[channel].start = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop dealing with TX descriptors
|
||||
*/
|
||||
static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out_link[channel].stop = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Restart a new outlink right after the last descriptor
|
||||
*/
|
||||
static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
dev->out_link[channel].restart = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if DMA TX FSM is in IDLE state
|
||||
*/
|
||||
static inline bool gdma_ll_tx_is_fsm_idle(gdma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out_link[channel].park;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get TX EOF descriptor's address
|
||||
*/
|
||||
static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out_eof_des_addr[channel];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get current TX descriptor's address
|
||||
*/
|
||||
static inline uint32_t gdma_ll_tx_get_current_desc_addr(gdma_dev_t *dev, uint32_t channel)
|
||||
{
|
||||
return dev->out_dscr[channel];
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set weight for DMA TX channel
|
||||
*/
|
||||
static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight)
|
||||
{
|
||||
dev->wight[channel].tx_weight = weight;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set priority for DMA TX channel
|
||||
*/
|
||||
static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
|
||||
{
|
||||
dev->pri[channel].tx_pri = prio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect DMA TX channel to a given peripheral
|
||||
*/
|
||||
static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, uint32_t periph_id)
|
||||
{
|
||||
dev->peri_sel[channel].peri_out_sel = periph_id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Extend the L2 FIFO size for TX channel
|
||||
* @note By default, the L2 FIFO size is SOC_GDMA_L2_FIFO_BASE_SIZE Bytes. Suggest to extend it to twice the block size when accessing PSRAM.
|
||||
* @note `size_in_bytes` should aligned to 8 and larger than SOC_GDMA_L2_FIFO_BASE_SIZE
|
||||
*/
|
||||
static inline void gdma_ll_tx_extend_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
|
||||
{
|
||||
if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
|
||||
dev->sram_size[channel].out_size = size_in_bytes / 8;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user