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fix(esp_driver_gpio): esp32c61 gpio number update 22 -> 25

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wanckl
2024-11-07 17:48:21 +08:00
parent 5e056de1e7
commit a50c095df1
14 changed files with 483 additions and 56 deletions
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17
docs/en/api-reference/peripherals/gpio/esp32c61.inc
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@@ -9,7 +9,7 @@
.. gpio-summary
The {IDF_TARGET_NAME} chip features 22 physical GPIO pins (GPIO0 ~ GPIO21). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The {IDF_TARGET_NAME} chip features 25 physical GPIO pins (GPIO0 ~ GPIO24). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__].
The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions.
@@ -132,6 +132,21 @@ The table below provides more information on pin usage, and please note the comm
-
- SPI0/1
* - GPIO22
-
-
-
* - GPIO23
-
-
-
* - GPIO24
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-
-
.. note::
- Some pins are used as strapping pins, which can be used to select in which boot mode to load the chip, etc.. The details can be found in `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`_ > ``Strapping Pins``.