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codeclean: only S series chip VDDSDIO is configurable
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@@ -959,6 +959,10 @@ config SOC_PM_SUPPORT_VDDSDIO_PD
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bool
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default y
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config SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
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bool
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default y
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config SOC_CLK_APLL_SUPPORTED
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bool
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default y
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@@ -417,6 +417,8 @@
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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#define SOC_CONFIGURABLE_VDDSDIO_SUPPORTED (1)
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_APLL_SUPPORTED (1)
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// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
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