mirror of
https://github.com/espressif/esp-idf.git
synced 2025-11-27 04:55:53 +00:00
feat(efuse): Adds efuse ADC calib data for ESP32-C61
This commit is contained in:
Konstantin Kondrashov
@@ -40,7 +40,7 @@ extern "C" {
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*/
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#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE0_BASE + 0x8)
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/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
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* Configures the 0th 32-bit data to be programmed.
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* Configures the 0th 32-bit data to be programmmmmed.
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*/
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#define EFUSE_PGM_DATA_2 0xFFFFFFFFU
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#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
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@@ -233,14 +233,14 @@ extern "C" {
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#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
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#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 14
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/** EFUSE_USB_DREFH : RO; bitpos: [16:15]; default: 0;
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* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
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* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
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*/
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#define EFUSE_USB_DREFH 0x00000003U
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#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
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#define EFUSE_USB_DREFH_V 0x00000003U
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#define EFUSE_USB_DREFH_S 15
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/** EFUSE_USB_DREFL : RO; bitpos: [18:17]; default: 0;
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* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
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* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
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*/
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#define EFUSE_USB_DREFL 0x00000003U
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#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
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@@ -441,7 +441,7 @@ extern "C" {
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#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U
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#define EFUSE_UART_PRINT_CONTROL_S 5
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/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [7]; default: 0;
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* Represents whether ROM code is forced to send a resume commmand during SPI boot.
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* Represents whether ROM code is forced to send a resume command during SPI boot.
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*/
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#define EFUSE_FORCE_SEND_RESUME (BIT(7))
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#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
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@@ -679,49 +679,147 @@ extern "C" {
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* Represents rd_sys_part1_data4
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*/
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#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE0_BASE + 0x6c)
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/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
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* Temperature calibration data
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*/
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#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
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#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_4_S 0
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#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU
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#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
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#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU
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#define EFUSE_TEMPERATURE_SENSOR_S 0
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/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
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* ADC OCode calibration
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*/
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#define EFUSE_OCODE 0x000000FFU
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#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
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#define EFUSE_OCODE_V 0x000000FFU
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#define EFUSE_OCODE_S 9
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/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
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* Average initcode of ADC1 atten0
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*/
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0 0x000003FFU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_S)
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_V 0x000003FFU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_S 17
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/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
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* Average initcode of ADC1 atten1
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*/
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1 0x0000001FU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_S)
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_V 0x0000001FU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_S 27
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/** EFUSE_RD_SYS_PART1_DATA5_REG register
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* Represents rd_sys_part1_data5
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*/
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#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE0_BASE + 0x70)
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/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
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* Average initcode of ADC1 atten1
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*/
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#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
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#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_5_S 0
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1 0x0000001FU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_S)
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_V 0x0000001FU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_S 0
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/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
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* Average initcode of ADC1 atten2
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*/
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2 0x000003FFU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_S)
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_V 0x000003FFU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_S 5
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/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
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* Average initcode of ADC1 atten3
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*/
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3 0x000003FFU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_S)
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_V 0x000003FFU
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#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_S 15
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/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
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* HI_DOUT of ADC1 atten0
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*/
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#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU
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#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
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#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU
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#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25
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/** EFUSE_RD_SYS_PART1_DATA6_REG register
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* Represents rd_sys_part1_data6
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*/
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#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE0_BASE + 0x74)
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/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
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* HI_DOUT of ADC1 atten0
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*/
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#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
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#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_6_S 0
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#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U
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#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
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#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U
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#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0
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/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
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* HI_DOUT of ADC1 atten1
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*/
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#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU
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#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
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#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU
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#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3
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/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
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* HI_DOUT of ADC1 atten2
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*/
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#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU
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#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
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#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU
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#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13
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/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
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* HI_DOUT of ADC1 atten3
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*/
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#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU
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#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
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#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU
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#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23
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/** EFUSE_RD_SYS_PART1_DATA7_REG register
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* Represents rd_sys_part1_data7
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*/
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#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE0_BASE + 0x78)
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/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
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* HI_DOUT of ADC1 atten3
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*/
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#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
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#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
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#define EFUSE_SYS_DATA_PART1_7_S 0
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#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0))
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#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
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#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U
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#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0
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/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
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* Gap between ADC1 CH0 and average initcode
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*/
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#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
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#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
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#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
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#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1
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/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
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* Gap between ADC1 CH1 and average initcode
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*/
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#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
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#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
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#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
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#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5
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/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
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* Gap between ADC1 CH2 and average initcode
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*/
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#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
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#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
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#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
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#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9
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/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
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* Gap between ADC1 CH3 and average initcode
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*/
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#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
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#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
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#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
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#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13
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/** EFUSE_RESERVED_2_241 : R; bitpos: [31:17]; default: 0;
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* reserved
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*/
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#define EFUSE_RESERVED_2_241 0x00007FFFU
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#define EFUSE_RESERVED_2_241_M (EFUSE_RESERVED_2_241_V << EFUSE_RESERVED_2_241_S)
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#define EFUSE_RESERVED_2_241_V 0x00007FFFU
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#define EFUSE_RESERVED_2_241_S 17
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/** EFUSE_RD_USR_DATA0_REG register
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* Represents rd_usr_data0
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@@ -2071,7 +2169,7 @@ extern "C" {
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#define EFUSE_CLK_EN_S 16
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/** EFUSE_CONF_REG register
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* eFuse operation mode configuraiton register
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* eFuse operation mode configuration register
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*/
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#define EFUSE_CONF_REG (DR_REG_EFUSE0_BASE + 0x1cc)
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/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
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@@ -223,11 +223,11 @@ typedef union {
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*/
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uint32_t dis_download_manual_encrypt:1;
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/** usb_drefh : RO; bitpos: [16:15]; default: 0;
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* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
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* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
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*/
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uint32_t usb_drefh:2;
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/** usb_drefl : RO; bitpos: [18:17]; default: 0;
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* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
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* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
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*/
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uint32_t usb_drefl:2;
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/** usb_exchg_pins : RO; bitpos: [19]; default: 0;
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@@ -361,7 +361,7 @@ typedef union {
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*/
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uint32_t uart_print_control:2;
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/** force_send_resume : RO; bitpos: [7]; default: 0;
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* Represents whether ROM code is forced to send a resume commmand during SPI boot.
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* Represents whether ROM code is forced to send a resume command during SPI boot.
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*/
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uint32_t force_send_resume:1;
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/** secure_version : RO; bitpos: [23:8]; default: 0;
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@@ -583,10 +583,22 @@ typedef union {
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*/
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typedef union {
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struct {
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/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** temperature_sensor : R; bitpos: [8:0]; default: 0;
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* Temperature calibration data
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*/
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uint32_t sys_data_part1_4:32;
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uint32_t temperature_sensor:9;
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/** ocode : R; bitpos: [16:9]; default: 0;
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* ADC OCode calibration
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*/
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uint32_t ocode:8;
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/** adc1_ave_init_code_atten0 : R; bitpos: [26:17]; default: 0;
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* Average initcode of ADC1 atten0
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*/
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uint32_t adc1_ave_init_code_atten0:10;
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/** adc1_ave_init_code_atten1 : R; bitpos: [31:27]; default: 0;
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* Average initcode of ADC1 atten1
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*/
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uint32_t adc1_ave_init_code_atten1:5;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data4_reg_t;
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@@ -596,10 +608,22 @@ typedef union {
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*/
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typedef union {
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struct {
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/** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
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* Represents the zeroth 32-bit of first part of system data.
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/** adc1_ave_init_code_atten1_1 : R; bitpos: [4:0]; default: 0;
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* Average initcode of ADC1 atten1
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*/
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uint32_t sys_data_part1_5:32;
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uint32_t adc1_ave_init_code_atten1_1:5;
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/** adc1_ave_init_code_atten2 : R; bitpos: [14:5]; default: 0;
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* Average initcode of ADC1 atten2
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*/
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uint32_t adc1_ave_init_code_atten2:10;
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/** adc1_ave_init_code_atten3 : R; bitpos: [24:15]; default: 0;
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* Average initcode of ADC1 atten3
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*/
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uint32_t adc1_ave_init_code_atten3:10;
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/** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
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* HI_DOUT of ADC1 atten0
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*/
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uint32_t adc1_hi_dout_atten0:7;
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};
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uint32_t val;
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} efuse_rd_sys_part1_data5_reg_t;
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@@ -609,10 +633,22 @@ typedef union {
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*/
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typedef union {
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struct {
|
||||
/** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* HI_DOUT of ADC1 atten0
|
||||
*/
|
||||
uint32_t sys_data_part1_6:32;
|
||||
uint32_t adc1_hi_dout_atten0_1:3;
|
||||
/** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
|
||||
* HI_DOUT of ADC1 atten1
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten1:10;
|
||||
/** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
|
||||
* HI_DOUT of ADC1 atten2
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten2:10;
|
||||
/** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
|
||||
* HI_DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten3:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data6_reg_t;
|
||||
@@ -622,10 +658,30 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
|
||||
* HI_DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t sys_data_part1_7:32;
|
||||
uint32_t adc1_hi_dout_atten3_1:1;
|
||||
/** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
|
||||
* Gap between ADC1 CH0 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch0_atten0_initcode_diff:4;
|
||||
/** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
|
||||
* Gap between ADC1 CH1 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch1_atten0_initcode_diff:4;
|
||||
/** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
|
||||
* Gap between ADC1 CH2 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch2_atten0_initcode_diff:4;
|
||||
/** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
|
||||
* Gap between ADC1 CH3 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch3_atten0_initcode_diff:4;
|
||||
/** reserved_2_241 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_241:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data7_reg_t;
|
||||
@@ -1893,7 +1949,7 @@ typedef union {
|
||||
|
||||
/** Group: EFUSE Configure Registers */
|
||||
/** Type of conf register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@@ -4111,7 +4167,7 @@ typedef union {
|
||||
} efuse_apb2otp_blk10_w11_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE_APB2OTP Function Enable Singal */
|
||||
/** Group: EFUSE_APB2OTP Function Enable Signal */
|
||||
/** Type of apb2otp_en register
|
||||
* eFuse apb2otp enable configuration register.
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user