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rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in

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soc/clk_tree_defs.h
This commit is contained in:
songruojing
2022-04-21 18:24:03 +08:00
parent 436085de51
commit a5b09cf015
73 changed files with 649 additions and 1006 deletions
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31
components/soc/esp32h2/include/soc/clk_tree_defs.h
View File

@@ -34,7 +34,7 @@ extern "C" {
*
* XTAL32K_CLK can also be calibrated to get its exact frequency.
*
* 5) Internal 32kHz RC Oscillator: RC_32K
* 5) Internal 32kHz RC Oscillator: RC32K
*
* The exact frequency of this clock can be computed in runtime through calibration.
*/
@@ -45,7 +45,7 @@ extern "C" {
#define SOC_CLK_RC_SLOW_FREQ_APPROX 130000
#define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256)
/* With the default value of DFREQ = 707 */ //<---- DFREQ to be adjusted!
#define SOC_CLK_RC_32K_FREQ_APPROX 32768
#define SOC_CLK_RC32K_FREQ_APPROX 32768
#define SOC_CLK_XTAL32K_FREQ_APPROX 32768
/**
@@ -60,39 +60,42 @@ typedef enum {
SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 150kHz RC oscillator */
SOC_ROOT_CLK_EXT_XTAL, /*!< External 32MHz crystal */
SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */
SOC_ROOT_CLK_INT_RC_32K /*!< Internal 32kHz RC oscillator */
SOC_ROOT_CLK_INT_RC32K /*!< Internal 32kHz RC oscillator */
} soc_root_clk_t;
/**
* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_CPU_CLK_SRC_XTAL, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
SOC_CPU_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_XTAL_DIV, /*!< Select XTAL_D2_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_XTAL_D2 = 3, /*!< Select XTAL_D2_CLK as CPU_CLK source */
} soc_cpu_clk_src_t;
/**
* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_XTAL32K, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC_32K, /*!< Select RC_32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
} soc_rtc_slow_clk_src_t;
/**
* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
* @note Enum values are matched with the register field values on purpose
*/
typedef enum {
SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
SOC_RTC_FAST_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
} soc_rtc_fast_clk_src_t;
/**
* @brief Supported clock sources for modules (CPU, peripherials, RTC, etc.)
* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
* Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
* {[upstream]clock_name}: AHB etc.
* [attr] - optional: FAST, SLOW, D<divider>, F<freq>
@@ -103,7 +106,7 @@ typedef enum {
SOC_MOD_CLK_CPU = 1, /*< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or XTAL_D2 by configuring soc_cpu_clk_src_t */
// For RTC domain
SOC_MOD_CLK_RTC_FAST = 2, /*< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW = 3, /*< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_32K by configuring soc_rtc_slow_clk_src_t */
SOC_MOD_CLK_RTC_SLOW = 3, /*< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC32K by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_AHB = 4, /*< AHB_CLK sources from CPU with a configurable divider */
SOC_MOD_CLK_XTAL32K = 5, /*< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */

85
components/soc/esp32h2/include/soc/rtc.h
View File

@@ -9,6 +9,7 @@
#include <stddef.h>
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
@@ -49,10 +50,6 @@ extern "C" {
#define RTC_SLOW_CLK_RC32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
#define RTC_SLOW_CLK_FREQ_150K 130000
#define RTC_SLOW_CLK_FREQ_32K 32768
#define RTC_SLOW_CLK_FREQ_RC32 32768
#define OTHER_BLOCKS_POWERUP 1
#define OTHER_BLOCKS_WAIT 1
@@ -146,46 +143,16 @@ typedef enum {
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
} rtc_xtal_freq_t;
/**
* @brief CPU clock source
*/
typedef enum {
RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
RTC_CPU_FREQ_SRC_PLL, //!< PLL (96M)
RTC_CPU_FREQ_SRC_8M, //!< Internal 18M RTC oscillator
RTC_CPU_FREQ_SRC_XTAL_D2 //!< XTAL/2
} rtc_cpu_freq_src_t;
/**
* @brief CPU clock configuration structure
*/
typedef struct rtc_cpu_freq_config_s {
rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived
soc_cpu_clk_src_t source; //!< The clock from which CPU clock is derived
uint32_t source_freq_mhz; //!< Source clock frequency
uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div
uint32_t freq_mhz; //!< CPU clock frequency
} rtc_cpu_freq_config_t;
/**
* @brief RTC SLOW_CLK frequency values
*/
typedef enum {
RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator
RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
RTC_SLOW_FREQ_RC32K = 2, //!< Internal 32 KHz RC oscillator
} rtc_slow_freq_t;
/**
* @brief RTC FAST_CLK frequency values
*/
typedef enum {
RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4
RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator
} rtc_fast_freq_t;
/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
#define RTC_FAST_CLK_FREQ_APPROX 8500000
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
@@ -204,15 +171,15 @@ typedef enum {
* Initialization parameters for rtc_clk_init
*/
typedef struct {
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
soc_rtc_fast_clk_src_t fast_clk_src : 1; //!< RTC_FAST_CLK clock source to choose
soc_rtc_slow_clk_src_t slow_clk_src : 2; //!< RTC_SLOW_CLK clock source to choose
uint32_t clk_rtc_clk_div : 8;
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
uint32_t clk_8m_dfreq : 10; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
uint32_t root_clk_slt : 2; //!< Select clock root source for esp32h2 (default 0: xtal_32M)
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
uint32_t clk_8m_dfreq : 10; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
uint32_t root_clk_slt : 2; //!< Select clock root source for esp32h2 (default 0: xtal_32M)
} rtc_clk_config_t;
/**
@@ -221,8 +188,8 @@ typedef struct {
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = RTC_XTAL_FREQ_32M, \
.cpu_freq_mhz = 32, \
.fast_freq = RTC_FAST_FREQ_8M, \
.slow_freq = RTC_SLOW_FREQ_RTC, \
.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
.clk_rtc_clk_div = 1, \
.clk_8m_clk_div = 1, \
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
@@ -339,6 +306,12 @@ bool rtc_clk_32k_enabled(void);
*/
void rtc_clk_32k_bootstrap(uint32_t cycle);
/**
* @brief Enable or disable 32 kHz internal rc oscillator
* @param en true to enable, false to disable
*/
void rtc_clk_rc32k_enable(bool enable);
/**
* @brief Enable or disable 8 MHz internal oscillator
*
@@ -371,22 +344,22 @@ bool rtc_clk_8md256_enabled(void);
/**
* @brief Select source for RTC_SLOW_CLK
* @param slow_freq clock source (one of rtc_slow_freq_t values)
* @param slow_freq clock source (one of soc_rtc_slow_clk_src_t values)
*/
void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t slow_freq);
/**
* @brief Get the RTC_SLOW_CLK source
* @return currently selected clock source (one of rtc_slow_freq_t values)
* @return currently selected clock source (one of soc_rtc_slow_clk_src_t values)
*/
rtc_slow_freq_t rtc_clk_slow_freq_get(void);
soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void);
/**
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
*
* - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
* - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
* - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
* - if SOC_RTC_SLOW_CLK_SRC_RC_SLOW is selected, returns ~150000
* - if SOC_RTC_SLOW_CLK_SRC_XTAL32K is selected, returns 32768
* - if SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256 is selected, returns ~33000
*
* rtc_clk_cal function can be used to get more precise value by comparing
* RTC_SLOW_CLK frequency to the frequency of main XTAL.
@@ -397,15 +370,15 @@ uint32_t rtc_clk_slow_freq_get_hz(void);
/**
* @brief Select source for RTC_FAST_CLK
* @param fast_freq clock source (one of rtc_fast_freq_t values)
* @param fast_freq clock source (one of soc_rtc_fast_clk_src_t values)
*/
void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t fast_freq);
/**
* @brief Get the RTC_FAST_CLK source
* @return currently selected clock source (one of rtc_fast_freq_t values)
* @return currently selected clock source (one of soc_rtc_fast_clk_src_t values)
*/
rtc_fast_freq_t rtc_clk_fast_freq_get(void);
soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void);
/**
* @brief Get CPU frequency config for a given frequency