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Merge branch 'feature/mcpwm_support_c5' into 'master'

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feat(mcpwm): add driver support on esp32c5

Closes IDF-8709 and IDF-9101

See merge request espressif/esp-idf!29876
This commit is contained in:
morris
2024-05-29 10:27:35 +08:00
parent bfc1ecdb4b de5fb9f070
commit a7ffe77de0
24 changed files with 2065 additions and 356 deletions
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60
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
View File

@@ -23,6 +23,10 @@ config SOC_PCNT_SUPPORTED
bool
default y
config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
@@ -423,6 +427,62 @@ config SOC_RMT_SUPPORT_XTAL
bool
default y
config SOC_MCPWM_GROUPS
int
default 1
config SOC_MCPWM_TIMERS_PER_GROUP
int
default 3
config SOC_MCPWM_OPERATORS_PER_GROUP
int
default 3
config SOC_MCPWM_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GENERATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR
int
default 2
config SOC_MCPWM_TRIGGERS_PER_OPERATOR
int
default 2
config SOC_MCPWM_GPIO_FAULTS_PER_GROUP
int
default 3
config SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP
bool
default y
config SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER
int
default 3
config SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP
int
default 3
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
bool
default y
config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_MPI_MEM_BLOCKS_NUM
int
default 4

18
components/soc/esp32c5/mp/include/soc/clk_tree_defs.h
View File

@@ -276,10 +276,14 @@ typedef enum { // TODO: [ESP32C5] IDF-8633 (inherit from C6)
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_mcpwm_timer_clk_src_t;
/**
@@ -290,10 +294,14 @@ typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
typedef enum {
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_mcpwm_capture_clk_src_t;
/**
@@ -304,10 +312,14 @@ typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
/**
* @brief Type of MCPWM carrier clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8709 (inherit from C6)
typedef enum {
MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
#else
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#endif
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////

6
components/soc/esp32c5/mp/include/soc/mcpwm_reg.h
View File

@@ -2764,7 +2764,7 @@ extern "C" {
#define MCPWM_CAP0_MODE_V 0x00000003U
#define MCPWM_CAP0_MODE_S 1
/** MCPWM_CAP0_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Configures prescale value on possitive edge of CAP0. Prescale value =
* Configures prescale value on positive edge of CAP0. Prescale value =
* PWM_CAP0_PRESCALE + 1
*/
#define MCPWM_CAP0_PRESCALE 0x000000FFU
@@ -2809,7 +2809,7 @@ extern "C" {
#define MCPWM_CAP1_MODE_V 0x00000003U
#define MCPWM_CAP1_MODE_S 1
/** MCPWM_CAP1_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Configures prescale value on possitive edge of CAP1. Prescale value =
* Configures prescale value on positive edge of CAP1. Prescale value =
* PWM_CAP1_PRESCALE + 1
*/
#define MCPWM_CAP1_PRESCALE 0x000000FFU
@@ -2854,7 +2854,7 @@ extern "C" {
#define MCPWM_CAP2_MODE_V 0x00000003U
#define MCPWM_CAP2_MODE_S 1
/** MCPWM_CAP2_PRESCALE : R/W; bitpos: [10:3]; default: 0;
* Configures prescale value on possitive edge of CAP2. Prescale value =
* Configures prescale value on positive edge of CAP2. Prescale value =
* PWM_CAP2_PRESCALE + 1
*/
#define MCPWM_CAP2_PRESCALE 0x000000FFU

267
components/soc/esp32c5/mp/include/soc/mcpwm_struct.h
View File

@@ -210,33 +210,19 @@ typedef union {
uint32_t val;
} mcpwm_genn_stmp_cfg_reg_t;
/** Type of genn_tstmp_a register
* Generatorn time stamp A's shadow register
/** Type of genn_tstmp register
* Generatorn time stamp shadow register
*/
typedef union {
struct {
/** cmprn_a : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp A's shadow register.
/** cmprn : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp shadow register.
*/
uint32_t cmprn_a:16;
uint32_t cmprn:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_genn_tstmp_a_reg_t;
/** Type of genn_tstmp_b register
* Generatorn time stamp B's shadow register
*/
typedef union {
struct {
/** cmprn_b : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp B's shadow register.
*/
uint32_t cmprn_b:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_genn_tstmp_b_reg_t;
} mcpwm_genn_tstmp_reg_t;
/** Type of genn_cfg0 register
* Generatorn fault event T0 and T1 configuration register
@@ -314,145 +300,75 @@ typedef union {
uint32_t val;
} mcpwm_genn_force_reg_t;
/** Type of genn_a register
/** Type of genn register
* PWMn output signal A actions configuration register
*/
typedef union {
struct {
/** genn_a_utez : R/W; bitpos: [1:0]; default: 0;
/** genn_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn A triggered by event TEZ when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_utez:2;
/** genn_a_utep : R/W; bitpos: [3:2]; default: 0;
uint32_t genn_utez:2;
/** genn_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn A triggered by event TEP when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_utep:2;
/** genn_a_utea : R/W; bitpos: [5:4]; default: 0;
uint32_t genn_utep:2;
/** genn_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn A triggered by event TEA when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_utea:2;
/** genn_a_uteb : R/W; bitpos: [7:6]; default: 0;
uint32_t genn_utea:2;
/** genn_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn A triggered by event TEB when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_uteb:2;
/** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0;
uint32_t genn_uteb:2;
/** genn_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn A triggered by event_t0 when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_ut0:2;
/** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0;
uint32_t genn_ut0:2;
/** genn_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn A triggered by event_t1 when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_ut1:2;
/** genn_a_dtez : R/W; bitpos: [13:12]; default: 0;
uint32_t genn_ut1:2;
/** genn_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn A triggered by event TEZ when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dtez:2;
/** genn_a_dtep : R/W; bitpos: [15:14]; default: 0;
uint32_t genn_dtez:2;
/** genn_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn A triggered by event TEP when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dtep:2;
/** genn_a_dtea : R/W; bitpos: [17:16]; default: 0;
uint32_t genn_dtep:2;
/** genn_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn A triggered by event TEA when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dtea:2;
/** genn_a_dteb : R/W; bitpos: [19:18]; default: 0;
uint32_t genn_dtea:2;
/** genn_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn A triggered by event TEB when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dteb:2;
/** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0;
uint32_t genn_dteb:2;
/** genn_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn A triggered by event_t0 when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dt0:2;
/** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0;
uint32_t genn_dt0:2;
/** genn_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn A triggered by event_t1 when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_a_dt1:2;
uint32_t genn_dt1:2;
uint32_t reserved_24:8;
};
uint32_t val;
} mcpwm_genn_a_reg_t;
/** Type of genn_b register
* PWMn output signal B actions configuration register
*/
typedef union {
struct {
/** genn_b_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn B triggered by event TEZ when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_utez:2;
/** genn_b_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn B triggered by event TEP when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_utep:2;
/** genn_b_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn B triggered by event TEA when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_utea:2;
/** genn_b_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn B triggered by event TEB when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_uteb:2;
/** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn B triggered by event_t0 when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_ut0:2;
/** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn B triggered by event_t1 when timer increasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_ut1:2;
/** genn_b_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn B triggered by event TEZ when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dtez:2;
/** genn_b_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn B triggered by event TEP when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dtep:2;
/** genn_b_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn B triggered by event TEA when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dtea:2;
/** genn_b_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn B triggered by event TEB when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dteb:2;
/** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn B triggered by event_t0 when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dt0:2;
/** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn B triggered by event_t1 when timer decreasing.\\0: No
* change\\1: Low\\2: High\\3: Toggle
*/
uint32_t genn_b_dt1:2;
uint32_t reserved_24:8;
};
uint32_t val;
} mcpwm_genn_b_reg_t;
} mcpwm_genn_reg_t;
/** Type of dtn_cfg register
* Dead time configuration register
@@ -810,7 +726,7 @@ typedef union {
*/
uint32_t capn_mode:2;
/** capn_prescale : R/W; bitpos: [10:3]; default: 0;
* Configures prescale value on possitive edge of CAPn. Prescale value =
* Configures prescale value on positive edge of CAPn. Prescale value =
* PWM_CAPn_PRESCALE + 1
*/
uint32_t capn_prescale:8;
@@ -1191,33 +1107,19 @@ typedef union {
uint32_t val;
} mcpwm_evt_en2_reg_t;
/** Type of opn_tstmp_e1 register
* Generatorn timer stamp E1 value register
/** Type of opn_tstmp register
* Generatorn timer stamp value register
*/
typedef union {
struct {
/** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
/** opn_tstmp_e : R/W; bitpos: [15:0]; default: 0;
* Configures generatorn timer stamp E1 value register
*/
uint32_t opn_tstmp_e1:16;
uint32_t opn_tstmp_e:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_opn_tstmp_e1_reg_t;
/** Type of opn_tstmp_e2 register
* Generatorn timer stamp E2 value register
*/
typedef union {
struct {
/** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0;
* Configures generatorn timer stamp E2 value register
*/
uint32_t opn_tstmp_e2:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_opn_tstmp_e2_reg_t;
} mcpwm_opn_tstmp_reg_t;
/** Type of clk register
* Global configuration register
@@ -1234,7 +1136,6 @@ typedef union {
uint32_t val;
} mcpwm_clk_reg_t;
/** Group: Status register */
/** Type of timern_status register
* PWM timern status register.
@@ -1309,7 +1210,6 @@ typedef union {
uint32_t val;
} mcpwm_cap_status_reg_t;
/** Group: Interrupt register */
/** Type of int_ena register
* Interrupt enable register
@@ -1903,7 +1803,6 @@ typedef union {
uint32_t val;
} mcpwm_int_clr_reg_t;
/** Group: Version register */
/** Type of version register
* Version register.
@@ -1919,65 +1818,38 @@ typedef union {
uint32_t val;
} mcpwm_version_reg_t;
typedef struct {
volatile mcpwm_timern_cfg0_reg_t timer_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer_cfg1;
volatile mcpwm_timern_sync_reg_t timer_sync;
volatile mcpwm_timern_status_reg_t timer_status;
} mcpwm_timer_regs_t;
typedef struct {
volatile mcpwm_genn_stmp_cfg_reg_t gen_stmp_cfg;
volatile mcpwm_genn_tstmp_reg_t timestamp[2];
volatile mcpwm_genn_cfg0_reg_t gen_cfg0;
volatile mcpwm_genn_force_reg_t gen_force;
volatile mcpwm_genn_reg_t generator[2];
volatile mcpwm_dtn_cfg_reg_t dt_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh_cfg1;
volatile mcpwm_fhn_status_reg_t fh_status;
} mcpwm_operator_reg_t;
typedef struct {
volatile mcpwm_opn_tstmp_reg_t timestamp[2];
} mcpwm_operator_tstmp_reg_t;
typedef struct mcpwm_dev_t {
volatile mcpwm_clk_cfg_reg_t clk_cfg;
volatile mcpwm_timern_cfg0_reg_t timer0_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer0_cfg1;
volatile mcpwm_timern_sync_reg_t timer0_sync;
volatile mcpwm_timern_status_reg_t timer0_status;
volatile mcpwm_timern_cfg0_reg_t timer1_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer1_cfg1;
volatile mcpwm_timern_sync_reg_t timer1_sync;
volatile mcpwm_timern_status_reg_t timer1_status;
volatile mcpwm_timern_cfg0_reg_t timer2_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer2_cfg1;
volatile mcpwm_timern_sync_reg_t timer2_sync;
volatile mcpwm_timern_status_reg_t timer2_status;
volatile mcpwm_timer_regs_t timer[3];
volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
volatile mcpwm_operator_timersel_reg_t operator_timersel;
volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen0_cfg0;
volatile mcpwm_genn_force_reg_t gen0_force;
volatile mcpwm_genn_a_reg_t gen0_a;
volatile mcpwm_genn_b_reg_t gen0_b;
volatile mcpwm_dtn_cfg_reg_t dt0_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier0_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1;
volatile mcpwm_fhn_status_reg_t fh0_status;
volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen1_cfg0;
volatile mcpwm_genn_force_reg_t gen1_force;
volatile mcpwm_genn_a_reg_t gen1_a;
volatile mcpwm_genn_b_reg_t gen1_b;
volatile mcpwm_dtn_cfg_reg_t dt1_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier1_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1;
volatile mcpwm_fhn_status_reg_t fh1_status;
volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen2_cfg0;
volatile mcpwm_genn_force_reg_t gen2_force;
volatile mcpwm_genn_a_reg_t gen2_a;
volatile mcpwm_genn_b_reg_t gen2_b;
volatile mcpwm_dtn_cfg_reg_t dt2_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier2_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1;
volatile mcpwm_fhn_status_reg_t fh2_status;
volatile mcpwm_operator_reg_t operators[3];
volatile mcpwm_fault_detect_reg_t fault_detect;
volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
@@ -1992,17 +1864,12 @@ typedef struct {
volatile mcpwm_evt_en_reg_t evt_en;
volatile mcpwm_task_en_reg_t task_en;
volatile mcpwm_evt_en2_reg_t evt_en2;
volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2;
volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2;
volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2;
volatile mcpwm_operator_tstmp_reg_t operators_timestamp[3];
volatile mcpwm_clk_reg_t clk;
volatile mcpwm_version_reg_t version;
} mcpwm_dev_t;
extern mcpwm_dev_t MCPWM;
extern mcpwm_dev_t MCPWM0;
#ifndef __cplusplus
_Static_assert(sizeof(mcpwm_dev_t) == 0x14c, "Invalid size of mcpwm_dev_t structure");

31
components/soc/esp32c5/mp/include/soc/soc_caps.h
View File

@@ -24,7 +24,7 @@
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
#define SOC_PCNT_SUPPORTED 1
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709
#define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686
@@ -323,19 +323,21 @@
// #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */
/*-------------------------- MCPWM CAPS --------------------------------------*/
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
#define SOC_MCPWM_GROUPS 1U ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define SOC_MCPWM_TIMERS_PER_GROUP 3 ///< The number of timers that each group has
#define SOC_MCPWM_OPERATORS_PER_GROUP 3 ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR 2 ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR 2 ///< The number of generators that each operator has
#define SOC_MCPWM_EVENT_COMPARATORS_PER_OPERATOR 2 ///< The number of event comparators that each operator has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR 2 ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP 3 ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP 1 ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER 3 ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP 3 ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1 ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM 1 ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR 1 ///< Support event comparator (based on ETM)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP 1 ///< Capture timer shares clock with other PWM timers
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
@@ -530,7 +532,6 @@
/* macro redefine for pass esp_wifi headers md5sum check */
// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
// #define SOC_PM_CPU_RETENTION_BY_SW (1)

2
components/soc/esp32c5/mp/ld/esp32c5.peripherals.ld
View File

@@ -25,7 +25,7 @@ PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
PROVIDE ( INTMTX = 0x60010000 );
PROVIDE ( PCNT = 0x60012000 );
PROVIDE ( SOC_ETM = 0x60013000 );
PROVIDE ( MCPWM = 0x60014000 );
PROVIDE ( MCPWM0 = 0x60014000 );
PROVIDE ( PARL_IO = 0x60015000 );
PROVIDE ( PVT_MONITOR = 0x60019000 );
PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 );

83
components/soc/esp32c5/mp/mcpwm_periph.c Normal file
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@@ -0,0 +1,83 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/mcpwm_periph.h"
#include "soc/gpio_sig_map.h"
const mcpwm_signal_conn_t mcpwm_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_MCPWM0_MODULE,
.irq_id = ETS_MCPWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
}
}
};