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Merge branch 'docs/core_docs_new_targets' into 'master'

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docs(core): updated core docs for new targets

Closes IDF-10159, IDF-10162, IDF-10171, IDF-12148, IDF-12150, IDF-12151, IDF-12152, IDF-12156, and IDF-12157

See merge request espressif/esp-idf!37860
This commit is contained in:
Marius Vikhammer
2025-03-20 19:56:18 +08:00
parent a57680c6db 034f677563
commit a89fc6d905
34 changed files with 256 additions and 383 deletions
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2
docs/en/api-reference/system/freertos.rst
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@@ -24,7 +24,7 @@ ESP-IDF FreeRTOS is a FreeRTOS implementation based on Vanilla FreeRTOS v10.5.1,
ESP-IDF FreeRTOS is currently the default FreeRTOS implementation for ESP-IDF.
.. only:: not esp32p4
.. only:: not esp32p4 and not esp32h4
.. _amazon_smp_freertos:

2
docs/en/api-reference/system/freertos_idf.rst
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@@ -47,7 +47,7 @@ Although an SMP system allows threads to switch cores, there are scenarios where
SMP on an ESP Target
^^^^^^^^^^^^^^^^^^^^
ESP targets such as ESP32, ESP32-S3, and ESP32-P4 are dual-core SMP SoCs. These targets have the following hardware features that make them SMP-capable:
ESP targets such as ESP32, ESP32-S3, ESP32-P4 and ESP32-H4 are dual-core SMP SoCs. These targets have the following hardware features that make them SMP-capable:
- Two identical cores are known as Core 0 and Core 1. This means that the execution of a piece of code is identical regardless of which core it runs on.
- Symmetric memory (with some small exceptions).

12
docs/en/api-reference/system/inc/revisions_ESP32-C2.rst
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@@ -1,12 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)
* - ECO0
- v0.0
* - ECO1
- v1.0

16
docs/en/api-reference/system/inc/revisions_ESP32-C3.rst
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@@ -1,16 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)
* - ECO1
- v0.1
* - ECO2
- v0.2
* - ECO3
- v0.3
* - ECO4
- v0.4

10
docs/en/api-reference/system/inc/revisions_ESP32-C5.rst
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@@ -1,10 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)
* - ECO0
- v0.0

12
docs/en/api-reference/system/inc/revisions_ESP32-C6.rst
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@@ -1,12 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)
* - ECO0
- v0.0
* - ECO1
- v0.1

14
docs/en/api-reference/system/inc/revisions_ESP32-H2.rst
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@@ -1,14 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)
* - ECO0
- v0.0
* - ECO1
- v0.1
* - ECO2
- v0.2

8
docs/en/api-reference/system/inc/revisions_ESP32-H21.rst
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@@ -1,8 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)

10
docs/en/api-reference/system/inc/revisions_ESP32-P4.rst
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@@ -1,10 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)
* - ECO0
- v0.0

12
docs/en/api-reference/system/inc/revisions_ESP32-S2.rst
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@@ -1,12 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)
* - ECO0
- v0.0
* - ECO1
- v1.0

14
docs/en/api-reference/system/inc/revisions_ESP32-S3.rst
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@@ -1,14 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)
* - ECO0
- v0.0
* - ECO1
- v0.1
* - ECO2
- v0.2

20
docs/en/api-reference/system/inc/revisions_ESP32.rst
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@@ -1,20 +0,0 @@
.. list-table::
:header-rows: 1
:width: 2 5
:align: center
* - ECO
- Revision (Major.Minor)
* - ECO0
- v0.0
* - ECO1
- v1.0
* - ECO1.1
- v1.1
* - ECO2
- v2.0
* - ECO3
- v3.0
* - ECO4
- v3.1

6
docs/en/api-reference/system/intr_alloc.rst
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@@ -22,7 +22,7 @@ Overview
The {IDF_TARGET_NAME} has one core, with 28 external asynchronous interrupts. Each interrupt's priority is independently programmable. In addition, there are also 4 core local interrupt sources (CLINT). See **{IDF_TARGET_NAME} Technical Reference Manual** [`PDF <{IDF_TARGET_TRM_EN_URL}#riscvcpu>`__] for more details.
.. only:: esp32p4
.. only:: esp32p4 or esp32h4
The {IDF_TARGET_NAME} has two cores, with 32 external asynchronous interrupts each. Each interrupt's priority is independently programmable. In addition, there are also 3 core local interrupt sources (CLINT) on each core. See **{IDF_TARGET_NAME} Technical Reference Manual** [`PDF <{IDF_TARGET_TRM_EN_URL}#riscvcpu>`__] for more details.
@@ -41,7 +41,7 @@ Non-shared interrupts can be either level- or edge-triggered. Shared interrupts
To illustrate why shared interrupts can only be level-triggered, take the scenario where peripheral A and peripheral B share the same edge-triggered interrupt. Peripheral B triggers an interrupt and sets its interrupt signal high, causing a low-to-high edge, which in turn latches the CPU's interrupt bit and triggers the ISR. The ISR executes, checks that peripheral A did not trigger an interrupt, and proceeds to handle and clear peripheral B's interrupt signal. Before the ISR returns, the CPU clears its interrupt bit latch. Thus, during the entire interrupt handling process, if peripheral A triggers an interrupt, it will be missed due the CPU clearing the interrupt bit latch.
.. only:: esp32 or esp32s3
.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES and CONFIG_IDF_TARGET_ARCH_XTENSA
Multicore Issues
----------------
@@ -71,7 +71,7 @@ To illustrate why shared interrupts can only be level-triggered, take the scenar
The remaining interrupt sources are from external peripherals.
.. only:: esp32p4
.. only:: SOC_HP_CPU_HAS_MULTIPLE_CORES and CONFIG_IDF_TARGET_ARCH_RISCV
Multicore Considerations
------------------------

2
docs/en/api-reference/system/misc_system_api.rst
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@@ -4,7 +4,7 @@ Miscellaneous System APIs
:link_to_translation:`zh_CN:[中文]`
{IDF_TARGET_BASE_MAC_BLOCK: default="BLK1", esp32="BLK0"}
{IDF_TARGET_CPU_RESET_DES: default="the CPU is reset", esp32="both CPUs are reset", esp32s3="both CPUs are reset", esp32p4="both CPUs are reset"}
{IDF_TARGET_CPU_RESET_DES: default="the CPU is reset", esp32="both CPUs are reset", esp32s3="both CPUs are reset", esp32p4="both CPUs are reset", esp32h4="both CPUs are reset"}
Software Reset
--------------

15
docs/en/api-reference/system/system_time.rst
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@@ -3,13 +3,6 @@ System Time
:link_to_translation:`zh_CN:[中文]`
{IDF_TARGET_RTC_CLK_FRE:default="Not updated", esp32="150 kHz", esp32s2="90 kHz", esp32s3="136 kHz", esp32c3="136 kHz", esp32c2="136 kHz", esp32c5="136 kHz", esp32c6="136 kHz", esp32h2="136 kHz", esp32p4="136 kHz"}
{IDF_TARGET_INT_OSC_FRE:default="Not updated", esp32="8.5 MHz", esp32s2="8.5 MHz", esp32s3="17.5 MHz", esp32c3="17.5 MHz", esp32c2="17.5 MHz"}
{IDF_TARGET_INT_OSC_FRE_DIVIDED:default="Not updated", esp32="about 33 kHz", esp32s2="about 33 kHz", esp32s3="about 68 kHz", esp32c3="about 68 kHz", esp32c2="about 68 kHz"}
{IDF_TARGET_EXT_CRYSTAL_PIN:default="Not updated", esp32="32K_XP and 32K_XN", esp32s2="XTAL_32K_P and XTAL_32K_N", esp32s3="XTAL_32K_P and XTAL_32K_N", esp32c3="XTAL_32K_P and XTAL_32K_N", esp32c5="XTAL_32K_P and XTAL_32K_N", esp32c6="XTAL_32K_P and XTAL_32K_N", esp32h2="XTAL_32K_P and XTAL_32K_N", esp32p4="XTAL_32K_P and XTAL_32K_N"}
{IDF_TARGET_EXT_OSC_PIN:default="Not updated", esp32="32K_XN", esp32s2="XTAL_32K_P", esp32s3="XTAL_32K_P", esp32c3="XTAL_32K_P", esp32c2="GPIO0", esp32c5="XTAL_32K_P", esp32c6="XTAL_32K_P", esp32h2="XTAL_32K_P", esp32p4="XTAL_32K_P"}
Overview
--------
@@ -38,13 +31,13 @@ The RTC timer has the following clock sources:
.. list::
- ``Internal {IDF_TARGET_RTC_CLK_FRE} RC oscillator`` (default): Features the lowest Deep-sleep current consumption and no dependence on any external components. However, the frequency stability of this clock source is affected by temperature fluctuations, so time may drift in both Deep-sleep and Light-sleep modes.
- ``Internal 90-150 kHz (depending on chip) RC oscillator`` (default): Features the lowest Deep-sleep current consumption and no dependence on any external components. However, the frequency stability of this clock source is affected by temperature fluctuations, so time may drift in both Deep-sleep and Light-sleep modes.
:not esp32c2: - ``External 32 kHz crystal``: Requires a 32 kHz crystal to be connected to the {IDF_TARGET_EXT_CRYSTAL_PIN} pins. This source provides a better frequency stability at the expense of a slightly higher (by 1 μA) Deep-sleep current consumption.
:not esp32c2: - ``External 32 kHz crystal``: Requires a 32 kHz crystal to be connected to the external crystal pins. This source provides a better frequency stability at the expense of a slightly higher (by 1 μA) Deep-sleep current consumption. Refer to the `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__ for information on which pins to connect to.
- ``External 32 kHz oscillator at {IDF_TARGET_EXT_OSC_PIN} pin``: Allows using 32 kHz clock generated by an external circuit. The external clock signal must be connected to the {IDF_TARGET_EXT_OSC_PIN} pin. The amplitude should be less than 1.2 V for sine wave signal and less than 1 V for square wave signal. Common mode voltage should be in the range of 0.1 < Vcm < 0.5xVamp, where Vamp stands for signal amplitude. In this case, the {IDF_TARGET_EXT_OSC_PIN} pin cannot be used as a GPIO pin.
- ``External 32 kHz oscillator``: Allows using 32 kHz clock generated by an external circuit. The external clock signal must be connected to the external oscillator pin. The amplitude should be less than 1.2 V for sine wave signal and less than 1 V for square wave signal. Common mode voltage should be in the range of 0.1 < Vcm < 0.5xVamp, where Vamp stands for signal amplitude. Refer to the `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`__ for information on which pin to connect to.
:not esp32c5 and not esp32c6 and not esp32h2 and not esp32p4: - ``Internal {IDF_TARGET_INT_OSC_FRE} oscillator, divided by 256 ({IDF_TARGET_INT_OSC_FRE_DIVIDED})``: Provides better frequency stability than the ``Internal {IDF_TARGET_RTC_CLK_FRE} RC oscillator`` at the expense of a higher (by 5 μA) Deep-sleep current consumption. It also does not require external components.
:esp32 or esp32s2 or esp32s3 or esp32c2 or esp32c3: - ``Internal 8.5-17.5 MHz oscillator (depending on chip), divided by 256``: Provides better frequency stability than the ``Internal 90-150 kHz RC oscillator`` at the expense of a higher (by 5 μA) Deep-sleep current consumption. It also does not require external components.
The choice depends on your requirements for system time accuracy and power consumption in sleep modes. To modify the RTC clock source, set :ref:`CONFIG_RTC_CLK_SRC` in project configuration.