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feat(riscv): implement coprocessors save area and FPU support

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This commit mainly targets the ESP32-P4. It adds supports for coprocessors on
RISC-V based targets. The coprocessor save area, describing the used coprocessors
is stored at the end of the stack of each task (highest address) whereas each
coprocessor save area is allocated at the beginning of the task (lowest address).
The context of each coprocessor is saved lazily, by the task that want to use it.
This commit is contained in:
Omar Chebib
2023-09-06 19:17:24 +08:00
parent b0124b9b9f
commit a8b1475fe7
11 changed files with 707 additions and 92 deletions
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36
components/esp_system/port/arch/riscv/panic_arch.c
View File

@@ -259,11 +259,28 @@ static inline void print_memprot_err_details(const void *frame __attribute__((un
}
#endif
static void panic_print_register_array(const char* names[], const uint32_t* regs, int size)
{
const int regs_per_line = 4;
for (int i = 0; i < size; i++) {
if (i % regs_per_line == 0) {
panic_print_str("\r\n");
}
panic_print_str(names[i]);
panic_print_str(": 0x");
panic_print_hex(regs[i]);
panic_print_str(" ");
}
}
void panic_print_registers(const void *f, int core)
{
uint32_t *regs = (uint32_t *)f;
const RvExcFrame *frame = (RvExcFrame *)f;
// only print ABI name
/**
* General Purpose context, only print ABI name
*/
const char *desc[] = {
"MEPC ", "RA ", "SP ", "GP ", "TP ", "T0 ", "T1 ", "T2 ",
"S0/FP ", "S1 ", "A0 ", "A1 ", "A2 ", "A3 ", "A4 ", "A5 ",
@@ -273,20 +290,9 @@ void panic_print_registers(const void *f, int core)
};
panic_print_str("Core ");
panic_print_dec(((RvExcFrame *)f)->mhartid);
panic_print_dec(frame->mhartid);
panic_print_str(" register dump:");
for (int x = 0; x < sizeof(desc) / sizeof(desc[0]); x += 4) {
panic_print_str("\r\n");
for (int y = 0; y < 4 && x + y < sizeof(desc) / sizeof(desc[0]); y++) {
if (desc[x + y][0] != 0) {
panic_print_str(desc[x + y]);
panic_print_str(": 0x");
panic_print_hex(regs[x + y]);
panic_print_str(" ");
}
}
}
panic_print_register_array(desc, f, DIM(desc));
}
/**

20
components/esp_system/port/cpu_start.c
View File

@@ -191,16 +191,6 @@ void IRAM_ATTR call_start_cpu1(void)
);
#endif //#ifdef __riscv
#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7770
//set mstatus.fs=2'b01, floating-point unit in the initialization state
asm volatile(
"li t0, 0x2000\n"
"csrrs t0, mstatus, t0\n"
:::"t0"
);
#endif //#if CONFIG_IDF_TARGET_ESP32P4
#if SOC_BRANCH_PREDICTOR_SUPPORTED
esp_cpu_branch_prediction_enable();
#endif //#if SOC_BRANCH_PREDICTOR_SUPPORTED
@@ -387,16 +377,6 @@ void IRAM_ATTR call_start_cpu0(void)
);
#endif
#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7770
//set mstatus.fs=2'b01, floating-point unit in the initialization state
asm volatile(
"li t0, 0x2000\n"
"csrrs t0, mstatus, t0\n"
:::"t0"
);
#endif //#if CONFIG_IDF_TARGET_ESP32P4
#if SOC_BRANCH_PREDICTOR_SUPPORTED
esp_cpu_branch_prediction_enable();
#endif