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feat(riscv): implement coprocessors save area and FPU support

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This commit mainly targets the ESP32-P4. It adds supports for coprocessors on
RISC-V based targets. The coprocessor save area, describing the used coprocessors
is stored at the end of the stack of each task (highest address) whereas each
coprocessor save area is allocated at the beginning of the task (lowest address).
The context of each coprocessor is saved lazily, by the task that want to use it.
This commit is contained in:
Omar Chebib
2023-09-06 19:17:24 +08:00
parent b0124b9b9f
commit a8b1475fe7
11 changed files with 707 additions and 92 deletions
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21
components/hal/spi_flash_hal.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -22,26 +22,31 @@ static const char *TAG = "flash_hal";
static uint32_t get_flash_clock_divider(const spi_flash_hal_config_t *cfg)
{
int clk_source = cfg->clock_src_freq;
const int clk_source = cfg->clock_src_freq;
const int clk_freq_mhz = cfg->freq_mhz;
// On ESP32, ESP32-S2, ESP32-C3, we allow specific frequency 26.666MHz
// If user passes freq_mhz like 26 or 27, it's allowed to use integer divider 3.
// However on other chips or on other frequency, we only allow user pass frequency which
// can be integer divided. If no, the following strategy is round up the division and
// round down flash frequency to keep it safe.
int best_div = 0;
if (clk_source < cfg->freq_mhz) {
HAL_LOGE(TAG, "Target frequency %dMHz higher than supported.", cfg->freq_mhz);
if (clk_source < clk_freq_mhz) {
HAL_LOGE(TAG, "Target frequency %dMHz higher than supported.", clk_freq_mhz);
abort();
}
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
if (cfg->freq_mhz == 26 || cfg->freq_mhz == 27) {
if (clk_freq_mhz == 26 || clk_freq_mhz == 27) {
best_div = 3;
} else
#endif
{
best_div = (int)ceil((double)clk_source / (double)cfg->freq_mhz);
if ((cfg->clock_src_freq % cfg->freq_mhz) != 0) {
HAL_LOGW(TAG, "Flash clock frequency round down to %d", (int)floor((double)clk_source / (double)best_div));
/* Do not use float/double as the FPU may not have been initialized yet on startup.
* The values are in MHz, so for sure we won't have an overflow by adding them. */
best_div = (clk_source + clk_freq_mhz - 1) / clk_freq_mhz;
/* Perform a division that returns both quotient and remainder */
const div_t res = div(clk_source, clk_freq_mhz);
if (res.rem != 0) {
HAL_LOGW(TAG, "Flash clock frequency round down to %d", res.quot);
}
}