fix(esp_hw_support): Fix incorrect PMA configuration for ESP32-P4

- As the PMA entry that made some memory regions cacheable was
assigned the highest priority, some intermediate inaccessible
memory regions bypassed protection.

- Added tests for the same

- Verified that even after changing the priority of the PMA entry,
a write operation at SOC_IRAM_LOW + 0x40 (a random RAM cached address)
still needs the same number (29) of CPU cycles.

tools/test_apps/system/panic/main/test_app_main.c

@@ -168,6 +168,10 @@ void app_main(void)
     HANDLE_TEST(test_name, test_drom_reg_execute_violation);
 #endif
 
+#ifdef CONFIG_SOC_CPU_HAS_PMA
+    HANDLE_TEST(test_name, test_invalid_memory_region_write_violation);
+    HANDLE_TEST(test_name, test_invalid_memory_region_execute_violation);
+#endif
 #endif
 
     die("Unknown test name");