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panic: Add support for SoC-level panic

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Activate "invalid access to cache raises panic (PRO CPU)" CI unit
test in order to test SoC-level panics.
This commit is contained in:
Omar Chebib
2020-12-08 17:25:46 +08:00
parent b6a450f824
commit a90dcfba1a
4 changed files with 23 additions and 8 deletions
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components/esp32c3/cache_err_int.c
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@@ -59,7 +59,7 @@ void esp_cache_err_int_init(void)
/* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL);
esprv_intc_int_set_priority(ETS_CACHEERR_INUM, 4);
esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
/* On the hardware side, stat by clearing all the bits reponsible for
* enabling cache access error interrupts. */