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panic: Add support for SoC-level panic

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Activate "invalid access to cache raises panic (PRO CPU)" CI unit
test in order to test SoC-level panics.
This commit is contained in:
Omar Chebib
2020-12-08 17:25:46 +08:00
parent b6a450f824
commit a90dcfba1a
4 changed files with 23 additions and 8 deletions
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4
components/esp_common/src/int_wdt.c
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@@ -126,11 +126,11 @@ void esp_int_wdt_cpu_init(void)
/* Set the type and priority to cache error interrupts, if supported. */
#if SOC_INTERRUPT_TYPE_CAN_SET
interrupt_controller_hal_set_type(BIT(WDT_INT_NUM), INTR_TYPE_LEVEL);
interrupt_controller_hal_set_type(WDT_INT_NUM, INTR_TYPE_LEVEL);
#endif
#if SOC_INTERRUPT_LEVEL_CAN_SET
interrupt_controller_hal_set_level(WDT_INT_NUM, 4);
interrupt_controller_hal_set_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM);
#endif
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX