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panic: Add support for SoC-level panic

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Activate "invalid access to cache raises panic (PRO CPU)" CI unit
test in order to test SoC-level panics.
This commit is contained in:
Omar Chebib
2020-12-08 17:25:46 +08:00
parent b6a450f824
commit a90dcfba1a
4 changed files with 23 additions and 8 deletions
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4
components/riscv/vectors.S
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@@ -122,12 +122,12 @@ _vector_table:
.option push
.option norvc
j _panic_handler /* exception handler, entry 0 */
.rept 23
.rept (ETS_T1_WDT_INUM - 1)
j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */
.endr
j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/
j _panic_handler /* Call panic handler for ETS_CACHEERR_INUM interrupt (soc-level panic)*/
.rept 6
.rept (ETS_MAX_INUM - ETS_CACHEERR_INUM)
j _interrupt_handler /* 6 identical entries, all pointing to the interrupt handler */
.endr