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panic: Add support for SoC-level panic

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Activate "invalid access to cache raises panic (PRO CPU)" CI unit
test in order to test SoC-level panics.
This commit is contained in:
Omar Chebib
2020-12-08 17:25:46 +08:00
parent b6a450f824
commit a90dcfba1a
4 changed files with 23 additions and 8 deletions
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2
components/esp32c3/cache_err_int.c
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@@ -59,7 +59,7 @@ void esp_cache_err_int_init(void)
/* Set the type and priority to cache error interrupts. */ /* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL);
esprv_intc_int_set_priority(ETS_CACHEERR_INUM, 4); esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
/* On the hardware side, stat by clearing all the bits reponsible for /* On the hardware side, stat by clearing all the bits reponsible for
* enabling cache access error interrupts. */ * enabling cache access error interrupts. */

4
components/esp_common/src/int_wdt.c
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@@ -126,11 +126,11 @@ void esp_int_wdt_cpu_init(void)
/* Set the type and priority to cache error interrupts, if supported. */ /* Set the type and priority to cache error interrupts, if supported. */
#if SOC_INTERRUPT_TYPE_CAN_SET #if SOC_INTERRUPT_TYPE_CAN_SET
interrupt_controller_hal_set_type(BIT(WDT_INT_NUM), INTR_TYPE_LEVEL); interrupt_controller_hal_set_type(WDT_INT_NUM, INTR_TYPE_LEVEL);
#endif #endif
#if SOC_INTERRUPT_LEVEL_CAN_SET #if SOC_INTERRUPT_LEVEL_CAN_SET
interrupt_controller_hal_set_level(WDT_INT_NUM, 4); interrupt_controller_hal_set_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM);
#endif #endif
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX

4
components/riscv/vectors.S
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@@ -122,12 +122,12 @@ _vector_table:
.option push .option push
.option norvc .option norvc
j _panic_handler /* exception handler, entry 0 */ j _panic_handler /* exception handler, entry 0 */
.rept 23 .rept (ETS_T1_WDT_INUM - 1)
j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */ j _interrupt_handler /* 24 identical entries, all pointing to the interrupt handler */
.endr .endr
j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/ j _panic_handler /* Call panic handler for ETS_T1_WDT_INUM interrupt (soc-level panic)*/
j _panic_handler /* Call panic handler for ETS_CACHEERR_INUM interrupt (soc-level panic)*/ j _panic_handler /* Call panic handler for ETS_CACHEERR_INUM interrupt (soc-level panic)*/
.rept 6 .rept (ETS_MAX_INUM - ETS_CACHEERR_INUM)
j _interrupt_handler /* 6 identical entries, all pointing to the interrupt handler */ j _interrupt_handler /* 6 identical entries, all pointing to the interrupt handler */
.endr .endr

21
components/spi_flash/test/test_cache_disabled.c
View File

@@ -51,10 +51,19 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash
vQueueDelete(result_queue); vQueueDelete(result_queue);
} }
static const uint32_t s_in_rodata[] = { 0x12345678, 0xfedcba98 }; /**
* On ESP32-C3 boards, constant data with a size less or equal to 8 bytes
* (64 bits) are placed in the DRAM.
* Let's add a third unused element to this array to force it to the DROM.
*/
static const uint32_t s_in_rodata[] = { 0x12345678, 0xfedcba98, 0x42 };
static void IRAM_ATTR cache_access_test_func(void* arg) static void IRAM_ATTR cache_access_test_func(void* arg)
{ {
/* Assert that the array s_in_rodata is in DROM. If not, this test is
* invalid as disabling the cache wouldn't have any effect. */
TEST_ASSERT(esp_ptr_in_drom(s_in_rodata));
spi_flash_disable_interrupts_caches_and_other_cpu(); spi_flash_disable_interrupts_caches_and_other_cpu();
volatile uint32_t* src = (volatile uint32_t*) s_in_rodata; volatile uint32_t* src = (volatile uint32_t*) s_in_rodata;
uint32_t v1 = src[0]; uint32_t v1 = src[0];
@@ -65,9 +74,15 @@ static void IRAM_ATTR cache_access_test_func(void* arg)
vTaskDelete(NULL); vTaskDelete(NULL);
} }
#ifdef CONFIG_IDF_TARGET_ESP32C3
#define CACHE_ERROR_REASON "Cache exception,RTC_SW_CPU_RST"
#else
#define CACHE_ERROR_REASON "Cache disabled,SW_RESET"
#endif
// These tests works properly if they resets the chip with the // These tests works properly if they resets the chip with the
// "Cache disabled but cached memory region accessed" reason and the correct CPU is logged. // "Cache disabled but cached memory region accessed" reason and the correct CPU is logged.
TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][ignore]") TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset="CACHE_ERROR_REASON"]")
{ {
xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0); xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0);
vTaskDelay(1000/portTICK_PERIOD_MS); vTaskDelay(1000/portTICK_PERIOD_MS);
@@ -75,7 +90,7 @@ TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][ignore]
#ifndef CONFIG_FREERTOS_UNICORE #ifndef CONFIG_FREERTOS_UNICORE
TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][ignore]") TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][reset=TG1WDT_SYS_RESET]")
{ {
xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 1); xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 1);
vTaskDelay(1000/portTICK_PERIOD_MS); vTaskDelay(1000/portTICK_PERIOD_MS);