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LEDC: improved support for ESP32-C3 and refactored divisor calculation

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As ESP32C3 does not have support for REF_TICK source clock, it is now not
possible to select it anymore.
Auto cfg clock has been improved for all boards.
This commit is contained in:
Omar Chebib
2021-06-02 20:19:09 +08:00
parent 534cd5bb31
commit aa2ca7dd94
17 changed files with 417 additions and 242 deletions
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233
components/driver/ledc.c
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@@ -63,6 +63,8 @@ static portMUX_TYPE ledc_spinlock = portMUX_INITIALIZER_UNLOCKED;
#define SLOW_CLK_CYC_CALIBRATE (13)
#define LEDC_FADE_TOO_SLOW_STR "LEDC FADE TOO SLOW"
#define LEDC_FADE_TOO_FAST_STR "LEDC FADE TOO FAST"
#define DIM(array) (sizeof(array)/sizeof(*array))
#define LEDC_IS_DIV_INVALID(div) ((div) <= LEDC_LL_FRACTIONAL_MAX || (div) > LEDC_TIMER_DIV_NUM_MAX)
static const char *LEDC_NOT_INIT = "LEDC is not initialized";
static const char *LEDC_FADE_SERVICE_ERR_STR = "LEDC fade service not installed";
@@ -102,10 +104,12 @@ static uint32_t ledc_get_src_clk_freq(ledc_clk_cfg_t clk_cfg)
uint32_t src_clk_freq = 0;
if (clk_cfg == LEDC_USE_APB_CLK) {
src_clk_freq = LEDC_APB_CLK_HZ;
} else if (clk_cfg == LEDC_USE_REF_TICK) {
src_clk_freq = LEDC_REF_CLK_HZ;
} else if (clk_cfg == LEDC_USE_RTC8M_CLK) {
src_clk_freq = s_ledc_slow_clk_8M;
#if SOC_LEDC_SUPPORT_REF_TICK
} else if (clk_cfg == LEDC_USE_REF_TICK) {
src_clk_freq = LEDC_REF_CLK_HZ;
#endif
#if SOC_LEDC_SUPPORT_XTAL_CLOCK
} else if (clk_cfg == LEDC_USE_XTAL_CLK) {
src_clk_freq = rtc_clk_xtal_freq_get() * 1000000;
@@ -175,7 +179,11 @@ esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_
LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
portENTER_CRITICAL(&ledc_spinlock);
ledc_hal_set_clock_divider(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel, clock_divider);
#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
/* Clock source can only be configured on boards which support timer-specific
* source clock. */
ledc_hal_set_clock_source(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel, clk_src);
#endif
ledc_hal_set_duty_resolution(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel, duty_resolution);
ledc_ls_timer_update(speed_mode, timer_sel);
portEXIT_CRITICAL(&ledc_spinlock);
@@ -259,52 +267,211 @@ esp_err_t ledc_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags,
return ret;
}
// Setting the LEDC timer divisor with the given source clock, frequency and resolution.
static inline uint32_t ledc_calculate_divisor(uint32_t src_clk_freq, int freq_hz, uint32_t precision)
{
/**
* In order to find the right divisor, we need to divide the source clock
* frequency by the desired frequency. However, two things to note here:
* - The lowest LEDC_LL_FRACTIONAL_BITS bits of the result are the FRACTIONAL
* part. The higher bits represent the integer part, this is why we need
* to right shift the source frequency.
* - The `precision` parameter represents the granularity of the clock. It
* **must** be a power of 2. It means that the resulted divisor is
* a multiplier of `precision`.
*
* Let's take a concrete example, we need to generate a 5KHz clock out of
* a 80MHz clock (APB).
* If the precision is 1024 (10 bits), the resulted multiplier is:
* (80000000 << 8) / (5000 * 1024) = 4000 (0xfa0)
* Let's ignore the fractional part to simplify the exaplanation, so we get
* a result of 15 (0xf).
* This can be interpreted as: every 15 "precision" ticks, the resulted
* clock will go high, where one precision tick is made out of 1024 source
* clock ticks.
* Thus, every `15 * 1024` source clock ticks, the resulted clock will go
* high. */
return ( (uint64_t) src_clk_freq << LEDC_LL_FRACTIONAL_BITS ) / (freq_hz * precision);
}
static inline uint32_t ledc_auto_global_clk_divisor(int freq_hz, uint32_t precision, ledc_clk_cfg_t* clk_target)
{
uint32_t div_param = 0;
uint32_t i = 0;
uint32_t clk_freq = 0;
/* This function will go through all the following clock sources to look
* for a valid divisor which generates the requested frequency. */
const ledc_clk_cfg_t glb_clks[] = LEDC_LL_GLOBAL_CLOCKS;
for (i = 0; i < DIM(glb_clks); i++) {
/* Before calculating the divisor, we need to have the RTC frequency.
* If it hasn't been mesured yet, try calibrating it now. */
if (glb_clks[i] == LEDC_SLOW_CLK_RTC8M && s_ledc_slow_clk_8M == 0 && !ledc_slow_clk_calibrate()) {
ESP_LOGD(LEDC_TAG, "Unable to retrieve RTC clock frequency, skipping it\n");
continue;
}
clk_freq = ledc_get_src_clk_freq(glb_clks[i]);
div_param = ledc_calculate_divisor(clk_freq, freq_hz, precision);
/* If the divisor is valid, we can return this value. */
if (!LEDC_IS_DIV_INVALID(div_param)) {
*clk_target = glb_clks[i];
break;
}
}
return div_param;
}
#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
static inline uint32_t ledc_auto_timer_specific_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint32_t precision,
ledc_clk_src_t* clk_source)
{
uint32_t div_param = 0;
uint32_t i = 0;
/* Use an anonymous structure, only this function requires it.
* Get the list of the timer-specific clocks, try to find one for the reuested frequency. */
const struct { ledc_clk_src_t clk; uint32_t freq; } specific_clks[] = LEDC_LL_TIMER_SPECIFIC_CLOCKS;
for (i = 0; i < DIM(specific_clks); i++) {
div_param = ledc_calculate_divisor(specific_clks[i].freq, freq_hz, precision);
/* If the divisor is valid, we can return this value. */
if (!LEDC_IS_DIV_INVALID(div_param)) {
*clk_source = specific_clks[i].clk;
break;
}
}
#if SOC_LEDC_SUPPORT_HS_MODE
/* On board that support LEDC high-speed mode, APB clock becomes a timer-
* specific clock when in high speed mode. Check if it is necessary here
* to test APB. */
if (speed_mode == LEDC_HIGH_SPEED_MODE && i == DIM(specific_clks)) {
/* No divider was found yet, try with APB! */
div_param = ledc_calculate_divisor(LEDC_APB_CLK_HZ, freq_hz, precision);
if (!LEDC_IS_DIV_INVALID(div_param)) {
*clk_source = LEDC_APB_CLK;
}
}
#endif
return div_param;
}
#endif
/**
* @brief Try to find the clock with its divisor giving the frequency requested
* by the caller.
*/
static uint32_t ledc_auto_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint32_t precision,
ledc_clk_src_t* clk_source, ledc_clk_cfg_t* clk_target)
{
uint32_t div_param = 0;
#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
/* If the SoC presents timer-specific clock(s), try to achieve the given frequency
* thanks to it/them.
* clk_source parameter will returned by this function. */
div_param = ledc_auto_timer_specific_clk_divisor(speed_mode, freq_hz, precision, clk_source);
if (!LEDC_IS_DIV_INVALID(div_param)) {
/* The dividor is valid, no need try any other clock, return directly. */
return div_param;
}
#endif
/* On ESP32, only low speed channel can use the global clocks. For other
* chips, there are no high speed channels. */
if (speed_mode == LEDC_LOW_SPEED_MODE) {
div_param = ledc_auto_global_clk_divisor(freq_hz, precision, clk_target);
}
return div_param;
}
/**
* @brief Function setting the LEDC timer divisor with the given source clock,
* frequency and resolution. If the clock configuration passed is
* LEDC_AUTO_CLK, the clock will be determined automatically (if possible).
*/
static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_num, ledc_clk_cfg_t clk_cfg, int freq_hz, int duty_resolution)
{
uint32_t div_param = 0;
uint32_t precision = ( 0x1 << duty_resolution );
ledc_clk_src_t timer_clk_src = LEDC_APB_CLK;
// Calculate the divisor
// User specified source clock(RTC8M_CLK) for low speed channel
if ((speed_mode == LEDC_LOW_SPEED_MODE) && (clk_cfg == LEDC_USE_RTC8M_CLK)) {
if (s_ledc_slow_clk_8M == 0) {
if (ledc_slow_clk_calibrate() == false) {
goto error;
}
const uint32_t precision = ( 0x1 << duty_resolution );
/* This variable represents the timer's mux value. It will be overwritten
* if a timer-specific clock is used. */
ledc_clk_src_t timer_clk_src = LEDC_SCLK;
uint32_t src_clk_freq = 0;
if (clk_cfg == LEDC_AUTO_CLK) {
/* User hasn't specified the speed, we should try to guess it. */
div_param = ledc_auto_clk_divisor(speed_mode, freq_hz, precision, &timer_clk_src, &clk_cfg);
} else if (clk_cfg == LEDC_USE_RTC8M_CLK) {
/* User specified source clock(RTC8M_CLK) for low speed channel.
* Make sure the speed mode is correct. */
ESP_RETURN_ON_FALSE((speed_mode == LEDC_LOW_SPEED_MODE), ESP_ERR_INVALID_ARG, LEDC_TAG, "RTC clock can only be used in low speed mode");
/* Before calculating the divisor, we need to have the RTC frequency.
* If it hasn't been mesured yet, try calibrating it now. */
if(s_ledc_slow_clk_8M == 0 && ledc_slow_clk_calibrate() == false) {
goto error;
}
div_param = ( (uint64_t) s_ledc_slow_clk_8M << 8 ) / freq_hz / precision;
/* We have the RTC clock frequency now. */
div_param = ledc_calculate_divisor(s_ledc_slow_clk_8M, freq_hz, precision);
} else {
// Automatically select APB or REF_TICK as the source clock.
if (clk_cfg == LEDC_AUTO_CLK) {
// Try calculating divisor based on LEDC_APB_CLK
div_param = ( (uint64_t) LEDC_APB_CLK_HZ << 8 ) / freq_hz / precision;
if (div_param > LEDC_TIMER_DIV_NUM_MAX) {
// APB_CLK results in divisor which too high. Try using REF_TICK as clock source.
timer_clk_src = LEDC_REF_TICK;
div_param = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision;
} else if (div_param < 256) {
// divisor is too low
goto error;
}
// User specified source clock(LEDC_APB_CLK_HZ or LEDC_REF_TICK)
} else {
timer_clk_src = (clk_cfg == LEDC_USE_REF_TICK) ? LEDC_REF_TICK : LEDC_APB_CLK;
uint32_t src_clk_freq = ledc_get_src_clk_freq(clk_cfg);
div_param = ( (uint64_t) src_clk_freq << 8 ) / freq_hz / precision;
#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
if (LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(speed_mode, clk_cfg)) {
/* Currently we can convert a timer specific clock to a source clock that
* easily because their values are identical in the enumerations (on purpose)
* If we decide to change the values in the future, we should consider defining
* a macro/function to convert timer-specific clock to clock source .*/
timer_clk_src = (ledc_clk_src_t) clk_cfg;
}
#endif
src_clk_freq = ledc_get_src_clk_freq(clk_cfg);
div_param = ledc_calculate_divisor(src_clk_freq, freq_hz, precision);
}
if (div_param < 256 || div_param > LEDC_TIMER_DIV_NUM_MAX) {
if (LEDC_IS_DIV_INVALID(div_param)) {
goto error;
}
/* The following debug message makes more sense for AUTO mode. */
ESP_LOGD(LEDC_TAG, "Using clock source %d (in %s mode), divisor: 0x%x\n",
timer_clk_src, (speed_mode == LEDC_LOW_SPEED_MODE ? "slow" : "fast"), div_param);
/* The following block configures the global clock.
* Thus, in theory, this only makes sense when the source clock is LEDC_SCLK
* and in LOW_SPEED_MODE (as FAST_SPEED_MODE doesn't present any global clock)
*
* However, in practice, on modules that support high-speed mode, no matter
* whether the source clock is a timer-specific one (e.g. REF_TICK) or not,
* the global clock MUST be configured when in low speed mode.
* When using high-speed mode, this is not necessary.
*/
#if SOC_LEDC_SUPPORT_HS_MODE
if (speed_mode == LEDC_LOW_SPEED_MODE) {
#else
if (timer_clk_src == LEDC_SCLK) {
#endif
ESP_LOGD(LEDC_TAG, "In slow speed mode, using clock %d", clk_cfg);
portENTER_CRITICAL(&ledc_spinlock);
ledc_hal_set_slow_clk(&(p_ledc_obj[speed_mode]->ledc_hal), clk_cfg);
portEXIT_CRITICAL(&ledc_spinlock);
}
//Set the divisor
/* The divisor is correct, we can write in the hardware. */
ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src);
// reset the timer
/* Reset the timer. */
ledc_timer_rst(speed_mode, timer_num);
return ESP_OK;
error: