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feat(lp-core): bringup lp-core for C5 MP

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LP-Core is now able to boot and run on C5 MP chip.
This commit is contained in:
Marius Vikhammer
2024-06-14 17:39:57 +08:00
parent 0479494e7a
commit aae3aa5e5f
15 changed files with 113 additions and 27 deletions
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21
components/hal/esp32c5/include/hal/rtc_io_ll.h
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@@ -44,6 +44,15 @@ typedef enum {
RTCIO_LL_OUTPUT_OD = 0x1, /*!< RTCIO output mode is open-drain. */
} rtcio_ll_out_mode_t;
typedef enum {
RTCIO_INTR_DISABLE = 0, /*!< Disable GPIO interrupt */
RTCIO_INTR_POSEDGE = 1, /*!< GPIO interrupt type : rising edge */
RTCIO_INTR_NEGEDGE = 2, /*!< GPIO interrupt type : falling edge */
RTCIO_INTR_ANYEDGE = 3, /*!< GPIO interrupt type : both rising and falling edge */
RTCIO_INTR_LOW_LEVEL = 4, /*!< GPIO interrupt type : input low level trigger */
RTCIO_INTR_HIGH_LEVEL = 5, /*!< GPIO interrupt type : input high level trigger */
} rtcio_ll_intr_type_t;
/**
* @brief Select a RTC IOMUX function for the RTC IO
*
@@ -451,6 +460,18 @@ static inline void rtcio_ll_clear_interrupt_status(void)
abort();
}
/**
* Enable interrupt function and set interrupt type
*
* @param rtcio_num The index of rtcio. 0 ~ MAX(rtcio).
* @param type Interrupt type on high level or low level.
*/
static inline void rtcio_ll_intr_enable(int rtcio_num, rtcio_ll_intr_type_t type)
{
// TODO: [ESP32C5] IDF-8719
//LP_GPIO.pin[rtcio_num].int_type = type;
}
#ifdef __cplusplus
}
#endif