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feat(lp-core): bringup lp-core for C5 MP

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LP-Core is now able to boot and run on C5 MP chip.
This commit is contained in:
Marius Vikhammer
2024-06-14 17:39:57 +08:00
parent 0479494e7a
commit aae3aa5e5f
15 changed files with 113 additions and 27 deletions
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12
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -35,6 +35,14 @@ config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y
config SOC_LP_CORE_SUPPORTED
bool
default y
config SOC_ULP_SUPPORTED
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@@ -774,3 +782,7 @@ config SOC_CLK_RC32K_SUPPORTED
config SOC_RCC_IS_INDEPENDENT
bool
default y
config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR
bool
default y

16
components/soc/esp32c5/include/soc/pmu_struct.h
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@@ -376,6 +376,16 @@ typedef union {
uint32_t val;
} pmu_power_wait_timer1_reg_t;
typedef union {
struct {
uint32_t reserved0 : 9;
uint32_t powerdown_timer: 7;
uint32_t powerup_timer : 7;
uint32_t wait_timer : 9;
};
uint32_t val;
} pmu_power_wait_timer2_reg_t;
typedef union {
struct {
uint32_t force_reset : 1;
@@ -445,6 +455,7 @@ typedef union {
typedef struct pmu_power_hw_regmap_t{
pmu_power_wait_timer0_reg_t wait_timer0;
pmu_power_wait_timer1_reg_t wait_timer1;
pmu_power_wait_timer2_reg_t wait_timer2;
pmu_power_domain_cntl_reg_t hp_pd[5];
pmu_power_domain_cntl_reg_t lp_peri;
pmu_power_memory_cntl_reg_t mem_cntl;
@@ -731,8 +742,6 @@ typedef struct pmu_dev_t{
volatile uint32_t val;
} vdd_spi_status;
uint32_t reserved[150];
union {
struct {
volatile uint32_t pmu_date: 31;
@@ -745,9 +754,8 @@ typedef struct pmu_dev_t{
extern pmu_dev_t PMU;
#ifndef __cplusplus
_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
//_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
//_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); TODO IDF-8643
#endif

6
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -33,7 +33,8 @@
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727
// #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851
#define SOC_SUPPORTS_SECURE_DL_MODE 1
// #define SOC_LP_CORE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8637
#define SOC_LP_CORE_SUPPORTED 1
#define SOC_ULP_SUPPORTED 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_EFUSE_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
@@ -579,3 +580,6 @@
/*------------------------------------- PHY CAPS -------------------------------------*/
// #define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/
/*------------------------------------- ULP CAPS -------------------------------------*/
#define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR (1) /*!< LP Core interrupts all map to a single entry in vector table */