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Merge branch 'bugfix/ulp_riscv_cocpu_trap_v4.3' into 'release/v4.3'

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ulp riscv: force cocpu clock on to prevent spurious cocpu trap resets (v4.3)

See merge request espressif/esp-idf!14317
This commit is contained in:
Marius Vikhammer
2021-09-08 08:59:42 +00:00
parent 0f7dd04a83 b667770cc6
commit ab111b7f79
1 changed files with 7 additions and 2 deletions
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9
components/ulp/ulp_riscv.c
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@@ -32,12 +32,16 @@
esp_err_t ulp_riscv_run(void)
{
/* Reset COCPU when power on. */
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
/* The coprocessor cpu trap signal doesnt have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
esp_rom_delay_us(20);
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
/* Disable ULP timer */
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
/* wait for at least 1 RTC_SLOW_CLK cycle */
@@ -55,6 +59,7 @@ esp_err_t ulp_riscv_run(void)
return ESP_OK;
}
esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes)
{
if (program_binary == NULL) {