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feat(clk): support ESP32C5 XTAL 40M/48M selection

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This commit is contained in:
Song Ruo Jing
2024-06-07 21:29:44 +08:00
parent 469c51bf2b
commit ac6101bf4e
29 changed files with 270 additions and 99 deletions
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13
components/hal/esp32c5/clk_tree_hal.c
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@@ -10,8 +10,11 @@
#include "hal/clk_tree_ll.h"
#include "hal/gpio_ll.h"
#include "hal/log.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
static const char *CLK_HAL_TAG = "clk_hal";
#endif
uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
{
@@ -85,12 +88,18 @@ uint32_t clk_hal_lp_slow_get_freq_hz(void)
uint32_t clk_hal_xtal_get_freq_mhz(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t freq = clk_ll_xtal_load_freq_mhz();
if (freq == 0) {
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
return (uint32_t)SOC_XTAL_FREQ_40M;
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 48MHz");
return (uint32_t)SOC_XTAL_FREQ_48M;
}
return freq;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t freq = clk_ll_xtal_get_freq_mhz();
HAL_ASSERT(freq == SOC_XTAL_FREQ_48M || freq == SOC_XTAL_FREQ_40M);
return freq;
#endif
}
void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)

16
components/hal/esp32c5/include/hal/clk_tree_ll.h
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@@ -266,6 +266,20 @@ static inline __attribute__((always_inline)) bool clk_ll_rc32k_digi_is_enabled(v
return LP_CLKRST.clk_to_hp.icg_hp_osc32k;
}
#if !CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief Get XTAL_CLK frequency
*
* PCR_CLK_XTAL_FREQ updates its value based on EFUSE_XTAL_48M_SEL.
*
* @return Main XTAL clock frequency, in MHz.
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_get_freq_mhz(void)
{
return PCR.sysclk_conf.clk_xtal_freq;
}
#endif
/**
* @brief Get PLL_CLK frequency
*
@@ -910,6 +924,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uin
}
/************************** LP STORAGE REGISTER STORE/LOAD **************************/
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* @brief Store XTAL_CLK frequency in RTC storage register
*
@@ -950,6 +965,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
// If the format in reg is invalid
return 0;
}
#endif
/**
* @brief Store RTC_SLOW_CLK calibration value in RTC storage register

4
components/hal/esp32c5/include/hal/i2s_ll.h
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@@ -35,8 +35,8 @@ extern "C" {
#define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
#define I2S_LL_XTAL_CLK_FREQ (CONFIG_XTAL_FREQ * 1000000) // XTAL_CLK: 40MHz or 48MHz
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_XTAL_CLK_FREQ // No PLL clock source on P4, use XTAL as default
#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
/**
* @brief Enable the bus clock for I2S module