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feat(clk): support ESP32C5 XTAL 40M/48M selection

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This commit is contained in:
Song Ruo Jing
2024-06-07 21:29:44 +08:00
parent 469c51bf2b
commit ac6101bf4e
29 changed files with 270 additions and 99 deletions
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13
components/hal/esp32c5/clk_tree_hal.c
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@@ -10,8 +10,11 @@
#include "hal/clk_tree_ll.h"
#include "hal/gpio_ll.h"
#include "hal/log.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
static const char *CLK_HAL_TAG = "clk_hal";
#endif
uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
{
@@ -85,12 +88,18 @@ uint32_t clk_hal_lp_slow_get_freq_hz(void)
uint32_t clk_hal_xtal_get_freq_mhz(void)
{
#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
uint32_t freq = clk_ll_xtal_load_freq_mhz();
if (freq == 0) {
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
return (uint32_t)SOC_XTAL_FREQ_40M;
HAL_LOGW(CLK_HAL_TAG, "invalid RTC_XTAL_FREQ_REG value, assume 48MHz");
return (uint32_t)SOC_XTAL_FREQ_48M;
}
return freq;
#elif CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t freq = clk_ll_xtal_get_freq_mhz();
HAL_ASSERT(freq == SOC_XTAL_FREQ_48M || freq == SOC_XTAL_FREQ_40M);
return freq;
#endif
}
void clk_hal_clock_output_setup(soc_clkout_sig_id_t clk_sig, clock_out_channel_t channel_id)