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feat(clk): support ESP32C5 XTAL 40M/48M selection

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Song Ruo Jing
2024-06-07 21:29:44 +08:00
parent 469c51bf2b
commit ac6101bf4e
29 changed files with 270 additions and 99 deletions
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4
components/hal/esp32c5/include/hal/i2s_ll.h
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@@ -35,8 +35,8 @@ extern "C" {
#define I2S_LL_CLK_FRAC_DIV_N_MAX 256 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the N register is 8 bit-width
#define I2S_LL_CLK_FRAC_DIV_AB_MAX 512 // I2S_MCLK = I2S_SRC_CLK / (N + b/a), the a/b register is 9 bit-width
#define I2S_LL_XTAL_CLK_FREQ (CONFIG_XTAL_FREQ * 1000000) // XTAL_CLK: 40MHz or 48MHz
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_XTAL_CLK_FREQ // No PLL clock source on P4, use XTAL as default
#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
#define I2S_LL_DEFAULT_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
/**
* @brief Enable the bus clock for I2S module