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feat(clk): support ESP32C5 XTAL 40M/48M selection

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This commit is contained in:
Song Ruo Jing
2024-06-07 21:29:44 +08:00
parent 469c51bf2b
commit ac6101bf4e
29 changed files with 270 additions and 99 deletions
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4
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
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@@ -127,6 +127,10 @@ config SOC_XTAL_SUPPORT_48M
bool
default y
config SOC_XTAL_SUPPORT_EFUSE_SEL
bool
default y
config SOC_AES_SUPPORT_DMA
bool
default y

5
components/soc/esp32c5/mp/include/soc/soc.h
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@@ -134,15 +134,10 @@
//}}
//Periheral Clock {{
#define APB_CLK_FREQ_ROM ( 40*1000000 )
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define EFUSE_CLK_FREQ_ROM ( 20*1000000)
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 40*1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
#define REF_CLK_FREQ ( 1000000 )
#define XTAL_CLK_FREQ (40*1000000)
#define GPIO_MATRIX_DELAY_NS 0
//}}

1
components/soc/esp32c5/mp/include/soc/soc_caps.h
View File

@@ -78,6 +78,7 @@
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_40M 1
#define SOC_XTAL_SUPPORT_48M 1
#define SOC_XTAL_SUPPORT_EFUSE_SEL 1 // XTAL freq in runtime determined through EFUSE_XTAL_48M_SEL
/*-------------------------- AES CAPS -----------------------------------------*/
#define SOC_AES_SUPPORT_DMA (1)