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ledc: Add support for esp32h2; Refactor ledc driver clock source selection related code

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LEDC examples and test cases are supported on ESP32H2.
   Switch to use general clock IDs for ledc_clk_cfg_t enum values.
   Deprecate LEDC_USE_RTC8M_CLK.
This commit is contained in:
Song Ruo Jing
2023-01-24 01:54:34 +08:00
parent 375aaf8e7b
commit ad55230b0a
34 changed files with 1078 additions and 336 deletions
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39
docs/en/api-reference/peripherals/ledc.rst
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@@ -85,7 +85,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
- 1 MHz
- High / Low
- Dynamic Frequency Scaling compatible
* - RTC8M_CLK
* - RC_FAST_CLK
- ~8 MHz
- Low
- Dynamic Frequency Scaling compatible, Light sleep compatible
@@ -105,7 +105,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
* - REF_TICK
- 1 MHz
- Dynamic Frequency Scaling compatible
* - RTC8M_CLK
* - RC_FAST_CLK
- ~8 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
* - XTAL_CLK
@@ -124,7 +124,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
* - APB_CLK
- 80 MHz
- /
* - RTC20M_CLK
* - RC_FAST_CLK
- ~20 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
* - XTAL_CLK
@@ -143,7 +143,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
* - PLL_60M_CLK
- 60 MHz
- /
* - RTC20M_CLK
* - RC_FAST_CLK
- ~20 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
* - XTAL_CLK
@@ -162,13 +162,32 @@ The source clock can also limit the PWM frequency. The higher the source clock f
* - PLL_80M_CLK
- 80 MHz
- /
* - RTC20M_CLK
* - RC_FAST_CLK
- ~20 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
* - XTAL_CLK
- 40 MHz
- Dynamic Frequency Scaling compatible
.. only:: esp32h2
.. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks
:widths: 15 15 30
:header-rows: 1
* - Clock name
- Clock freq
- Clock capabilities
* - PLL_96M_CLK
- 96 MHz
- /
* - RC_FAST_CLK
- ~8 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
* - XTAL_CLK
- 32 MHz
- Dynamic Frequency Scaling compatible
.. only:: esp32h4
.. list-table:: Characteristics of {IDF_TARGET_NAME} LEDC source clocks
@@ -181,7 +200,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
* - APB_CLK
- 96 MHz
- /
* - RTC8M_CLK
* - RC_FAST_CLK
- ~8 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
* - XTAL_CLK
@@ -190,13 +209,13 @@ The source clock can also limit the PWM frequency. The higher the source clock f
.. note::
.. only:: not esp32h4
.. only:: SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
1. On {IDF_TARGET_NAME}, if RTCxM_CLK is chosen as the LEDC clock source, an internal calibration will be performed to get the exact frequency of the clock. This ensures the accuracy of output PWM signal frequency.
1. On {IDF_TARGET_NAME}, if RC_FAST_CLK is chosen as the LEDC clock source, an internal calibration will be performed to get the exact frequency of the clock. This ensures the accuracy of output PWM signal frequency.
.. only:: esp32h4
.. only:: not SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
1. On {IDF_TARGET_NAME}, if RTC8M_CLK is chosen as the LEDC clock source, you may see the frequency of output PWM signal is not very accurate. This is because no internal calibration is performed to get the exact frequency of the clock due to hardware limitation, a theoretic frequency value is used.
1. On {IDF_TARGET_NAME}, if RC_FAST_CLK is chosen as the LEDC clock source, you may see the frequency of output PWM signal is not very accurate. This is because no internal calibration is performed to get the exact frequency of the clock due to hardware limitation, a theoretic frequency value is used.
.. only:: not SOC_LEDC_HAS_TIMER_SPECIFIC_MUX