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ci(spi_flash): add tests for cache2phys with XIP

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Xiao Xufeng
2024-05-27 01:45:02 +08:00
parent 23024f795e
commit ad828dcc52
14 changed files with 93 additions and 32 deletions
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51
components/app_update/test_apps/pytest_app_update_ut.py
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@@ -9,24 +9,43 @@ DEFAULT_TIMEOUT = 20
TEST_SUBMENU_PATTERN_PYTEST = re.compile(rb'\s+\((\d+)\)\s+"([^"]+)"\r?\n')
def run_multiple_stages(dut: Dut, test_case_num: int, stages: int) -> None:
for stage in range(1, stages + 1):
dut.write(str(test_case_num))
dut.expect(TEST_SUBMENU_PATTERN_PYTEST, timeout=DEFAULT_TIMEOUT)
dut.write(str(stage))
if stage != stages:
dut.expect_exact('Press ENTER to see the list of tests.')
@pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32c6', 'esp32h2'], reason='c6/h2 support TBD')
@pytest.mark.generic
@pytest.mark.parametrize(
'config',
[
'defaults',
],
indirect=True,
)
def test_app_update(dut: Dut) -> None:
dut.run_all_single_board_cases(timeout=90)
@pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32c6', 'esp32h2'], reason='c6/h2 support TBD')
@pytest.mark.generic
def test_app_update(dut: Dut) -> None:
extra_data = dut.parse_test_menu()
for test_case in extra_data:
if test_case.type != 'multi_stage':
dut.write(str(test_case.index))
else:
run_multiple_stages(dut, test_case.index, len(test_case.subcases))
dut.expect_unity_test_output(timeout=90)
dut.expect_exact("Enter next test, or 'enter' to see menu")
@pytest.mark.parametrize(
'config',
[
'xip_psram',
],
indirect=True,
)
def test_app_update_xip_psram(dut: Dut) -> None:
dut.run_all_single_board_cases(timeout=90)
@pytest.mark.supported_targets
@pytest.mark.temp_skip_ci(targets=['esp32c6', 'esp32h2'], reason='c6/h2 support TBD')
@pytest.mark.generic
@pytest.mark.parametrize(
'config',
[
'xip_psram_with_rom_impl',
],
indirect=True,
)
def test_app_update_xip_psram_rom_impl(dut: Dut) -> None:
dut.run_all_single_board_cases(timeout=90)