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Merge branch 'feature/esp32c61_regi2c_support' into 'master'

Browse Source 
feat(regi2c): support REGI2C for ESP32C61

Closes IDF-9276

See merge request espressif/esp-idf!31980
This commit is contained in:
Song Ruo Jing
2024-07-29 11:52:41 +08:00
parent 23ee0b65ff 71d37f9ea8
commit adb1a81729
43 changed files with 1974 additions and 320 deletions
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25
components/hal/esp32c5/include/hal/modem_lpcon_ll.h
View File

@@ -133,12 +133,6 @@ static inline uint32_t modem_lpcon_ll_get_wifi_lpclk_divisor_value(modem_lpcon_d
return hw->wifi_lp_clk_conf.clk_wifipwr_lp_div_num;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_i2c_master_160m_clock(modem_lpcon_dev_t *hw, bool en)
{
// ESP32C5 Not Support
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_set_modem_pwr_clk_src_fo(modem_lpcon_dev_t *hw, bool value)
{
@@ -169,12 +163,6 @@ static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool
hw->clk_conf.clk_coex_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf.clk_i2c_mst_en = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_ble_rtc_timer_clock(modem_lpcon_dev_t *hw, bool en)
{
@@ -193,12 +181,6 @@ static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw,
hw->clk_conf_force_on.clk_coex_fo = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en)
{
hw->clk_conf_force_on.clk_i2c_mst_fo = en;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_enable_ble_rtc_timer_force_clock(modem_lpcon_dev_t *hw, bool en)
{
@@ -267,13 +249,6 @@ static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw)
hw->rst_conf.rst_coex = 0;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_reset_i2c_master(modem_lpcon_dev_t *hw)
{
hw->rst_conf.rst_i2c_mst = 1;
hw->rst_conf.rst_i2c_mst = 0;
}
__attribute__((always_inline))
static inline void modem_lpcon_ll_reset_ble_rtc_timer(modem_lpcon_dev_t *hw)
{

54
components/hal/esp32c5/include/hal/regi2c_ctrl_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,18 +10,54 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/regi2c_defs.h"
#include "modem/modem_lpcon_struct.h"
#include "modem/modem_syscon_struct.h"
#include "soc/i2c_ana_mst_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable analog I2C master clock
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_enable_clock(bool en)
{
MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
}
/**
* @brief Reset analog I2C master
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_reset(void)
{
MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
}
/**
* @brief Force enable analog I2C master clock
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en)
{
MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en;
}
/**
* @brief Configure analog I2C master clock
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void)
{
MODEM_SYSCON.clk_conf.clk_i2c_mst_sel_160m = 1;
}
/**
* @brief Start BBPLL self-calibration
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
{
REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
}
/**
@@ -29,8 +65,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
*/
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void)
{
REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
}
/**
@@ -40,7 +76,7 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
*/
static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void)
{
return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
}
/**
@@ -48,8 +84,7 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
*/
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
{
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
// TODO: IDF-8727
}
/**
@@ -57,8 +92,7 @@ static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
*/
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
{
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
// TODO: IDF-8727
}
#ifdef __cplusplus