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Merge branch 'feature/p4_reset_reason' into 'master'

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system: support reset reason on esp32p4

Closes IDF-8072 and IDF-7791

See merge request espressif/esp-idf!25693
This commit is contained in:
Marius Vikhammer
2023-09-15 15:25:03 +08:00
parent c1342d3347 e58becec0a
commit addfc0d870
10 changed files with 121 additions and 84 deletions
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38
components/soc/esp32p4/include/soc/reset_reasons.h
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@@ -22,31 +22,29 @@
extern "C" {
#endif
// TODO: IDF-7791
/**
* @brief Naming conventions: RESET_REASON_{reset level}_{reset reason}
* @note refer to TRM: <Reset and Clock> chapter
*/
typedef enum {
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CHIP_BROWN_OUT = 0x01, // VDD voltage is not stable and resets the chip
RESET_REASON_CHIP_SUPER_WDT = 0x01, // Super watch dog resets the chip
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core by RTC_CNTL_SW_SYS_RST
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core
RESET_REASON_CORE_MWDT0 = 0x07, // Main watch dog 0 resets digital core
RESET_REASON_CORE_MWDT1 = 0x08, // Main watch dog 1 resets digital core
RESET_REASON_CORE_RTC_WDT = 0x09, // RTC watch dog resets digital core
RESET_REASON_CPU0_MWDT0 = 0x0B, // Main watch dog 0 resets CPU 0
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0 by RTC_CNTL_SW_PROCPU_RST
RESET_REASON_CPU0_RTC_WDT = 0x0D, // RTC watch dog resets CPU 0
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_SYS_RTC_WDT = 0x10, // RTC watch dog resets digital core and rtc module
RESET_REASON_CPU0_MWDT1 = 0x11, // Main watch dog 1 resets CPU 0
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_PWR_GLITCH = 0x17, // Glitch on power resets the digital core
RESET_REASON_CHIP_POWER_ON = 0x01, // Power on reset
RESET_REASON_CORE_SW = 0x03, // Software resets the digital core
RESET_REASON_CORE_DEEP_SLEEP = 0x05, // Deep sleep reset the digital core, check when doing sleep bringup if 0x5/0x6 is deepsleep wakeup TODO IDF-7529
RESET_REASON_SYS_PMU_PWR_DOWN = 0x05, // PMU HP power down system reset
RESET_REASON_CPU_PMU_PWR_DOWN = 0x06, // PMU HP power down CPU reset
RESET_REASON_SYS_HP_WDT = 0x07, // HP WDT resets system
RESET_REASON_SYS_LP_WDT = 0x09, // LP WDT resets system
RESET_REASON_CORE_HP_WDT = 0x0B, // HP WDT resets digital core
RESET_REASON_CPU0_SW = 0x0C, // Software resets CPU 0
RESET_REASON_CORE_LP_WDT = 0x0D, // LP WDT resets digital core
RESET_REASON_SYS_BROWN_OUT = 0x0F, // VDD voltage is not stable and resets the digital core
RESET_REASON_CHIP_LP_WDT = 0x10, // LP WDT resets chip
RESET_REASON_SYS_SUPER_WDT = 0x12, // Super watch dog resets the digital core and rtc module
RESET_REASON_SYS_CLK_GLITCH = 0x13, // Glitch on clock resets the digital core and rtc module
RESET_REASON_CORE_EFUSE_CRC = 0x14, // eFuse CRC error resets the digital core
RESET_REASON_CORE_USB_JTAG = 0x16, // USB Serial/JTAG controller's JTAG resets the digital core
RESET_REASON_CORE_USB_UART = 0x17, // USB Serial/JTAG controller's UART resets the digital core
RESET_REASON_CPU_JTAG = 0x18, // Glitch on power resets the digital core
} soc_reset_reason_t;