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i2s: impove the clock division calculation

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Reported from: https://esp32.com/viewtopic.php?f=25&t=24542&p=87595#p87595
This commit is contained in:
laokaiyao
2021-11-24 16:08:00 +08:00
parent 355e8bba76
commit af4e448928
11 changed files with 157 additions and 252 deletions
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19
components/soc/esp32s3/include/soc/rtc.h
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@@ -157,7 +157,6 @@ typedef enum {
RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M)
RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator
RTC_CPU_FREQ_SRC_APLL //!< APLL
} rtc_cpu_freq_src_t;
/**
@@ -371,24 +370,6 @@ bool rtc_clk_8m_enabled(void);
*/
bool rtc_clk_8md256_enabled(void);
/**
* @brief Enable or disable APLL
*
* Output frequency is given by the formula:
* apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
*
* The dividend in this expression should be in the range of 240 - 600 MHz.
*
* In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
*
* @param enable true to enable, false to disable
* @param sdm0 frequency adjustment parameter, 0..255
* @param sdm1 frequency adjustment parameter, 0..255
* @param sdm2 frequency adjustment parameter, 0..63
* @param o_div frequency divider, 0..31
*/
void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
/**
* @brief Select source for RTC_SLOW_CLK
* @param slow_freq clock source (one of rtc_slow_freq_t values)