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tools: Mass fixing of empty prototypes (for -Wstrict-prototypes)

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This commit is contained in:
Anton Maklakov
2019-07-16 16:33:30 +07:00
parent 50629eec27
commit afbaf74007
507 changed files with 1295 additions and 1295 deletions
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4
components/esp32/brownout.c
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@@ -31,7 +31,7 @@
#define BROWNOUT_DET_LVL 0
#endif //CONFIG_ESP32_BROWNOUT_DET_LVL
static void rtc_brownout_isr_handler()
static void rtc_brownout_isr_handler(void)
{
/* Normally RTC ISR clears the interrupt flag after the application-supplied
* handler returns. Since restart is called here, the flag needs to be
@@ -47,7 +47,7 @@ static void rtc_brownout_isr_handler()
esp_restart_noos();
}
void esp_brownout_init()
void esp_brownout_init(void)
{
REG_WRITE(RTC_CNTL_BROWN_OUT_REG,
RTC_CNTL_BROWN_OUT_ENA /* Enable BOD */

4
components/esp32/cache_err_int.c
View File

@@ -30,7 +30,7 @@
#include "soc/dport_reg.h"
#include "sdkconfig.h"
void esp_cache_err_int_init()
void esp_cache_err_int_init(void)
{
uint32_t core_id = xPortGetCoreID();
ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
@@ -70,7 +70,7 @@ void esp_cache_err_int_init()
ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
}
int IRAM_ATTR esp_cache_err_get_cpuid()
int IRAM_ATTR esp_cache_err_get_cpuid(void)
{
esp_dport_access_int_pause();
const uint32_t pro_mask =

2
components/esp32/clk.c
View File

@@ -210,7 +210,7 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
esp_clk_slowclk_cal_set(cal_val);
}
void rtc_clk_select_rtc_slow_clk()
void rtc_clk_select_rtc_slow_clk(void)
{
select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
}

8
components/esp32/cpu_start.c
View File

@@ -79,7 +79,7 @@
void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
void start_cpu0_default(void) IRAM_ATTR __attribute__((noreturn));
#if !CONFIG_FREERTOS_UNICORE
static void IRAM_ATTR call_start_cpu1() __attribute__((noreturn));
static void IRAM_ATTR call_start_cpu1(void) __attribute__((noreturn));
void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default"))) __attribute__((noreturn));
void start_cpu1_default(void) IRAM_ATTR __attribute__((noreturn));
static bool app_cpu_started = false;
@@ -117,7 +117,7 @@ static bool s_spiram_okay=true;
* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
*/
void IRAM_ATTR call_start_cpu0()
void IRAM_ATTR call_start_cpu0(void)
{
#if CONFIG_FREERTOS_UNICORE
RESET_REASON rst_reas[1];
@@ -277,7 +277,7 @@ static void wdt_reset_cpu1_info_enable(void)
DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
}
void IRAM_ATTR call_start_cpu1()
void IRAM_ATTR call_start_cpu1(void)
{
asm volatile (\
"wsr %0, vecbase\n" \
@@ -484,7 +484,7 @@ void start_cpu1_default(void)
#endif //!CONFIG_FREERTOS_UNICORE
#ifdef CONFIG_COMPILER_CXX_EXCEPTIONS
size_t __cxx_eh_arena_size_get()
size_t __cxx_eh_arena_size_get(void)
{
return CONFIG_COMPILER_CXX_EXCEPTIONS_EMG_POOL_SIZE;
}

4
components/esp32/crosscore_int.c
View File

@@ -43,7 +43,7 @@ static volatile uint32_t reason[ portNUM_PROCESSORS ];
ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
*/
static inline void IRAM_ATTR esp_crosscore_isr_handle_yield()
static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
{
portYIELD_FROM_ISR();
}
@@ -79,7 +79,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
//Initialize the crosscore interrupt on this core. Call this once
//on each active core.
void esp_crosscore_int_init() {
void esp_crosscore_int_init(void) {
portENTER_CRITICAL(&reason_spinlock);
reason[xPortGetCoreID()]=0;
portEXIT_CRITICAL(&reason_spinlock);

2
components/esp32/esp_clk_internal.h
View File

@@ -41,4 +41,4 @@ void esp_perip_clk_init(void);
/* Selects an external clock source (32 kHz) for RTC.
* Only internal use in unit test.
*/
void rtc_clk_select_rtc_slow_clk();
void rtc_clk_select_rtc_slow_clk(void);

8
components/esp32/esp_himem.c
View File

@@ -117,13 +117,13 @@ static void set_bank(int virt_bank, int phys_bank, int ct)
assert(r == 0);
}
size_t esp_himem_get_phys_size()
size_t esp_himem_get_phys_size(void)
{
int paddr_start = (4096 * 1024) - (CACHE_BLOCKSIZE * SPIRAM_BANKSWITCH_RESERVE);
return esp_spiram_get_size()-paddr_start;
}
size_t esp_himem_get_free_size()
size_t esp_himem_get_free_size(void)
{
size_t ret=0;
for (int i = 0; i < s_ramblockcnt; i++) {
@@ -132,12 +132,12 @@ size_t esp_himem_get_free_size()
return ret;
}
size_t esp_himem_reserved_area_size() {
size_t esp_himem_reserved_area_size(void) {
return CACHE_BLOCKSIZE * SPIRAM_BANKSWITCH_RESERVE;
}
void __attribute__((constructor)) esp_himem_init()
void __attribute__((constructor)) esp_himem_init(void)
{
if (SPIRAM_BANKSWITCH_RESERVE == 0) return;
int maxram=esp_spiram_get_size();

14
components/esp32/esp_timer_esp32.c
View File

@@ -150,7 +150,7 @@ portMUX_TYPE s_time_update_lock = portMUX_INITIALIZER_UNLOCKED;
#define TIMER_IS_AFTER_OVERFLOW(a) (ALARM_OVERFLOW_VAL < (a) && (a) <= FRC_TIMER_LOAD_VALUE(1))
// Check if timer overflow has happened (but was not handled by ISR yet)
static inline bool IRAM_ATTR timer_overflow_happened()
static inline bool IRAM_ATTR timer_overflow_happened(void)
{
if (s_overflow_happened) {
return true;
@@ -176,17 +176,17 @@ static inline void IRAM_ATTR timer_count_reload(void)
REG_WRITE(FRC_TIMER_LOAD_REG(1), REG_READ(FRC_TIMER_COUNT_REG(1)) - ALARM_OVERFLOW_VAL);
}
void esp_timer_impl_lock()
void esp_timer_impl_lock(void)
{
portENTER_CRITICAL(&s_time_update_lock);
}
void esp_timer_impl_unlock()
void esp_timer_impl_unlock(void)
{
portEXIT_CRITICAL(&s_time_update_lock);
}
uint64_t IRAM_ATTR esp_timer_impl_get_time()
uint64_t IRAM_ATTR esp_timer_impl_get_time(void)
{
uint32_t timer_val;
uint64_t time_base;
@@ -371,7 +371,7 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)
return ESP_OK;
}
void esp_timer_impl_deinit()
void esp_timer_impl_deinit(void)
{
esp_intr_disable(s_timer_interrupt_handle);
@@ -386,13 +386,13 @@ void esp_timer_impl_deinit()
// FIXME: This value is safe for 80MHz APB frequency.
// Should be modified to depend on clock frequency.
uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us()
uint64_t IRAM_ATTR esp_timer_impl_get_min_period_us(void)
{
return 50;
}
#ifdef ESP_TIMER_DYNAMIC_OVERFLOW_VAL
uint32_t esp_timer_impl_get_overflow_val()
uint32_t esp_timer_impl_get_overflow_val(void)
{
return s_alarm_overflow_val;
}

2
components/esp32/include/esp32/brownout.h
View File

@@ -16,6 +16,6 @@
#ifndef __ESP_BROWNOUT_H
#define __ESP_BROWNOUT_H
void esp_brownout_init();
void esp_brownout_init(void);
#endif

4
components/esp32/include/esp32/cache_err_int.h
View File

@@ -20,7 +20,7 @@
* to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
* from the startup code.
*/
void esp_cache_err_int_init();
void esp_cache_err_int_init(void);
/**
@@ -30,4 +30,4 @@ void esp_cache_err_int_init();
* - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
* - (-1) otherwise
*/
int esp_cache_err_get_cpuid();
int esp_cache_err_get_cpuid(void);

4
components/esp32/include/esp32/clk.h
View File

@@ -29,7 +29,7 @@
*
* @return the calibration value obtained using rtc_clk_cal, at startup time
*/
uint32_t esp_clk_slowclk_cal_get();
uint32_t esp_clk_slowclk_cal_get(void);
/**
* @brief Update the calibration value of RTC slow clock
@@ -84,4 +84,4 @@ int esp_clk_xtal_freq(void);
*
* @return Value or RTC counter, expressed in microseconds
*/
uint64_t esp_clk_rtc_time();
uint64_t esp_clk_rtc_time(void);

6
components/esp32/include/esp32/himem.h
View File

@@ -125,14 +125,14 @@ esp_err_t esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len);
*
* @returns Amount of memory, in bytes
*/
size_t esp_himem_get_phys_size();
size_t esp_himem_get_phys_size(void);
/**
* @brief Get free amount of memory under control of himem API
*
* @returns Amount of free memory, in bytes
*/
size_t esp_himem_get_free_size();
size_t esp_himem_get_free_size(void);
/**
@@ -143,7 +143,7 @@ size_t esp_himem_get_free_size();
*
* @returns Amount of reserved area, in bytes
*/
size_t esp_himem_reserved_area_size();
size_t esp_himem_reserved_area_size(void);
#ifdef __cplusplus

14
components/esp32/include/esp32/spiram.h
View File

@@ -34,14 +34,14 @@ typedef enum {
* - ESP_SPIRAM_SIZE_INVALID if SPI RAM not enabled or not valid
* - SPI RAM size
*/
esp_spiram_size_t esp_spiram_get_chip_size();
esp_spiram_size_t esp_spiram_get_chip_size(void);
/**
* @brief Initialize spiram interface/hardware. Normally called from cpu_start.c.
*
* @return ESP_OK on success
*/
esp_err_t esp_spiram_init();
esp_err_t esp_spiram_init(void);
/**
* @brief Configure Cache/MMU for access to external SPI RAM.
@@ -52,7 +52,7 @@ esp_err_t esp_spiram_init();
*
* @attention this function must be called with flash cache disabled.
*/
void esp_spiram_init_cache();
void esp_spiram_init_cache(void);
/**
@@ -63,13 +63,13 @@ void esp_spiram_init_cache();
*
* @return true on success, false on failed memory test
*/
bool esp_spiram_test();
bool esp_spiram_test(void);
/**
* @brief Add the initialized SPI RAM to the heap allocator.
*/
esp_err_t esp_spiram_add_to_heapalloc();
esp_err_t esp_spiram_add_to_heapalloc(void);
/**
@@ -77,7 +77,7 @@ esp_err_t esp_spiram_add_to_heapalloc();
*
* @return Size in bytes, or 0 if no external RAM chip support compiled in.
*/
size_t esp_spiram_get_size();
size_t esp_spiram_get_size(void);
/**
@@ -87,7 +87,7 @@ size_t esp_spiram_get_size();
*
* This is meant for use from within the SPI flash code.
*/
void esp_spiram_writeback_cache();
void esp_spiram_writeback_cache(void);

4
components/esp32/include/esp_intr_alloc.h
View File

@@ -282,13 +282,13 @@ esp_err_t esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram);
/**
* @brief Disable interrupts that aren't specifically marked as running from IRAM
*/
void esp_intr_noniram_disable();
void esp_intr_noniram_disable(void);
/**
* @brief Re-enable interrupts disabled by esp_intr_noniram_disable
*/
void esp_intr_noniram_enable();
void esp_intr_noniram_enable(void);
/**@}*/

16
components/esp32/include/esp_sleep.h
View File

@@ -98,7 +98,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source);
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled.
* - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
*/
esp_err_t esp_sleep_enable_ulp_wakeup();
esp_err_t esp_sleep_enable_ulp_wakeup(void);
/**
* @brief Enable wakeup by timer
@@ -125,7 +125,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
* - ESP_ERR_NOT_SUPPORTED if additional current by touch (CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) is enabled.
* - ESP_ERR_INVALID_STATE if wakeup triggers conflict
*/
esp_err_t esp_sleep_enable_touchpad_wakeup();
esp_err_t esp_sleep_enable_touchpad_wakeup(void);
/**
* @brief Get the touch pad which caused wakeup
@@ -134,7 +134,7 @@ esp_err_t esp_sleep_enable_touchpad_wakeup();
*
* @return touch pad which caused wakeup
*/
touch_pad_t esp_sleep_get_touchpad_wakeup_status();
touch_pad_t esp_sleep_get_touchpad_wakeup_status(void);
/**
* @brief Enable wakeup using a pin
@@ -213,7 +213,7 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode
* - ESP_OK on success
* - ESP_ERR_INVALID_STATE if wakeup triggers conflict
*/
esp_err_t esp_sleep_enable_gpio_wakeup();
esp_err_t esp_sleep_enable_gpio_wakeup(void);
/**
* @brief Enable wakeup from light sleep using UART
@@ -239,7 +239,7 @@ esp_err_t esp_sleep_enable_uart_wakeup(int uart_num);
*
* @return bit mask, if GPIOn caused wakeup, BIT(n) will be set
*/
uint64_t esp_sleep_get_ext1_wakeup_status();
uint64_t esp_sleep_get_ext1_wakeup_status(void);
/**
* @brief Set power down mode for an RTC power domain in sleep mode
@@ -260,7 +260,7 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
*
* This function does not return.
*/
void esp_deep_sleep_start() __attribute__((noreturn));
void esp_deep_sleep_start(void) __attribute__((noreturn));
/**
* @brief Enter light sleep with the configured wakeup options
@@ -269,7 +269,7 @@ void esp_deep_sleep_start() __attribute__((noreturn));
* - ESP_OK on success (returned after wakeup)
* - ESP_ERR_INVALID_STATE if WiFi or BT is not stopped
*/
esp_err_t esp_light_sleep_start();
esp_err_t esp_light_sleep_start(void);
/**
* @brief Enter deep-sleep mode
@@ -311,7 +311,7 @@ void system_deep_sleep(uint64_t time_in_us) __attribute__((noreturn, deprecated)
*
* @return cause of wake up from last sleep (deep sleep or light sleep)
*/
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause();
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void);
/**

4
components/esp32/int_wdt.c
View File

@@ -69,7 +69,7 @@ static void IRAM_ATTR tick_hook(void) {
#endif
void esp_int_wdt_init() {
void esp_int_wdt_init(void) {
periph_module_enable(PERIPH_TIMG1_MODULE);
TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
TIMERG1.wdt_config0.sys_reset_length=7; //3.2uS
@@ -89,7 +89,7 @@ void esp_int_wdt_init() {
timer_group_intr_enable(TIMER_GROUP_1, TIMG_WDT_INT_ENA_M);
}
void esp_int_wdt_cpu_init()
void esp_int_wdt_cpu_init(void)
{
esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
ESP_INTR_DISABLE(WDT_INT_NUM);

4
components/esp32/intr_alloc.c
View File

@@ -854,7 +854,7 @@ esp_err_t IRAM_ATTR esp_intr_disable(intr_handle_t handle)
}
void IRAM_ATTR esp_intr_noniram_disable()
void IRAM_ATTR esp_intr_noniram_disable(void)
{
int oldint;
int cpu=xPortGetCoreID();
@@ -873,7 +873,7 @@ void IRAM_ATTR esp_intr_noniram_disable()
non_iram_int_disabled[cpu]=oldint&non_iram_int_mask[cpu];
}
void IRAM_ATTR esp_intr_noniram_enable()
void IRAM_ATTR esp_intr_noniram_enable(void)
{
int cpu=xPortGetCoreID();
int intmask=non_iram_int_disabled[cpu];

16
components/esp32/panic.c
View File

@@ -139,7 +139,7 @@ esp_reset_reason_t __attribute__((weak)) esp_reset_reason_get_hint(void)
static bool abort_called;
static __attribute__((noreturn)) inline void invoke_abort()
static __attribute__((noreturn)) inline void invoke_abort(void)
{
abort_called = true;
#if CONFIG_ESP32_APPTRACE_ENABLE
@@ -158,7 +158,7 @@ static __attribute__((noreturn)) inline void invoke_abort()
}
}
void abort()
void abort(void)
{
#if !CONFIG_ESP32_PANIC_SILENT_REBOOT
ets_printf("abort() was called at PC 0x%08x on core %d\r\n", (intptr_t)__builtin_return_address(0) - 3, xPortGetCoreID());
@@ -189,12 +189,12 @@ static const char *edesc[] = {
#define NUM_EDESCS (sizeof(edesc) / sizeof(char *))
static void commonErrorHandler(XtExcFrame *frame);
static inline void disableAllWdts();
static inline void disableAllWdts(void);
static void illegal_instruction_helper(XtExcFrame *frame);
//The fact that we've panic'ed probably means the other CPU is now running wild, possibly
//messing up the serial output, so we stall it here.
static void haltOtherCore()
static void haltOtherCore(void)
{
esp_cpu_stall( xPortGetCoreID() == 0 ? 1 : 0 );
}
@@ -399,7 +399,7 @@ static void illegal_instruction_helper(XtExcFrame *frame)
all watchdogs except the timer group 0 watchdog, and it reconfigures that to reset the chip after
one second.
*/
static void reconfigureAllWdts()
static void reconfigureAllWdts(void)
{
TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
TIMERG0.wdt_feed = 1;
@@ -419,7 +419,7 @@ static void reconfigureAllWdts()
/*
This disables all the watchdogs for when we call the gdbstub.
*/
static inline void disableAllWdts()
static inline void disableAllWdts(void)
{
TIMERG0.wdt_wprotect = TIMG_WDT_WKEY_VALUE;
TIMERG0.wdt_config0.en = 0;
@@ -429,9 +429,9 @@ static inline void disableAllWdts()
TIMERG1.wdt_wprotect = 0;
}
static void esp_panic_dig_reset() __attribute__((noreturn));
static void esp_panic_dig_reset(void) __attribute__((noreturn));
static void esp_panic_dig_reset()
static void esp_panic_dig_reset(void)
{
// make sure all the panic handler output is sent from UART FIFO
uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);

18
components/esp32/pm_esp32.c
View File

@@ -145,9 +145,9 @@ static const char* s_mode_names[] = {
static const char* TAG = "pm_esp32";
static void update_ccompare();
static void update_ccompare(void);
static void do_switch(pm_mode_t new_mode);
static void leave_idle();
static void leave_idle(void);
static void on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us);
@@ -246,7 +246,7 @@ esp_err_t esp_pm_configure(const void* vconfig)
return ESP_OK;
}
static pm_mode_t IRAM_ATTR get_lowest_allowed_mode()
static pm_mode_t IRAM_ATTR get_lowest_allowed_mode(void)
{
/* TODO: optimize using ffs/clz */
if (s_mode_mask >= BIT(PM_MODE_CPU_MAX)) {
@@ -418,7 +418,7 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
* would happen without the frequency change.
* Assumes that the new_frequency = old_frequency * s_ccount_mul / s_ccount_div.
*/
static void IRAM_ATTR update_ccompare()
static void IRAM_ATTR update_ccompare(void)
{
uint32_t ccount = XTHAL_GET_CCOUNT();
uint32_t ccompare = XTHAL_GET_CCOMPARE(XT_TIMER_INDEX);
@@ -432,7 +432,7 @@ static void IRAM_ATTR update_ccompare()
}
}
static void IRAM_ATTR leave_idle()
static void IRAM_ATTR leave_idle(void)
{
int core_id = xPortGetCoreID();
if (s_core_idle[core_id]) {
@@ -442,7 +442,7 @@ static void IRAM_ATTR leave_idle()
}
}
void esp_pm_impl_idle_hook()
void esp_pm_impl_idle_hook(void)
{
int core_id = xPortGetCoreID();
uint32_t state = portENTER_CRITICAL_NESTED();
@@ -454,7 +454,7 @@ void esp_pm_impl_idle_hook()
ESP_PM_TRACE_ENTER(IDLE, core_id);
}
void IRAM_ATTR esp_pm_impl_isr_hook()
void IRAM_ATTR esp_pm_impl_isr_hook(void)
{
int core_id = xPortGetCoreID();
ESP_PM_TRACE_ENTER(ISR_HOOK, core_id);
@@ -476,7 +476,7 @@ void IRAM_ATTR esp_pm_impl_isr_hook()
ESP_PM_TRACE_EXIT(ISR_HOOK, core_id);
}
void esp_pm_impl_waiti()
void esp_pm_impl_waiti(void)
{
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
int core_id = xPortGetCoreID();
@@ -595,7 +595,7 @@ void esp_pm_impl_dump_stats(FILE* out)
}
#endif // WITH_PROFILING
void esp_pm_impl_init()
void esp_pm_impl_init(void)
{
#ifdef CONFIG_PM_TRACE
esp_pm_trace_init();

2
components/esp32/pm_trace.c
View File

@@ -29,7 +29,7 @@ static const int DRAM_ATTR s_trace_io[] = {
BIT(27), BIT(27), // ESP_PM_TRACE_SLEEP
};
void esp_pm_trace_init()
void esp_pm_trace_init(void)
{
for (size_t i = 0; i < sizeof(s_trace_io)/sizeof(s_trace_io[0]); ++i) {
int io = __builtin_ffs(s_trace_io[i]);

4
components/esp32/reset_reason.c
View File

@@ -17,7 +17,7 @@
#include "esp_private/system_internal.h"
#include "soc/rtc_periph.h"
static void esp_reset_reason_clear_hint();
static void esp_reset_reason_clear_hint(void);
static esp_reset_reason_t s_reset_reason;
@@ -119,7 +119,7 @@ esp_reset_reason_t IRAM_ATTR esp_reset_reason_get_hint(void)
}
return (esp_reset_reason_t) low;
}
static void esp_reset_reason_clear_hint()
static void esp_reset_reason_clear_hint(void)
{
REG_WRITE(RTC_RESET_CAUSE_REG, 0);
}

38
components/esp32/sleep_modes.c
View File

@@ -89,10 +89,10 @@ static _lock_t lock_rtc_memory_crc;
static const char* TAG = "sleep";
static uint32_t get_power_down_flags();
static void ext0_wakeup_prepare();
static void ext1_wakeup_prepare();
static void timer_wakeup_prepare();
static uint32_t get_power_down_flags(void);
static void ext0_wakeup_prepare(void);
static void ext1_wakeup_prepare(void);
static void timer_wakeup_prepare(void);
/* Wake from deep sleep stub
See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
@@ -148,14 +148,14 @@ void esp_deep_sleep(uint64_t time_in_us)
esp_deep_sleep_start();
}
static void IRAM_ATTR flush_uarts()
static void IRAM_ATTR flush_uarts(void)
{
for (int i = 0; i < 3; ++i) {
uart_tx_wait_idle(i);
}
}
static void IRAM_ATTR suspend_uarts()
static void IRAM_ATTR suspend_uarts(void)
{
for (int i = 0; i < 3; ++i) {
REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
@@ -165,7 +165,7 @@ static void IRAM_ATTR suspend_uarts()
}
}
static void IRAM_ATTR resume_uarts()
static void IRAM_ATTR resume_uarts(void)
{
for (int i = 0; i < 3; ++i) {
REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
@@ -222,7 +222,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
return result;
}
void IRAM_ATTR esp_deep_sleep_start()
void IRAM_ATTR esp_deep_sleep_start(void)
{
// record current RTC time
s_config.rtc_ticks_at_sleep_start = rtc_time_get();
@@ -277,7 +277,7 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
return err;
}
esp_err_t esp_light_sleep_start()
esp_err_t esp_light_sleep_start(void)
{
static portMUX_TYPE light_sleep_lock = portMUX_INITIALIZER_UNLOCKED;
portENTER_CRITICAL(&light_sleep_lock);
@@ -399,7 +399,7 @@ esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
return ESP_OK;
}
esp_err_t esp_sleep_enable_ulp_wakeup()
esp_err_t esp_sleep_enable_ulp_wakeup(void)
{
#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
return ESP_ERR_NOT_SUPPORTED;
@@ -423,7 +423,7 @@ esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us)
return ESP_OK;
}
static void timer_wakeup_prepare()
static void timer_wakeup_prepare(void)
{
uint32_t period = esp_clk_slowclk_cal_get();
int64_t sleep_duration = (int64_t) s_config.sleep_duration - (int64_t) s_config.sleep_time_adjustment;
@@ -435,7 +435,7 @@ static void timer_wakeup_prepare()
rtc_sleep_set_wakeup_time(s_config.rtc_ticks_at_sleep_start + rtc_count_delta);
}
esp_err_t esp_sleep_enable_touchpad_wakeup()
esp_err_t esp_sleep_enable_touchpad_wakeup(void)
{
#ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
return ESP_ERR_NOT_SUPPORTED;
@@ -448,7 +448,7 @@ esp_err_t esp_sleep_enable_touchpad_wakeup()
return ESP_OK;
}
touch_pad_t esp_sleep_get_touchpad_wakeup_status()
touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
{
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) {
return TOUCH_PAD_MAX;
@@ -477,7 +477,7 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
return ESP_OK;
}
static void ext0_wakeup_prepare()
static void ext0_wakeup_prepare(void)
{
int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
// Set GPIO to be used for wakeup
@@ -520,7 +520,7 @@ esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode
return ESP_OK;
}
static void ext1_wakeup_prepare()
static void ext1_wakeup_prepare(void)
{
// Configure all RTC IOs selected as ext1 wakeup inputs
uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
@@ -556,7 +556,7 @@ static void ext1_wakeup_prepare()
s_config.ext1_trigger_mode, RTC_CNTL_EXT_WAKEUP1_LV_S);
}
uint64_t esp_sleep_get_ext1_wakeup_status()
uint64_t esp_sleep_get_ext1_wakeup_status(void)
{
if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) {
return 0;
@@ -577,7 +577,7 @@ uint64_t esp_sleep_get_ext1_wakeup_status()
return gpio_mask;
}
esp_err_t esp_sleep_enable_gpio_wakeup()
esp_err_t esp_sleep_enable_gpio_wakeup(void)
{
if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
@@ -600,7 +600,7 @@ esp_err_t esp_sleep_enable_uart_wakeup(int uart_num)
return ESP_OK;
}
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause()
esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
{
if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET && !s_light_sleep_wakeup) {
return ESP_SLEEP_WAKEUP_UNDEFINED;
@@ -636,7 +636,7 @@ esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
return ESP_OK;
}
static uint32_t get_power_down_flags()
static uint32_t get_power_down_flags(void)
{
// Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.

20
components/esp32/spiram.c
View File

@@ -69,12 +69,12 @@ static bool spiram_inited=false;
//If no function in esp_himem.c is used, this function will be linked into the
//binary instead of the one in esp_himem.c, automatically making sure no memory
//is reserved if no himem function is used.
size_t __attribute__((weak)) esp_himem_reserved_area_size() {
size_t __attribute__((weak)) esp_himem_reserved_area_size(void) {
return 0;
}
static int spiram_size_usable_for_malloc()
static int spiram_size_usable_for_malloc(void)
{
int s=esp_spiram_get_size();
if (s>4*1024*1024) s=4*1024*1024; //we can map at most 4MiB
@@ -87,7 +87,7 @@ static int spiram_size_usable_for_malloc()
true when RAM seems OK, false when test fails. WARNING: Do not run this before the 2nd cpu has been
initialized (in a two-core system) or after the heap allocator has taken ownership of the memory.
*/
bool esp_spiram_test()
bool esp_spiram_test(void)
{
volatile int *spiram=(volatile int*)SOC_EXTRAM_DATA_LOW;
size_t p;
@@ -112,7 +112,7 @@ bool esp_spiram_test()
}
}
void IRAM_ATTR esp_spiram_init_cache()
void IRAM_ATTR esp_spiram_init_cache(void)
{
//Enable external RAM in MMU
cache_sram_mmu_set( 0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128 );
@@ -123,7 +123,7 @@ void IRAM_ATTR esp_spiram_init_cache()
#endif
}
esp_spiram_size_t esp_spiram_get_chip_size()
esp_spiram_size_t esp_spiram_get_chip_size(void)
{
if (!spiram_inited) {
ESP_EARLY_LOGE(TAG, "SPI RAM not initialized");
@@ -142,7 +142,7 @@ esp_spiram_size_t esp_spiram_get_chip_size()
}
}
esp_err_t esp_spiram_init()
esp_err_t esp_spiram_init(void)
{
esp_err_t r;
r = psram_enable(PSRAM_SPEED, PSRAM_MODE);
@@ -174,7 +174,7 @@ esp_err_t esp_spiram_init()
}
esp_err_t esp_spiram_add_to_heapalloc()
esp_err_t esp_spiram_add_to_heapalloc(void)
{
//Add entire external RAM region to heap allocator. Heap allocator knows the capabilities of this type of memory, so there's
//no need to explicitly specify them.
@@ -213,7 +213,7 @@ esp_err_t esp_spiram_reserve_dma_pool(size_t size) {
return ESP_OK;
}
size_t esp_spiram_get_size()
size_t esp_spiram_get_size(void)
{
psram_size_t size=esp_spiram_get_chip_size();
if (size==PSRAM_SIZE_16MBITS) return 2*1024*1024;
@@ -228,7 +228,7 @@ size_t esp_spiram_get_size()
Note that this routine assumes some unique mapping for the first 2 banks of the PSRAM memory range, as well as the
2 banks after the 2 MiB mark.
*/
void IRAM_ATTR esp_spiram_writeback_cache()
void IRAM_ATTR esp_spiram_writeback_cache(void)
{
int x;
volatile int i=0;
@@ -289,7 +289,7 @@ void IRAM_ATTR esp_spiram_writeback_cache()
* @return true SPI RAM has been initialized successfully
* @return false SPI RAM hasn't been initialized or initialized failed
*/
bool esp_spiram_is_initialized()
bool esp_spiram_is_initialized(void)
{
return spiram_inited;
}

2
components/esp32/spiram_psram.c
View File

@@ -596,7 +596,7 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_mode_t
}
}
psram_size_t psram_get_size()
psram_size_t psram_get_size(void)
{
if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
return PSRAM_SIZE_64MBITS;

2
components/esp32/spiram_psram.h
View File

@@ -53,7 +53,7 @@ typedef enum {
* - PSRAM_SIZE_MAX if psram not enabled or not valid
* - PSRAM size
*/
psram_size_t psram_get_size();
psram_size_t psram_get_size(void);
/**
* @brief psram cache enable function

6
components/esp32/system_api.c
View File

@@ -46,7 +46,7 @@ static uint8_t base_mac_addr[6] = { 0 };
#define SHUTDOWN_HANDLERS_NO 2
static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
void system_init()
void system_init(void)
{
}
@@ -232,7 +232,7 @@ esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
return ESP_ERR_INVALID_STATE;
}
void esp_restart_noos() __attribute__ ((noreturn));
void esp_restart_noos(void) __attribute__ ((noreturn));
void IRAM_ATTR esp_restart(void)
{
@@ -253,7 +253,7 @@ void IRAM_ATTR esp_restart(void)
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos()
void IRAM_ATTR esp_restart_noos(void)
{
// Disable interrupts
xt_ints_off(0xFFFFFFFF);

8
components/esp32/task_wdt.c
View File

@@ -104,7 +104,7 @@ static twdt_task_t *find_task_in_twdt_list(TaskHandle_t handle, bool *all_reset)
* Resets the hardware timer and has_reset flags of each task on the list.
* Called within critical
*/
static void reset_hw_timer()
static void reset_hw_timer(void)
{
//All tasks have reset; time to reset the hardware timer.
TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
@@ -229,7 +229,7 @@ esp_err_t esp_task_wdt_init(uint32_t timeout, bool panic)
return ESP_OK;
}
esp_err_t esp_task_wdt_deinit()
esp_err_t esp_task_wdt_deinit(void)
{
portENTER_CRITICAL(&twdt_spinlock);
//TWDT must already be initialized
@@ -297,7 +297,7 @@ esp_err_t esp_task_wdt_add(TaskHandle_t handle)
return ESP_OK;
}
esp_err_t esp_task_wdt_reset()
esp_err_t esp_task_wdt_reset(void)
{
portENTER_CRITICAL(&twdt_spinlock);
//TWDT must already be initialized
@@ -385,7 +385,7 @@ esp_err_t esp_task_wdt_status(TaskHandle_t handle)
return ESP_ERR_NOT_FOUND;
}
void esp_task_wdt_feed()
void esp_task_wdt_feed(void)
{
portENTER_CRITICAL(&twdt_spinlock);
//Return immediately if TWDT has not been initialized

2
components/esp32/test/test_4mpsram.c
View File

@@ -7,7 +7,7 @@
static const char TAG[] = "test_psram";
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
static void test_psram_content()
static void test_psram_content(void)
{
const int test_size = 2048;
uint32_t *test_area = heap_caps_malloc(test_size, MALLOC_CAP_SPIRAM);

4
components/esp32/test/test_ahb_arb.c
View File

@@ -31,7 +31,7 @@ to copy bytes over from one memory location to another. DO NOT USE the i2s routi
the point where they happened to do what I want.
*/
static void lcdIfaceInit()
static void lcdIfaceInit(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
@@ -99,7 +99,7 @@ static void lcdIfaceInit()
static volatile lldesc_t dmaDesc[2];
static void finishDma()
static void finishDma(void)
{
//No need to finish if no DMA transfer going on
if (!(READ_PERI_REG(I2S_FIFO_CONF_REG(0))&I2S_DSCR_EN)) {

8
components/esp32/test/test_esp_timer.c
View File

@@ -16,12 +16,12 @@
#define WITH_PROFILING 1
#endif
extern uint32_t esp_timer_impl_get_overflow_val();
extern uint32_t esp_timer_impl_get_overflow_val(void);
extern void esp_timer_impl_set_overflow_val(uint32_t overflow_val);
static uint32_t s_old_overflow_val;
static void setup_overflow()
static void setup_overflow(void)
{
s_old_overflow_val = esp_timer_impl_get_overflow_val();
/* Overflow every 0.1 sec.
@@ -31,7 +31,7 @@ static void setup_overflow()
esp_timer_impl_set_overflow_val(8000000);
}
static void teardown_overflow()
static void teardown_overflow(void)
{
esp_timer_impl_set_overflow_val(s_old_overflow_val);
}
@@ -409,7 +409,7 @@ TEST_CASE("esp_timer_get_time call takes less than 1us", "[esp_timer]")
TEST_PERFORMANCE_LESS_THAN(ESP_TIMER_GET_TIME_PER_CALL, "%dns", ns_per_call);
}
static int64_t IRAM_ATTR __attribute__((noinline)) get_clock_diff()
static int64_t IRAM_ATTR __attribute__((noinline)) get_clock_diff(void)
{
uint64_t hs_time = esp_timer_get_time();
uint64_t ref_time = ref_clock_get();

2
components/esp32/test/test_intr_alloc.c
View File

@@ -144,7 +144,7 @@ void int_timer_handler(void *arg) {
int_timer_ctr++;
}
void local_timer_test()
void local_timer_test(void)
{
intr_handle_t ih;
esp_err_t r;

4
components/esp32/test/test_pm.c
View File

@@ -58,7 +58,7 @@ TEST_CASE("Can switch frequency using esp_pm_configure", "[pm]")
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE
static void light_sleep_enable()
static void light_sleep_enable(void)
{
const esp_pm_config_esp32_t pm_config = {
.max_cpu_freq = rtc_clk_cpu_freq_get(),
@@ -68,7 +68,7 @@ static void light_sleep_enable()
ESP_ERROR_CHECK( esp_pm_configure(&pm_config) );
}
static void light_sleep_disable()
static void light_sleep_disable(void)
{
const esp_pm_config_esp32_t pm_config = {
.max_cpu_freq = rtc_clk_cpu_freq_get(),

36
components/esp32/test/test_reset_reason.c
View File

@@ -24,7 +24,7 @@ static RTC_FAST_ATTR uint32_t s_rtc_force_fast_val;
static RTC_SLOW_ATTR uint32_t s_rtc_force_slow_val;
static void setup_values()
static void setup_values(void)
{
s_noinit_val = CHECK_VALUE;
s_rtc_noinit_val = CHECK_VALUE;
@@ -44,14 +44,14 @@ TEST_CASE("reset reason ESP_RST_POWERON", "[reset][ignore]")
TEST_ASSERT_EQUAL(ESP_RST_POWERON, esp_reset_reason());
}
static void do_deep_sleep()
static void do_deep_sleep(void)
{
setup_values();
esp_sleep_enable_timer_wakeup(10000);
esp_deep_sleep_start();
}
static void check_reset_reason_deep_sleep()
static void check_reset_reason_deep_sleep(void)
{
TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
@@ -67,19 +67,19 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_DEEPSLEEP", "[reset_reason][rese
do_deep_sleep,
check_reset_reason_deep_sleep);
static void do_exception()
static void do_exception(void)
{
setup_values();
*(int*) (0x40000001) = 0;
}
static void do_abort()
static void do_abort(void)
{
setup_values();
abort();
}
static void check_reset_reason_panic()
static void check_reset_reason_panic(void)
{
TEST_ASSERT_EQUAL(ESP_RST_PANIC, esp_reset_reason());
@@ -100,14 +100,14 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_PANIC after abort", "[reset_reas
do_abort,
check_reset_reason_panic);
static void do_restart()
static void do_restart(void)
{
setup_values();
esp_restart();
}
#if portNUM_PROCESSORS > 1
static void do_restart_from_app_cpu()
static void do_restart_from_app_cpu(void)
{
setup_values();
xTaskCreatePinnedToCore((TaskFunction_t) &do_restart, "restart", 2048, NULL, 5, NULL, 1);
@@ -115,7 +115,7 @@ static void do_restart_from_app_cpu()
}
#endif
static void check_reset_reason_sw()
static void check_reset_reason_sw(void)
{
TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
@@ -139,21 +139,21 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_SW after restart from APP CPU",
#endif
static void do_int_wdt()
static void do_int_wdt(void)
{
setup_values();
portENTER_CRITICAL_NESTED();
while(1);
}
static void do_int_wdt_hw()
static void do_int_wdt_hw(void)
{
setup_values();
XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);
while(1);
}
static void check_reset_reason_int_wdt()
static void check_reset_reason_int_wdt(void)
{
TEST_ASSERT_EQUAL(ESP_RST_INT_WDT, esp_reset_reason());
TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
@@ -169,7 +169,7 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_INT_WDT after interrupt watchdog
do_int_wdt_hw,
check_reset_reason_int_wdt);
static void do_task_wdt()
static void do_task_wdt(void)
{
setup_values();
esp_task_wdt_init(1, true);
@@ -177,7 +177,7 @@ static void do_task_wdt()
while(1);
}
static void check_reset_reason_task_wdt()
static void check_reset_reason_task_wdt(void)
{
TEST_ASSERT_EQUAL(ESP_RST_TASK_WDT, esp_reset_reason());
@@ -195,7 +195,7 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_TASK_WDT after task watchdog",
do_task_wdt,
check_reset_reason_task_wdt);
static void do_rtc_wdt()
static void do_rtc_wdt(void)
{
setup_values();
WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
@@ -206,7 +206,7 @@ static void do_rtc_wdt()
while(1);
}
static void check_reset_reason_any_wdt()
static void check_reset_reason_any_wdt(void)
{
TEST_ASSERT_EQUAL(ESP_RST_WDT, esp_reset_reason());
TEST_ASSERT_EQUAL_HEX32(CHECK_VALUE, s_rtc_noinit_val);
@@ -218,14 +218,14 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_WDT after RTC watchdog",
check_reset_reason_any_wdt);
static void do_brownout()
static void do_brownout(void)
{
setup_values();
printf("Manual test: lower the supply voltage to cause brownout\n");
vTaskSuspend(NULL);
}
static void check_reset_reason_brownout()
static void check_reset_reason_brownout(void)
{
TEST_ASSERT_EQUAL(ESP_RST_BROWNOUT, esp_reset_reason());

20
components/esp32/test/test_sleep.c
View File

@@ -29,7 +29,7 @@ static void deep_sleep_task(void *arg)
esp_deep_sleep_start();
}
static void do_deep_sleep_from_app_cpu()
static void do_deep_sleep_from_app_cpu(void)
{
xTaskCreatePinnedToCore(&deep_sleep_task, "ds", 2048, NULL, 5, NULL, 1);
@@ -204,20 +204,20 @@ TEST_CASE("enter deep sleep on APP CPU and wake up using timer", "[deepsleep][re
}
#endif
static void do_deep_sleep()
static void do_deep_sleep(void)
{
esp_sleep_enable_timer_wakeup(100000);
esp_deep_sleep_start();
}
static void check_sleep_reset_and_sleep()
static void check_sleep_reset_and_sleep(void)
{
TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
esp_sleep_enable_timer_wakeup(100000);
esp_deep_sleep_start();
}
static void check_sleep_reset()
static void check_sleep_reset(void)
{
TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
}
@@ -228,12 +228,12 @@ TEST_CASE_MULTIPLE_STAGES("enter deep sleep more than once", "[deepsleep][reset=
check_sleep_reset_and_sleep,
check_sleep_reset);
static void do_abort()
static void do_abort(void)
{
abort();
}
static void check_abort_reset_and_sleep()
static void check_abort_reset_and_sleep(void)
{
TEST_ASSERT_EQUAL(ESP_RST_PANIC, esp_reset_reason());
esp_sleep_enable_timer_wakeup(100000);
@@ -247,20 +247,20 @@ TEST_CASE_MULTIPLE_STAGES("enter deep sleep after abort", "[deepsleep][reset=abo
static RTC_DATA_ATTR uint32_t s_wake_stub_var;
static RTC_IRAM_ATTR void wake_stub()
static RTC_IRAM_ATTR void wake_stub(void)
{
esp_default_wake_deep_sleep();
s_wake_stub_var = (uint32_t) &wake_stub;
}
static void prepare_wake_stub()
static void prepare_wake_stub(void)
{
esp_set_deep_sleep_wake_stub(&wake_stub);
esp_sleep_enable_timer_wakeup(100000);
esp_deep_sleep_start();
}
static void check_wake_stub()
static void check_wake_stub(void)
{
TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
TEST_ASSERT_EQUAL_HEX32((uint32_t) &wake_stub, s_wake_stub_var);
@@ -336,7 +336,7 @@ static float get_time_ms(void)
return fabs(dt);
}
static uint32_t get_cause()
static uint32_t get_cause(void)
{
uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, \
RTC_CNTL_WAKEUP_CAUSE);

2
components/esp32/test/test_stack_check.c
View File

@@ -2,7 +2,7 @@
#if CONFIG_COMPILER_STACK_CHECK
static void recur_and_smash()
static void recur_and_smash(void)
{
static int cnt;
volatile uint8_t buf[50];