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tools: Mass fixing of empty prototypes (for -Wstrict-prototypes)

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This commit is contained in:
Anton Maklakov
2019-07-16 16:33:30 +07:00
parent 50629eec27
commit afbaf74007
507 changed files with 1295 additions and 1295 deletions
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2
components/soc/esp32/cpu_util.c
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@@ -50,7 +50,7 @@ void IRAM_ATTR esp_cpu_reset(int cpu_id)
cpu_id == 0 ? RTC_CNTL_SW_PROCPU_RST_M : RTC_CNTL_SW_APPCPU_RST_M);
}
bool IRAM_ATTR esp_cpu_in_ocd_debug_mode()
bool IRAM_ATTR esp_cpu_in_ocd_debug_mode(void)
{
#if CONFIG_ESP32_DEBUG_OCDAWARE
int dcr;

8
components/soc/esp32/include/soc/cpu.h
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@@ -30,7 +30,7 @@
/** @brief Read current stack pointer address
*
*/
static inline void *get_sp()
static inline void *get_sp(void)
{
void *sp;
asm volatile ("mov %0, sp;" : "=r" (sp));
@@ -52,7 +52,7 @@ static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
}
static inline void cpu_init_memctl()
static inline void cpu_init_memctl(void)
{
#if XCHAL_ERRATUM_572
uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
@@ -71,7 +71,7 @@ static inline void cpu_init_memctl()
* 15 — no access, raise exception
*/
static inline void cpu_configure_region_protection()
static inline void cpu_configure_region_protection(void)
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
@@ -108,7 +108,7 @@ void esp_cpu_reset(int cpu_id);
* @note If "Make exception and panic handlers JTAG/OCD aware"
* is disabled, this function always returns false.
*/
bool esp_cpu_in_ocd_debug_mode();
bool esp_cpu_in_ocd_debug_mode(void);
/**
* @brief Convert the PC register value to its true address

28
components/soc/esp32/include/soc/rtc.h
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@@ -176,7 +176,7 @@ void rtc_clk_init(rtc_clk_config_t cfg);
*
* @return XTAL frequency, one of rtc_xtal_freq_t
*/
rtc_xtal_freq_t rtc_clk_xtal_freq_get();
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
/**
* @brief Update XTAL frequency
@@ -197,13 +197,13 @@ void rtc_clk_32k_enable(bool en);
/**
* @brief Configure 32 kHz XTAL oscillator to accept external clock signal
*/
void rtc_clk_32k_enable_external();
void rtc_clk_32k_enable_external(void);
/**
* @brief Get the state of 32k XTAL oscillator
* @return true if 32k XTAL oscillator has been enabled
*/
bool rtc_clk_32k_enabled();
bool rtc_clk_32k_enabled(void);
/**
* @brief Enable 32k oscillator, configuring it for fast startup time.
@@ -239,13 +239,13 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
* @brief Get the state of 8 MHz internal oscillator
* @return true if the oscillator is enabled
*/
bool rtc_clk_8m_enabled();
bool rtc_clk_8m_enabled(void);
/**
* @brief Get the state of /256 divider which is applied to 8MHz clock
* @return true if the divided output is enabled
*/
bool rtc_clk_8md256_enabled();
bool rtc_clk_8md256_enabled(void);
/**
* @brief Enable or disable APLL
@@ -276,7 +276,7 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
* @brief Get the RTC_SLOW_CLK source
* @return currently selected clock source (one of rtc_slow_freq_t values)
*/
rtc_slow_freq_t rtc_clk_slow_freq_get();
rtc_slow_freq_t rtc_clk_slow_freq_get(void);
/**
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
@@ -290,7 +290,7 @@ rtc_slow_freq_t rtc_clk_slow_freq_get();
*
* @return RTC_SLOW_CLK frequency, in Hz
*/
uint32_t rtc_clk_slow_freq_get_hz();
uint32_t rtc_clk_slow_freq_get_hz(void);
/**
* @brief Select source for RTC_FAST_CLK
@@ -302,7 +302,7 @@ void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
* @brief Get the RTC_FAST_CLK source
* @return currently selected clock source (one of rtc_fast_freq_t values)
*/
rtc_fast_freq_t rtc_clk_fast_freq_get();
rtc_fast_freq_t rtc_clk_fast_freq_get(void);
/**
* @brief Switch CPU frequency
@@ -355,7 +355,7 @@ void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq) __attribute__((deprecate
*
* @return CPU frequency (one of rtc_cpu_freq_t values)
*/
rtc_cpu_freq_t rtc_clk_cpu_freq_get() __attribute__((deprecated));
rtc_cpu_freq_t rtc_clk_cpu_freq_get(void) __attribute__((deprecated));
/**
* @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
@@ -444,7 +444,7 @@ uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) __attribute__((depreca
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
* Assumes that XTAL frequency has been determined — don't call in startup code.
*/
void rtc_clk_cpu_freq_set_xtal();
void rtc_clk_cpu_freq_set_xtal(void);
/**
@@ -465,7 +465,7 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq);
* @brief Get the current stored APB frequency.
* @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
*/
uint32_t rtc_clk_apb_freq_get();
uint32_t rtc_clk_apb_freq_get(void);
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
@@ -522,7 +522,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
*
* @return current value of RTC counter
*/
uint64_t rtc_time_get();
uint64_t rtc_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
@@ -531,7 +531,7 @@ uint64_t rtc_time_get();
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle();
void rtc_clk_wait_for_slow_cycle(void);
/**
* @brief sleep configuration for rtc_sleep_init function
@@ -710,7 +710,7 @@ typedef struct rtc_vddsdio_config_s {
* Otherwise, use default values and the level of MTDI bootstrapping pin.
* @return currently used VDDSDIO configuration
*/
rtc_vddsdio_config_t rtc_vddsdio_get_config();
rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
/**
* Set new VDDSDIO configuration using RTC registers.

36
components/soc/esp32/rtc_clk.c
View File

@@ -100,9 +100,9 @@
#define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480
static void rtc_clk_cpu_freq_to_8m();
static void rtc_clk_bbpll_disable();
static void rtc_clk_bbpll_enable();
static void rtc_clk_cpu_freq_to_8m(void);
static void rtc_clk_bbpll_disable(void);
static void rtc_clk_bbpll_enable(void);
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz);
static bool rtc_clk_cpu_freq_from_mhz_internal(int mhz, rtc_cpu_freq_t* out_val);
@@ -161,7 +161,7 @@ void rtc_clk_32k_enable(bool enable)
}
}
void rtc_clk_32k_enable_external()
void rtc_clk_32k_enable_external(void)
{
rtc_clk_32k_enable_common(XTAL_32K_EXT_DAC_VAL, XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL);
}
@@ -201,7 +201,7 @@ void rtc_clk_32k_bootstrap(uint32_t cycle)
XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
}
bool rtc_clk_32k_enabled()
bool rtc_clk_32k_enabled(void)
{
return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0;
}
@@ -224,12 +224,12 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
}
}
bool rtc_clk_8m_enabled()
bool rtc_clk_8m_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
}
bool rtc_clk_8md256_enabled()
bool rtc_clk_8md256_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
}
@@ -284,12 +284,12 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
ets_delay_us(DELAY_SLOW_CLK_SWITCH);
}
rtc_slow_freq_t rtc_clk_slow_freq_get()
rtc_slow_freq_t rtc_clk_slow_freq_get(void)
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
}
uint32_t rtc_clk_slow_freq_get_hz()
uint32_t rtc_clk_slow_freq_get_hz(void)
{
switch(rtc_clk_slow_freq_get()) {
case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
@@ -305,7 +305,7 @@ void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
ets_delay_us(DELAY_FAST_CLK_SWITCH);
}
rtc_fast_freq_t rtc_clk_fast_freq_get()
rtc_fast_freq_t rtc_clk_fast_freq_get(void)
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
}
@@ -435,7 +435,7 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
}
}
static void rtc_clk_cpu_freq_to_8m()
static void rtc_clk_cpu_freq_to_8m(void)
{
ets_update_cpu_frequency(8);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
@@ -444,7 +444,7 @@ static void rtc_clk_cpu_freq_to_8m()
rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
}
static void rtc_clk_bbpll_disable()
static void rtc_clk_bbpll_disable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
@@ -459,7 +459,7 @@ static void rtc_clk_bbpll_disable()
}
}
static void rtc_clk_bbpll_enable()
static void rtc_clk_bbpll_enable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
@@ -516,7 +516,7 @@ void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq)
rtc_clk_cpu_freq_set_config_fast(&config);
}
void rtc_clk_cpu_freq_set_xtal()
void rtc_clk_cpu_freq_set_xtal(void)
{
int freq_mhz = (int) rtc_clk_xtal_freq_get();
@@ -525,7 +525,7 @@ void rtc_clk_cpu_freq_set_xtal()
rtc_clk_bbpll_disable();
}
rtc_cpu_freq_t rtc_clk_cpu_freq_get()
rtc_cpu_freq_t rtc_clk_cpu_freq_get(void)
{
rtc_cpu_freq_config_t config;
rtc_clk_cpu_freq_get_config(&config);
@@ -766,7 +766,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config)
}
}
rtc_xtal_freq_t rtc_clk_xtal_freq_get()
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
/* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
@@ -790,7 +790,7 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq)
WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
}
uint32_t rtc_clk_apb_freq_get()
uint32_t rtc_clk_apb_freq_get(void)
{
uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
// round to the nearest MHz
@@ -802,4 +802,4 @@ uint32_t rtc_clk_apb_freq_get()
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/
rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get")));
rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));

4
components/soc/esp32/rtc_clk_init.c
View File

@@ -36,7 +36,7 @@
*/
#define XTAL_FREQ_EST_CYCLES 10
static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate();
static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void);
static const char* TAG = "rtc_clk_init";
@@ -140,7 +140,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
rtc_clk_slow_freq_set(cfg.slow_freq);
}
static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
{
/* Enable 8M/256 clock if needed */
const bool clk_8m_enabled = rtc_clk_8m_enabled();

2
components/soc/esp32/rtc_init.c
View File

@@ -97,7 +97,7 @@ void rtc_init(rtc_config_t cfg)
}
}
rtc_vddsdio_config_t rtc_vddsdio_get_config()
rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
{
rtc_vddsdio_config_t result;
uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);

8
components/soc/esp32/rtc_pm.c
View File

@@ -29,14 +29,14 @@ typedef enum{
/* These MAC-related functions are defined in the closed source part of
* RTC library
*/
extern void pm_mac_init();
extern int pm_check_mac_idle();
extern void pm_mac_deinit();
extern void pm_mac_init(void);
extern int pm_check_mac_idle(void);
extern void pm_mac_deinit(void);
/* This sleep-related function is called from the closed source part of RTC
* library.
*/
pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_params)())
pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_params)(void))
{
(void) pmac_save_params; /* unused */

4
components/soc/esp32/rtc_time.c
View File

@@ -140,7 +140,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
}
uint64_t rtc_time_get()
uint64_t rtc_time_get(void)
{
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
@@ -152,7 +152,7 @@ uint64_t rtc_time_get()
return t;
}
void rtc_clk_wait_for_slow_cycle()
void rtc_clk_wait_for_slow_cycle(void)
{
REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | TIMG_RTC_CALI_START);
REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY);

16
components/soc/esp32/rtc_wdt.c
View File

@@ -16,34 +16,34 @@
#include "soc/rtc.h"
bool rtc_wdt_get_protect_status()
bool rtc_wdt_get_protect_status(void)
{
return READ_PERI_REG(RTC_CNTL_WDTWPROTECT_REG) != RTC_CNTL_WDT_WKEY_VALUE;
}
void rtc_wdt_protect_off()
void rtc_wdt_protect_off(void)
{
WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
}
void rtc_wdt_protect_on()
void rtc_wdt_protect_on(void)
{
WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0);
}
void rtc_wdt_enable()
void rtc_wdt_enable(void)
{
REG_SET_BIT(RTC_CNTL_WDTFEED_REG, RTC_CNTL_WDT_FEED);
SET_PERI_REG_MASK(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN | RTC_CNTL_WDT_PAUSE_IN_SLP);
}
void rtc_wdt_flashboot_mode_enable()
void rtc_wdt_flashboot_mode_enable(void)
{
REG_SET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
}
void rtc_wdt_disable()
void rtc_wdt_disable(void)
{
bool protect = rtc_wdt_get_protect_status();
if (protect) {
@@ -61,7 +61,7 @@ void rtc_wdt_disable()
}
}
void rtc_wdt_feed()
void rtc_wdt_feed(void)
{
bool protect = rtc_wdt_get_protect_status();
if (protect) {
@@ -145,7 +145,7 @@ esp_err_t rtc_wdt_set_length_of_reset_signal(rtc_wdt_reset_sig_t reset_src, rtc_
return ESP_OK;
}
bool rtc_wdt_is_on()
bool rtc_wdt_is_on(void)
{
return (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_EN) != 0) || (REG_GET_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN) != 0);
}

2
components/soc/esp32/test/test_rtc_clk.c
View File

@@ -141,7 +141,7 @@ TEST_CASE("Test fast switching between PLL and XTAL", "[rtc_clk]")
#define COUNT_TEST 3
#define TIMEOUT_TEST_MS (5 + CONFIG_ESP32_RTC_CLK_CAL_CYCLES / 16)
void stop_rtc_external_quartz(){
void stop_rtc_external_quartz(void){
const uint8_t pin_32 = 32;
const uint8_t pin_33 = 33;
const uint8_t mask_32 = (1 << (pin_32 - 32));